Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2002689	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

37975846

1

T4

6101

T5

8868

T6

5680

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	28032361	1			T4	2397		T5	3269		T6	2423
values[0x0]	10417568	1			T4	3704		T5	5599		T6	3257
values[0x1]	1528606	1			T4	170		T5	228		T6	433

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	626061	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

39352474

1

T4

6271

T5

9096

T6

6113

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18826609	1			T4	3136		T5	4548		T6	3057
valid_sources[0x01]	18825448	1			T4	3135		T5	4548		T6	3056
valid_sources[0x02]	37071	1			T58	2		T126	152		T138	180
valid_sources[0x03]	36411	1			T126	168		T138	161		T139	780
valid_sources[0x04]	37368	1			T58	1		T7	1		T196	2
valid_sources[0x05]	37751	1			T58	1		T126	89		T138	260
valid_sources[0x06]	37419	1			T58	2		T7	1		T196	1
valid_sources[0x07]	39084	1			T126	189		T138	150		T139	808
valid_sources[0x08]	36885	1			T7	2		T126	111		T138	251
valid_sources[0x09]	37329	1			T7	1		T196	1		T126	170
valid_sources[0x0a]	37090	1			T7	1		T126	72		T138	185
valid_sources[0x0b]	37740	1			T58	1		T126	192		T138	213
valid_sources[0x0c]	37391	1			T7	2		T126	224		T138	218
valid_sources[0x0d]	36625	1			T58	1		T7	1		T196	2
valid_sources[0x0e]	42745	1			T7	2		T196	2		T126	118
valid_sources[0x0f]	36489	1			T58	3		T196	3		T126	88
valid_sources[0x10]	37011	1			T16	39		T196	2		T126	217
valid_sources[0x11]	36407	1			T7	3		T196	1		T126	202
valid_sources[0x12]	37619	1			T58	1		T7	1		T126	137
valid_sources[0x13]	36864	1			T7	1		T126	142		T138	170
valid_sources[0x14]	37579	1			T58	1		T126	142		T138	161
valid_sources[0x15]	37434	1			T126	205		T138	190		T139	790
valid_sources[0x16]	37199	1			T7	2		T126	120		T138	119
valid_sources[0x17]	38323	1			T58	3		T196	2		T126	153
valid_sources[0x18]	36869	1			T126	110		T138	150		T139	822
valid_sources[0x19]	37586	1			T58	2		T126	124		T138	93
valid_sources[0x1a]	37279	1			T126	102		T138	125		T139	743
valid_sources[0x1b]	37010	1			T58	3		T7	2		T126	230
valid_sources[0x1c]	37281	1			T7	1		T126	119		T138	208
valid_sources[0x1d]	40387	1			T126	139		T138	147		T139	829
valid_sources[0x1e]	38079	1			T126	209		T138	81		T139	809
valid_sources[0x1f]	37173	1			T58	1		T7	2		T126	186
valid_sources[0x20]	37998	1			T58	1		T126	184		T138	119

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27342001

1

T4

2397

T5

3269

T6

2423

values[0x0]

all_enables

biggest_size

10366432

1

T4

3704

T5

5599

T6

3257

values[0x1]

all_enables

biggest_size

267413

1

T16

22

T58

17

T7

19

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2963660	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

467455

1

T78

10

T79

1514

T80

29

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1162837	1			T78	45		T79	3588		T80	145
values[0x0]	1107751	1			T78	8		T79	3546		T80	29
values[0x1]	1160527	1			T78	32		T79	3577		T80	137

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2295615	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1135500

1

T78

33

T79

3511

T80

115

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53832	1			T79	146		T80	6		T673	8
valid_sources[0x01]	53482	1			T78	3		T79	161		T80	3
valid_sources[0x02]	52931	1			T78	1		T79	174		T80	2
valid_sources[0x03]	54185	1			T78	1		T79	170		T80	3
valid_sources[0x04]	54011	1			T79	209		T80	3		T673	8
valid_sources[0x05]	53707	1			T78	4		T79	122		T80	5
valid_sources[0x06]	52838	1			T78	6		T79	198		T80	5
valid_sources[0x07]	53521	1			T78	1		T79	168		T80	5
valid_sources[0x08]	53729	1			T79	170		T80	7		T673	6
valid_sources[0x09]	53134	1			T79	191		T80	3		T673	11
valid_sources[0x0a]	53846	1			T78	3		T79	190		T80	1
valid_sources[0x0b]	52387	1			T78	1		T79	153		T80	8
valid_sources[0x0c]	53506	1			T78	2		T79	128		T80	5
valid_sources[0x0d]	53286	1			T78	1		T79	175		T80	7
valid_sources[0x0e]	53882	1			T79	208		T80	4		T673	11
valid_sources[0x0f]	53544	1			T78	1		T79	140		T80	3
valid_sources[0x10]	53153	1			T79	168		T80	4		T673	10
valid_sources[0x11]	53005	1			T78	1		T79	177		T80	4
valid_sources[0x12]	53222	1			T79	157		T80	5		T673	10
valid_sources[0x13]	54811	1			T78	1		T79	175		T80	9
valid_sources[0x14]	53385	1			T79	174		T80	5		T673	13
valid_sources[0x15]	53917	1			T78	1		T79	205		T80	10
valid_sources[0x16]	53207	1			T78	3		T79	165		T80	9
valid_sources[0x17]	53546	1			T79	133		T80	4		T673	9
valid_sources[0x18]	52964	1			T78	1		T79	168		T80	7
valid_sources[0x19]	52887	1			T79	136		T80	4		T673	11
valid_sources[0x1a]	52678	1			T79	218		T80	4		T673	10
valid_sources[0x1b]	55065	1			T78	3		T79	187		T80	3
valid_sources[0x1c]	52791	1			T79	185		T80	5		T673	8
valid_sources[0x1d]	53069	1			T78	3		T79	188		T80	3
valid_sources[0x1e]	53481	1			T78	1		T79	152		T80	3
valid_sources[0x1f]	53672	1			T78	1		T79	155		T80	4
valid_sources[0x20]	52834	1			T78	1		T79	132		T80	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48686

1

T78

4

T79

163

T80

8

values[0x0]

all_enables

biggest_size

370247

1

T78

4

T79

1212

T80

10

values[0x1]

all_enables

biggest_size

48522

1

T78

2

T79

139

T80

11

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3163367	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

516815

1

T78

26

T79

1608

T80

32

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1258740	1			T78	83		T79	3913		T80	154
values[0x0]	1161535	1			T78	19		T79	3749		T80	27
values[0x1]	1259907	1			T78	99		T79	3752		T80	145

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2428315	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1251867

1

T78

83

T79

3876

T80

120

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	57944	1			T78	1		T79	128		T80	7
valid_sources[0x01]	56283	1			T78	4		T79	219		T80	3
valid_sources[0x02]	57628	1			T78	7		T79	214		T80	8
valid_sources[0x03]	57741	1			T78	4		T79	172		T80	3
valid_sources[0x04]	58492	1			T78	7		T79	185		T80	3
valid_sources[0x05]	58170	1			T78	5		T79	109		T80	6
valid_sources[0x06]	56048	1			T78	3		T79	233		T80	7
valid_sources[0x07]	57685	1			T78	2		T79	219		T80	4
valid_sources[0x08]	57488	1			T78	9		T79	221		T80	5
valid_sources[0x09]	58273	1			T78	1		T79	176		T80	9
valid_sources[0x0a]	58571	1			T78	7		T79	139		T80	1
valid_sources[0x0b]	57499	1			T78	4		T79	145		T80	2
valid_sources[0x0c]	57356	1			T78	7		T79	103		T80	7
valid_sources[0x0d]	57348	1			T78	2		T79	200		T673	11
valid_sources[0x0e]	57688	1			T78	1		T79	199		T80	3
valid_sources[0x0f]	56810	1			T78	4		T79	114		T80	11
valid_sources[0x10]	57718	1			T78	2		T79	251		T80	5
valid_sources[0x11]	57019	1			T78	3		T79	160		T80	5
valid_sources[0x12]	57086	1			T78	2		T79	115		T80	3
valid_sources[0x13]	57835	1			T78	2		T79	238		T80	9
valid_sources[0x14]	58196	1			T78	1		T79	221		T80	1
valid_sources[0x15]	56646	1			T78	3		T79	198		T80	7
valid_sources[0x16]	56707	1			T78	6		T79	119		T80	2
valid_sources[0x17]	57637	1			T78	3		T79	152		T80	5
valid_sources[0x18]	56840	1			T78	2		T79	152		T80	1
valid_sources[0x19]	58348	1			T78	3		T79	187		T80	3
valid_sources[0x1a]	57011	1			T78	1		T79	203		T80	6
valid_sources[0x1b]	58070	1			T78	3		T79	206		T80	2
valid_sources[0x1c]	57755	1			T78	5		T79	165		T80	2
valid_sources[0x1d]	56744	1			T78	4		T79	155		T80	6
valid_sources[0x1e]	57239	1			T78	1		T79	226		T80	5
valid_sources[0x1f]	57030	1			T78	4		T79	190		T80	2
valid_sources[0x20]	56298	1			T78	2		T79	171		T80	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

54251

1

T78

6

T79

149

T80

11

values[0x0]

all_enables

biggest_size

408579

1

T78

11

T79

1309

T80

12

values[0x1]

all_enables

biggest_size

53985

1

T78

9

T79

150

T80

9

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2997023	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

474029

1

T78

6

T79

1510

T80

33

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1173595	1			T78	36		T79	3560		T80	145
values[0x0]	1121836	1			T78	3		T79	3513		T80	26
values[0x1]	1175621	1			T78	41		T79	3577		T80	142

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2321238	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1149814

1

T78

32

T79

3587

T80

108

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54413	1			T79	154		T80	3		T673	11
valid_sources[0x01]	53958	1			T79	150		T80	4		T673	11
valid_sources[0x02]	53989	1			T79	168		T80	5		T673	7
valid_sources[0x03]	54312	1			T79	134		T80	8		T673	13
valid_sources[0x04]	53774	1			T79	199		T80	5		T673	6
valid_sources[0x05]	54483	1			T78	1		T79	176		T80	2
valid_sources[0x06]	53239	1			T78	1		T79	195		T80	2
valid_sources[0x07]	53378	1			T78	1		T79	139		T80	10
valid_sources[0x08]	53959	1			T78	1		T79	151		T80	5
valid_sources[0x09]	54896	1			T79	153		T80	3		T673	10
valid_sources[0x0a]	55496	1			T78	3		T79	169		T80	5
valid_sources[0x0b]	53838	1			T78	1		T79	159		T80	3
valid_sources[0x0c]	54351	1			T79	142		T80	5		T673	7
valid_sources[0x0d]	54333	1			T78	4		T79	190		T80	3
valid_sources[0x0e]	53756	1			T78	3		T79	187		T80	4
valid_sources[0x0f]	53968	1			T79	149		T80	10		T673	12
valid_sources[0x10]	53519	1			T78	1		T79	157		T80	6
valid_sources[0x11]	54313	1			T78	1		T79	131		T80	2
valid_sources[0x12]	55015	1			T78	1		T79	144		T80	8
valid_sources[0x13]	55076	1			T78	3		T79	191		T80	11
valid_sources[0x14]	54331	1			T78	1		T79	162		T80	7
valid_sources[0x15]	54174	1			T78	1		T79	199		T80	4
valid_sources[0x16]	53707	1			T78	3		T79	162		T80	5
valid_sources[0x17]	55050	1			T78	1		T79	164		T80	6
valid_sources[0x18]	54186	1			T78	1		T79	193		T80	1
valid_sources[0x19]	54263	1			T78	2		T79	138		T80	1
valid_sources[0x1a]	53569	1			T79	204		T80	6		T673	12
valid_sources[0x1b]	55259	1			T78	1		T79	164		T80	7
valid_sources[0x1c]	54235	1			T78	1		T79	253		T80	3
valid_sources[0x1d]	54353	1			T78	4		T79	173		T80	2
valid_sources[0x1e]	54100	1			T79	156		T80	4		T673	7
valid_sources[0x1f]	53833	1			T79	168		T80	7		T673	7
valid_sources[0x20]	53721	1			T79	164		T80	6		T673	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49945

1

T78

4

T79

164

T80

13

values[0x0]

all_enables

biggest_size

374343

1

T78

1

T79

1193

T80

13

values[0x1]

all_enables

biggest_size

49741

1

T78

1

T79

153

T80

7