Module Definition
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Module : rv_plic_gateway
SCORELINECONDTOGGLEFSMBRANCHASSERT
69.17 100.00 20.00 87.50

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_plic_component_0.1/rtl/rv_plic_gateway.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_plic.u_gateway 75.00 100.00 25.00 100.00



Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_gateway

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 100.00 25.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 100.00 25.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.93 99.65 100.00 100.00 100.00 90.00 u_rv_plic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : rv_plic_gateway
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS2833100.00
ALWAYS3300
ALWAYS3322100.00
ALWAYS4333100.00
ALWAYS5533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_plic_component_0.1/rtl/rv_plic_gateway.sv' or '../src/lowrisc_ip_rv_plic_component_0.1/rtl/rv_plic_gateway.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 2 2
29 1 1
33 1 1
34 1 1
43 1 1
44 1 1
46 1 1
55 1 1
56 1 1
58 1 1


Cond Coverage for Module : rv_plic_gateway
TotalCoveredPercent
Conditions5120.00
Logical5120.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (le_i[i] ? (src_i[i] & ((~src_q[i]))) : src_i[i])
             ---1---
-1-StatusTests
0CoveredT4,T5,T15
1Not Covered

 LINE       34
 SUB-EXPRESSION (src_i[i] & ((~src_q[i])))
                 ----1---   ------2------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

Branch Coverage for Module : rv_plic_gateway
Line No.TotalCoveredPercent
Branches 8 7 87.50
IF 28 2 2 100.00
TERNARY 34 2 1 50.00
IF 43 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_plic_component_0.1/rtl/rv_plic_gateway.sv' or '../src/lowrisc_ip_rv_plic_component_0.1/rtl/rv_plic_gateway.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 34 (le_i[i]) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T4,T5,T15


LineNo. Expression -1-: 43 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_gateway
Line No.TotalCoveredPercent
TOTAL1111100.00
ALWAYS2833100.00
ALWAYS3300
ALWAYS3322100.00
ALWAYS4333100.00
ALWAYS5533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_plic_component_0.1/rtl/rv_plic_gateway.sv' or '../src/lowrisc_ip_rv_plic_component_0.1/rtl/rv_plic_gateway.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 2 2
29 1 1
33 1 1
34 1 1
43 1 1
44 1 1
46 1 1
55 1 1
56 1 1
58 1 1


Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_gateway
TotalCoveredPercent
Conditions4125.00
Logical4125.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (le_i[i] ? (src_i[i] & ((~src_q[i]))) : src_i[i])
             ---1---
-1-StatusTestsExclude Annotation
0CoveredT4,T5,T15
1Excluded [UNR] The le_i input is tied off to 0 (only level interrupts supported).

 LINE       34
 SUB-EXPRESSION (src_i[i] & ((~src_q[i])))
                 ----1---   ------2------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_gateway
Line No.TotalCoveredPercent
Branches 7 7 100.00
IF 28 2 2 100.00
TERNARY 34 1 1 100.00
IF 43 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_plic_component_0.1/rtl/rv_plic_gateway.sv' or '../src/lowrisc_ip_rv_plic_component_0.1/rtl/rv_plic_gateway.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 28 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 34 (le_i[i]) ?

Branches:
-1-StatusTestsExclude Annotation
1 Excluded [UNR] The le_i input is tied off to 0 (only level interrupts supported).
0 Covered T4,T5,T15


LineNo. Expression -1-: 43 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%