Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	544042129	63304689	0	0
DepthKnown_A	544042129	543933742	0	0
RvalidKnown_A	544042129	543933742	0	0
WreadyKnown_A	544042129	543933742	0	0
gen_passthru_fifo.paramCheckPass	1023	1023	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544042129	63304689	0	0
T4	124959	17032	0	0
T5	256708	19989	0	0
T6	101613	11716	0	0
T15	145163	19480	0	0
T28	151562	15478	0	0
T30	108646	30680	0	0
T55	152062	161447	0	0
T87	98585	10921	0	0
T88	78568	9034	0	0
T89	241644	32691	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544042129	543933742	0	0
T4	124959	124908	0	0
T5	256708	256650	0	0
T6	101613	101558	0	0
T15	145163	145108	0	0
T28	151562	151461	0	0
T30	108646	108619	0	0
T55	152062	152057	0	0
T87	98585	98523	0	0
T88	78568	78517	0	0
T89	241644	241586	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544042129	543933742	0	0
T4	124959	124908	0	0
T5	256708	256650	0	0
T6	101613	101558	0	0
T15	145163	145108	0	0
T28	151562	151461	0	0
T30	108646	108619	0	0
T55	152062	152057	0	0
T87	98585	98523	0	0
T88	78568	78517	0	0
T89	241644	241586	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544042129	543933742	0	0
T4	124959	124908	0	0
T5	256708	256650	0	0
T6	101613	101558	0	0
T15	145163	145108	0	0
T28	151562	151461	0	0
T30	108646	108619	0	0
T55	152062	152057	0	0
T87	98585	98523	0	0
T88	78568	78517	0	0
T89	241644	241586	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T28	1	1	0	0
T30	1	1	0	0
T55	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	544042129	49440173	0	0
DepthKnown_A	544042129	543933742	0	0
RvalidKnown_A	544042129	543933742	0	0
WreadyKnown_A	544042129	543933742	0	0
gen_passthru_fifo.paramCheckPass	1023	1023	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544042129	49440173	0	0
T4	124959	11903	0	0
T5	256708	15903	0	0
T6	101613	9340	0	0
T15	145163	14347	0	0
T28	151562	11853	0	0
T30	108646	22183	0	0
T55	152062	141488	0	0
T87	98585	8743	0	0
T88	78568	6741	0	0
T89	241644	28413	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544042129	543933742	0	0
T4	124959	124908	0	0
T5	256708	256650	0	0
T6	101613	101558	0	0
T15	145163	145108	0	0
T28	151562	151461	0	0
T30	108646	108619	0	0
T55	152062	152057	0	0
T87	98585	98523	0	0
T88	78568	78517	0	0
T89	241644	241586	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544042129	543933742	0	0
T4	124959	124908	0	0
T5	256708	256650	0	0
T6	101613	101558	0	0
T15	145163	145108	0	0
T28	151562	151461	0	0
T30	108646	108619	0	0
T55	152062	152057	0	0
T87	98585	98523	0	0
T88	78568	78517	0	0
T89	241644	241586	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544042129	543933742	0	0
T4	124959	124908	0	0
T5	256708	256650	0	0
T6	101613	101558	0	0
T15	145163	145108	0	0
T28	151562	151461	0	0
T30	108646	108619	0	0
T55	152062	152057	0	0
T87	98585	98523	0	0
T88	78568	78517	0	0
T89	241644	241586	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T28	1	1	0	0
T30	1	1	0	0
T55	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	544042129	44554238	0	0
DepthKnown_A	544042129	543933742	0	0
RvalidKnown_A	544042129	543933742	0	0
WreadyKnown_A	544042129	543933742	0	0
gen_passthru_fifo.paramCheckPass	1023	1023	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544042129	44554238	0	0
T4	124959	6549	0	0
T5	256708	9839	0	0
T6	101613	6259	0	0
T15	145163	8328	0	0
T28	151562	9055	0	0
T30	108646	16908	0	0
T55	152062	226985	0	0
T87	98585	5890	0	0
T88	78568	5157	0	0
T89	241644	14157	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544042129	543933742	0	0
T4	124959	124908	0	0
T5	256708	256650	0	0
T6	101613	101558	0	0
T15	145163	145108	0	0
T28	151562	151461	0	0
T30	108646	108619	0	0
T55	152062	152057	0	0
T87	98585	98523	0	0
T88	78568	78517	0	0
T89	241644	241586	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544042129	543933742	0	0
T4	124959	124908	0	0
T5	256708	256650	0	0
T6	101613	101558	0	0
T15	145163	145108	0	0
T28	151562	151461	0	0
T30	108646	108619	0	0
T55	152062	152057	0	0
T87	98585	98523	0	0
T88	78568	78517	0	0
T89	241644	241586	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544042129	543933742	0	0
T4	124959	124908	0	0
T5	256708	256650	0	0
T6	101613	101558	0	0
T15	145163	145108	0	0
T28	151562	151461	0	0
T30	108646	108619	0	0
T55	152062	152057	0	0
T87	98585	98523	0	0
T88	78568	78517	0	0
T89	241644	241586	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T28	1	1	0	0
T30	1	1	0	0
T55	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	544042129	37654217	0	0
DepthKnown_A	544042129	543933742	0	0
RvalidKnown_A	544042129	543933742	0	0
WreadyKnown_A	544042129	543933742	0	0
gen_passthru_fifo.paramCheckPass	1023	1023	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544042129	37654217	0	0
T4	124959	6271	0	0
T5	256708	9096	0	0
T6	101613	6113	0	0
T15	145163	8050	0	0
T28	151562	8816	0	0
T30	108646	16330	0	0
T55	152062	147292	0	0
T87	98585	5736	0	0
T88	78568	5031	0	0
T89	241644	13903	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544042129	543933742	0	0
T4	124959	124908	0	0
T5	256708	256650	0	0
T6	101613	101558	0	0
T15	145163	145108	0	0
T28	151562	151461	0	0
T30	108646	108619	0	0
T55	152062	152057	0	0
T87	98585	98523	0	0
T88	78568	78517	0	0
T89	241644	241586	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544042129	543933742	0	0
T4	124959	124908	0	0
T5	256708	256650	0	0
T6	101613	101558	0	0
T15	145163	145108	0	0
T28	151562	151461	0	0
T30	108646	108619	0	0
T55	152062	152057	0	0
T87	98585	98523	0	0
T88	78568	78517	0	0
T89	241644	241586	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	544042129	543933742	0	0
T4	124959	124908	0	0
T5	256708	256650	0	0
T6	101613	101558	0	0
T15	145163	145108	0	0
T28	151562	151461	0	0
T30	108646	108619	0	0
T55	152062	152057	0	0
T87	98585	98523	0	0
T88	78568	78517	0	0
T89	241644	241586	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1023	1023	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T28	1	1	0	0
T30	1	1	0	0
T55	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	628324083	90067	0	0
DepthKnown_A	628324083	628199962	0	0
RvalidKnown_A	628324083	628199962	0	0
WreadyKnown_A	628324083	628199962	0	0
gen_passthru_fifo.paramCheckPass	2933	2933	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628324083	90067	0	0
T4	124959	26	0	0
T5	256708	346	0	0
T6	101613	13	0	0
T15	145163	26	0	0
T28	151562	26	0	0
T30	108646	63	0	0
T55	152062	41	0	0
T87	98585	13	0	0
T88	78568	13	0	0
T89	241644	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628324083	628199962	0	0
T4	124959	124908	0	0
T5	256708	256650	0	0
T6	101613	101558	0	0
T15	145163	145108	0	0
T28	151562	151461	0	0
T30	108646	108619	0	0
T55	152062	152057	0	0
T87	98585	98523	0	0
T88	78568	78517	0	0
T89	241644	241586	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628324083	628199962	0	0
T4	124959	124908	0	0
T5	256708	256650	0	0
T6	101613	101558	0	0
T15	145163	145108	0	0
T28	151562	151461	0	0
T30	108646	108619	0	0
T55	152062	152057	0	0
T87	98585	98523	0	0
T88	78568	78517	0	0
T89	241644	241586	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628324083	628199962	0	0
T4	124959	124908	0	0
T5	256708	256650	0	0
T6	101613	101558	0	0
T15	145163	145108	0	0
T28	151562	151461	0	0
T30	108646	108619	0	0
T55	152062	152057	0	0
T87	98585	98523	0	0
T88	78568	78517	0	0
T89	241644	241586	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2933	2933	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T28	1	1	0	0
T30	1	1	0	0
T55	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	628324083	93174	0	0
DepthKnown_A	628324083	628199962	0	0
RvalidKnown_A	628324083	628199962	0	0
WreadyKnown_A	628324083	628199962	0	0
gen_passthru_fifo.paramCheckPass	2933	2933	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628324083	93174	0	0
T4	124959	26	0	0
T5	256708	346	0	0
T6	101613	13	0	0
T15	145163	26	0	0
T28	151562	26	0	0
T30	108646	63	0	0
T55	152062	41	0	0
T87	98585	13	0	0
T88	78568	13	0	0
T89	241644	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628324083	628199962	0	0
T4	124959	124908	0	0
T5	256708	256650	0	0
T6	101613	101558	0	0
T15	145163	145108	0	0
T28	151562	151461	0	0
T30	108646	108619	0	0
T55	152062	152057	0	0
T87	98585	98523	0	0
T88	78568	78517	0	0
T89	241644	241586	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628324083	628199962	0	0
T4	124959	124908	0	0
T5	256708	256650	0	0
T6	101613	101558	0	0
T15	145163	145108	0	0
T28	151562	151461	0	0
T30	108646	108619	0	0
T55	152062	152057	0	0
T87	98585	98523	0	0
T88	78568	78517	0	0
T89	241644	241586	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628324083	628199962	0	0
T4	124959	124908	0	0
T5	256708	256650	0	0
T6	101613	101558	0	0
T15	145163	145108	0	0
T28	151562	151461	0	0
T30	108646	108619	0	0
T55	152062	152057	0	0
T87	98585	98523	0	0
T88	78568	78517	0	0
T89	241644	241586	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2933	2933	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T28	1	1	0	0
T30	1	1	0	0
T55	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	628324083	51915	0	0
DepthKnown_A	628324083	628199962	0	0
RvalidKnown_A	628324083	628199962	0	0
WreadyKnown_A	628324083	628199962	0	0
gen_passthru_fifo.paramCheckPass	2933	2933	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628324083	51915	0	0
T4	124959	23	0	0
T5	256708	343	0	0
T6	101613	12	0	0
T15	145163	23	0	0
T28	151562	24	0	0
T30	108646	59	0	0
T55	152062	12	0	0
T87	98585	12	0	0
T88	78568	12	0	0
T89	241644	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628324083	628199962	0	0
T4	124959	124908	0	0
T5	256708	256650	0	0
T6	101613	101558	0	0
T15	145163	145108	0	0
T28	151562	151461	0	0
T30	108646	108619	0	0
T55	152062	152057	0	0
T87	98585	98523	0	0
T88	78568	78517	0	0
T89	241644	241586	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628324083	628199962	0	0
T4	124959	124908	0	0
T5	256708	256650	0	0
T6	101613	101558	0	0
T15	145163	145108	0	0
T28	151562	151461	0	0
T30	108646	108619	0	0
T55	152062	152057	0	0
T87	98585	98523	0	0
T88	78568	78517	0	0
T89	241644	241586	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628324083	628199962	0	0
T4	124959	124908	0	0
T5	256708	256650	0	0
T6	101613	101558	0	0
T15	145163	145108	0	0
T28	151562	151461	0	0
T30	108646	108619	0	0
T55	152062	152057	0	0
T87	98585	98523	0	0
T88	78568	78517	0	0
T89	241644	241586	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2933	2933	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T28	1	1	0	0
T30	1	1	0	0
T55	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	628324083	51915	0	0
DepthKnown_A	628324083	628199962	0	0
RvalidKnown_A	628324083	628199962	0	0
WreadyKnown_A	628324083	628199962	0	0
gen_passthru_fifo.paramCheckPass	2933	2933	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628324083	51915	0	0
T4	124959	23	0	0
T5	256708	343	0	0
T6	101613	12	0	0
T15	145163	23	0	0
T28	151562	24	0	0
T30	108646	59	0	0
T55	152062	12	0	0
T87	98585	12	0	0
T88	78568	12	0	0
T89	241644	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628324083	628199962	0	0
T4	124959	124908	0	0
T5	256708	256650	0	0
T6	101613	101558	0	0
T15	145163	145108	0	0
T28	151562	151461	0	0
T30	108646	108619	0	0
T55	152062	152057	0	0
T87	98585	98523	0	0
T88	78568	78517	0	0
T89	241644	241586	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628324083	628199962	0	0
T4	124959	124908	0	0
T5	256708	256650	0	0
T6	101613	101558	0	0
T15	145163	145108	0	0
T28	151562	151461	0	0
T30	108646	108619	0	0
T55	152062	152057	0	0
T87	98585	98523	0	0
T88	78568	78517	0	0
T89	241644	241586	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628324083	628199962	0	0
T4	124959	124908	0	0
T5	256708	256650	0	0
T6	101613	101558	0	0
T15	145163	145108	0	0
T28	151562	151461	0	0
T30	108646	108619	0	0
T55	152062	152057	0	0
T87	98585	98523	0	0
T88	78568	78517	0	0
T89	241644	241586	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2933	2933	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T28	1	1	0	0
T30	1	1	0	0
T55	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	628324083	38152	0	0
DepthKnown_A	628324083	628199962	0	0
RvalidKnown_A	628324083	628199962	0	0
WreadyKnown_A	628324083	628199962	0	0
gen_passthru_fifo.paramCheckPass	2933	2933	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628324083	38152	0	0
T4	124959	3	0	0
T5	256708	3	0	0
T6	101613	1	0	0
T15	145163	3	0	0
T28	151562	2	0	0
T30	108646	4	0	0
T55	152062	29	0	0
T87	98585	1	0	0
T88	78568	1	0	0
T89	241644	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628324083	628199962	0	0
T4	124959	124908	0	0
T5	256708	256650	0	0
T6	101613	101558	0	0
T15	145163	145108	0	0
T28	151562	151461	0	0
T30	108646	108619	0	0
T55	152062	152057	0	0
T87	98585	98523	0	0
T88	78568	78517	0	0
T89	241644	241586	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628324083	628199962	0	0
T4	124959	124908	0	0
T5	256708	256650	0	0
T6	101613	101558	0	0
T15	145163	145108	0	0
T28	151562	151461	0	0
T30	108646	108619	0	0
T55	152062	152057	0	0
T87	98585	98523	0	0
T88	78568	78517	0	0
T89	241644	241586	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628324083	628199962	0	0
T4	124959	124908	0	0
T5	256708	256650	0	0
T6	101613	101558	0	0
T15	145163	145108	0	0
T28	151562	151461	0	0
T30	108646	108619	0	0
T55	152062	152057	0	0
T87	98585	98523	0	0
T88	78568	78517	0	0
T89	241644	241586	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2933	2933	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T28	1	1	0	0
T30	1	1	0	0
T55	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	628324083	41259	0	0
DepthKnown_A	628324083	628199962	0	0
RvalidKnown_A	628324083	628199962	0	0
WreadyKnown_A	628324083	628199962	0	0
gen_passthru_fifo.paramCheckPass	2933	2933	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628324083	41259	0	0
T4	124959	3	0	0
T5	256708	3	0	0
T6	101613	1	0	0
T15	145163	3	0	0
T28	151562	2	0	0
T30	108646	4	0	0
T55	152062	29	0	0
T87	98585	1	0	0
T88	78568	1	0	0
T89	241644	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628324083	628199962	0	0
T4	124959	124908	0	0
T5	256708	256650	0	0
T6	101613	101558	0	0
T15	145163	145108	0	0
T28	151562	151461	0	0
T30	108646	108619	0	0
T55	152062	152057	0	0
T87	98585	98523	0	0
T88	78568	78517	0	0
T89	241644	241586	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628324083	628199962	0	0
T4	124959	124908	0	0
T5	256708	256650	0	0
T6	101613	101558	0	0
T15	145163	145108	0	0
T28	151562	151461	0	0
T30	108646	108619	0	0
T55	152062	152057	0	0
T87	98585	98523	0	0
T88	78568	78517	0	0
T89	241644	241586	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	628324083	628199962	0	0
T4	124959	124908	0	0
T5	256708	256650	0	0
T6	101613	101558	0	0
T15	145163	145108	0	0
T28	151562	151461	0	0
T30	108646	108619	0	0
T55	152062	152057	0	0
T87	98585	98523	0	0
T88	78568	78517	0	0
T89	241644	241586	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2933	2933	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T28	1	1	0	0
T30	1	1	0	0
T55	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0