Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T30,T28,T1	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T55,T56,T105	Yes	T55,T56,T105	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T55,T56,T105	Yes	T55,T56,T105	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T16,*T58,*T81	Yes	T16,T58,T81	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T16,T58,T7	Yes	T16,T58,T7	INPUT
tl_i.a_valid	Yes	Yes	T55,T60,T56	Yes	T55,T60,T56	INPUT
tl_o.a_ready	Yes	Yes	T55,T60,T56	Yes	T55,T60,T56	OUTPUT
tl_o.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T55,T56,T105	Yes	T55,T56,T105	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T55,T56,T105	Yes	T55,T60,T56	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T55,T56,T105	Yes	T55,T60,T56	OUTPUT
tl_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T253,*T254,*T713	Yes	T253,T254,T713	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T55,*T56,*T105	Yes	T55,T56,T105	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T55,T60,T56	Yes	T55,T60,T56	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T60,T238,T714	Yes	T60,T238,T714	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T238,T237,T85	Yes	T238,T237,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T238,T237,T85	Yes	T238,T237,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T60,T238,T714	Yes	T60,T238,T714	OUTPUT
cio_rx_i	Yes	Yes	T30,T41,T42	Yes	T4,T5,T6	INPUT
cio_tx_o	Yes	Yes	T55,T56,T105	Yes	T55,T56,T105	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T105,T18,T213	Yes	T105,T18,T213	OUTPUT
intr_tx_empty_o	Yes	Yes	T105,T18,T213	Yes	T105,T18,T213	OUTPUT
intr_rx_watermark_o	Yes	Yes	T105,T18,T213	Yes	T105,T18,T213	OUTPUT
intr_tx_done_o	Yes	Yes	T105,T18,T213	Yes	T105,T18,T213	OUTPUT
intr_rx_overflow_o	Yes	Yes	T105,T18,T213	Yes	T105,T18,T213	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T306,T308,T287	Yes	T306,T308,T287	OUTPUT
intr_rx_break_err_o	Yes	Yes	T306,T308,T287	Yes	T306,T308,T287	OUTPUT
intr_rx_timeout_o	Yes	Yes	T306,T308,T287	Yes	T306,T308,T287	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T306,T308,T287	Yes	T306,T308,T287	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T30,T28,T1	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T16,*T58,*T81	Yes	T16,T58,T81	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T16,T58,T7	Yes	T16,T58,T7	INPUT
tl_i.a_valid	Yes	Yes	T55,T60,T56	Yes	T55,T60,T56	INPUT
tl_o.a_ready	Yes	Yes	T55,T60,T56	Yes	T55,T60,T56	OUTPUT
tl_o.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T55,T56,T57	Yes	T55,T60,T56	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T55,T56,T57	Yes	T55,T60,T56	OUTPUT
tl_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T253,*T254,*T713	Yes	T253,T254,T713	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T55,*T56,*T57	Yes	T55,T56,T57	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T55,T60,T56	Yes	T55,T60,T56	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T60,T237,T85	Yes	T60,T237,T85	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T237,T85,T703	Yes	T237,T85,T86	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T237,T85,T86	Yes	T237,T85,T703	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T60,T237,T85	Yes	T60,T237,T85	OUTPUT
cio_rx_i	Yes	Yes	T30,T41,T42	Yes	T4,T5,T6	INPUT
cio_tx_o	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T213,T306,T116	Yes	T213,T306,T116	OUTPUT
intr_tx_empty_o	Yes	Yes	T213,T306,T116	Yes	T213,T306,T116	OUTPUT
intr_rx_watermark_o	Yes	Yes	T213,T306,T116	Yes	T213,T306,T116	OUTPUT
intr_tx_done_o	Yes	Yes	T213,T306,T116	Yes	T213,T306,T116	OUTPUT
intr_rx_overflow_o	Yes	Yes	T213,T306,T116	Yes	T213,T306,T116	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T306,T308,T287	Yes	T306,T308,T287	OUTPUT
intr_rx_break_err_o	Yes	Yes	T306,T308,T287	Yes	T306,T308,T287	OUTPUT
intr_rx_timeout_o	Yes	Yes	T306,T308,T287	Yes	T306,T308,T287	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T306,T308,T287	Yes	T306,T308,T287	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T30,T28,T1	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T18,T210,T325	Yes	T18,T210,T325	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T18,T210,T325	Yes	T18,T210,T325	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T16,*T58,*T81	Yes	T16,T58,T81	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T16,T58,T7	Yes	T16,T58,T7	INPUT
tl_i.a_valid	Yes	Yes	T60,T18,T210	Yes	T60,T18,T210	INPUT
tl_o.a_ready	Yes	Yes	T60,T18,T210	Yes	T60,T18,T210	OUTPUT
tl_o.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T18,T210,T325	Yes	T18,T210,T325	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T18,T210,T325	Yes	T60,T18,T210	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T18,T210,T325	Yes	T60,T18,T210	OUTPUT
tl_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T18,*T210,*T325	Yes	T18,T210,T325	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T60,T18,T210	Yes	T60,T18,T210	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T60,T85,T407	Yes	T60,T85,T407	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T85,T86,T150	Yes	T85,T86,T150	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T85,T86,T150	Yes	T85,T86,T150	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T60,T85,T407	Yes	T60,T85,T407	OUTPUT
cio_rx_i	Yes	Yes	T18,T58,T210	Yes	T18,T58,T210	INPUT
cio_tx_o	Yes	Yes	T18,T210,T325	Yes	T18,T210,T325	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T18,T210,T325	Yes	T18,T210,T325	OUTPUT
intr_tx_empty_o	Yes	Yes	T18,T210,T325	Yes	T18,T210,T325	OUTPUT
intr_rx_watermark_o	Yes	Yes	T18,T210,T325	Yes	T18,T210,T325	OUTPUT
intr_tx_done_o	Yes	Yes	T18,T210,T325	Yes	T18,T210,T325	OUTPUT
intr_rx_overflow_o	Yes	Yes	T18,T210,T325	Yes	T18,T210,T325	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T306,T308,T287	Yes	T306,T308,T287	OUTPUT
intr_rx_break_err_o	Yes	Yes	T306,T308,T287	Yes	T306,T308,T287	OUTPUT
intr_rx_timeout_o	Yes	Yes	T306,T308,T287	Yes	T306,T308,T287	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T306,T308,T287	Yes	T306,T308,T287	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T30,T28,T1	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T105,T141,T306	Yes	T105,T141,T306	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T105,T141,T306	Yes	T105,T141,T306	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T16,*T58,*T81	Yes	T16,T58,T81	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T16,T58,T7	Yes	T16,T58,T7	INPUT
tl_i.a_valid	Yes	Yes	T60,T105,T141	Yes	T60,T105,T141	INPUT
tl_o.a_ready	Yes	Yes	T60,T105,T141	Yes	T60,T105,T141	OUTPUT
tl_o.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T105,T141,T306	Yes	T105,T141,T306	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T105,T141,T306	Yes	T60,T105,T141	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T105,T141,T306	Yes	T60,T105,T141	OUTPUT
tl_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T105,*T141,*T306	Yes	T105,T141,T306	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T60,T105,T141	Yes	T60,T105,T141	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T60,T238,T85	Yes	T60,T238,T85	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T238,T85,T86	Yes	T238,T85,T86	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T238,T85,T86	Yes	T238,T85,T86	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T60,T238,T85	Yes	T60,T238,T85	OUTPUT
cio_rx_i	Yes	Yes	T105,T141,T326	Yes	T105,T141,T326	INPUT
cio_tx_o	Yes	Yes	T105,T141,T326	Yes	T105,T141,T326	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T105,T141,T306	Yes	T105,T141,T306	OUTPUT
intr_tx_empty_o	Yes	Yes	T105,T141,T306	Yes	T105,T141,T306	OUTPUT
intr_rx_watermark_o	Yes	Yes	T105,T141,T306	Yes	T105,T141,T306	OUTPUT
intr_tx_done_o	Yes	Yes	T105,T141,T306	Yes	T105,T141,T306	OUTPUT
intr_rx_overflow_o	Yes	Yes	T105,T141,T306	Yes	T105,T141,T306	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T306,T308,T287	Yes	T306,T308,T287	OUTPUT
intr_rx_break_err_o	Yes	Yes	T306,T308,T287	Yes	T306,T308,T287	OUTPUT
intr_rx_timeout_o	Yes	Yes	T306,T308,T287	Yes	T306,T308,T287	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T306,T308,T287	Yes	T306,T308,T287	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T30,T28,T1	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T25,T306,T309	Yes	T25,T306,T309	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T25,T306,T309	Yes	T25,T306,T309	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T16,*T58,*T81	Yes	T16,T58,T81	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T16,T58,T7	Yes	T16,T58,T7	INPUT
tl_i.a_valid	Yes	Yes	T60,T25,T306	Yes	T60,T25,T306	INPUT
tl_o.a_ready	Yes	Yes	T60,T25,T306	Yes	T60,T25,T306	OUTPUT
tl_o.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T25,T306,T309	Yes	T25,T306,T309	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T25,T306,T309	Yes	T60,T25,T306	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T25,T306,T309	Yes	T60,T25,T306	OUTPUT
tl_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T25,*T306,*T309	Yes	T25,T306,T309	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T60,T25,T306	Yes	T60,T25,T306	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T60,T238,T714	Yes	T60,T238,T714	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T238,T85,T86	Yes	T238,T85,T86	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T238,T85,T86	Yes	T238,T85,T86	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T60,T238,T714	Yes	T60,T238,T714	OUTPUT
cio_rx_i	Yes	Yes	T25,T309,T310	Yes	T25,T309,T310	INPUT
cio_tx_o	Yes	Yes	T25,T309,T310	Yes	T25,T309,T310	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T25,T306,T309	Yes	T25,T306,T309	OUTPUT
intr_tx_empty_o	Yes	Yes	T25,T306,T309	Yes	T25,T306,T309	OUTPUT
intr_rx_watermark_o	Yes	Yes	T25,T306,T309	Yes	T25,T306,T309	OUTPUT
intr_tx_done_o	Yes	Yes	T25,T306,T309	Yes	T25,T306,T309	OUTPUT
intr_rx_overflow_o	Yes	Yes	T25,T306,T309	Yes	T25,T306,T309	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T306,T308,T287	Yes	T306,T308,T287	OUTPUT
intr_rx_break_err_o	Yes	Yes	T306,T308,T287	Yes	T306,T308,T287	OUTPUT
intr_rx_timeout_o	Yes	Yes	T306,T308,T287	Yes	T306,T308,T287	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T306,T308,T287	Yes	T306,T308,T287	OUTPUT

*Tests covering at least one bit in the range