Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sensor_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.78 94.59 89.00 80.28 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_0.1/rtl/sensor_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_sensor_ctrl_aon 92.78 94.59 89.00 80.28 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.78 94.59 89.00 80.28 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.37 94.19 86.20 80.28 96.17 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_sync_assign[0].u_alert_in_buf 100.00 100.00
gen_alert_sync_assign[10].u_alert_in_buf 100.00 100.00
gen_alert_sync_assign[1].u_alert_in_buf 100.00 100.00
gen_alert_sync_assign[2].u_alert_in_buf 100.00 100.00
gen_alert_sync_assign[3].u_alert_in_buf 100.00 100.00
gen_alert_sync_assign[4].u_alert_in_buf 100.00 100.00
gen_alert_sync_assign[5].u_alert_in_buf 100.00 100.00
gen_alert_sync_assign[6].u_alert_in_buf 100.00 100.00
gen_alert_sync_assign[7].u_alert_in_buf 100.00 100.00
gen_alert_sync_assign[8].u_alert_in_buf 100.00 100.00
gen_alert_sync_assign[9].u_alert_in_buf 100.00 100.00
u_alert_n_sync 100.00 100.00 100.00
u_alert_p_sync 100.00 100.00 100.00
u_init_chg 100.00 100.00 100.00 100.00
u_init_intr 100.00 100.00 100.00 100.00 100.00
u_io_intr 100.00 100.00 100.00 100.00 100.00
u_io_status_chg 100.00 100.00 100.00
u_prim_sec_anchor_buf 100.00 100.00
u_reg 93.77 93.71 85.48 95.89 100.00
u_wake_sync 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : sensor_ctrl
Line No.TotalCoveredPercent
TOTAL11110594.59
ALWAYS18600
ALWAYS18622100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN21411100.00
CONT_ASSIGN21411100.00
CONT_ASSIGN21411100.00
CONT_ASSIGN21411100.00
CONT_ASSIGN21411100.00
CONT_ASSIGN21411100.00
CONT_ASSIGN21411100.00
CONT_ASSIGN21411100.00
CONT_ASSIGN21411100.00
CONT_ASSIGN21411100.00
CONT_ASSIGN21411100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN22211100.00
CONT_ASSIGN225100.00
CONT_ASSIGN22511100.00
CONT_ASSIGN22511100.00
CONT_ASSIGN22511100.00
CONT_ASSIGN22511100.00
CONT_ASSIGN225100.00
CONT_ASSIGN22511100.00
CONT_ASSIGN225100.00
CONT_ASSIGN225100.00
CONT_ASSIGN225100.00
CONT_ASSIGN225100.00
CONT_ASSIGN22811100.00
CONT_ASSIGN22811100.00
CONT_ASSIGN22811100.00
CONT_ASSIGN22811100.00
CONT_ASSIGN22811100.00
CONT_ASSIGN22811100.00
CONT_ASSIGN22811100.00
CONT_ASSIGN22811100.00
CONT_ASSIGN22811100.00
CONT_ASSIGN22811100.00
CONT_ASSIGN22811100.00
CONT_ASSIGN23411100.00
ALWAYS24400
ALWAYS24433100.00
ALWAYS25200
ALWAYS25233100.00
CONT_ASSIGN26111100.00
CONT_ASSIGN26311100.00
CONT_ASSIGN31411100.00
ALWAYS33033100.00
ALWAYS34133100.00
ALWAYS3561111100.00
CONT_ASSIGN37611100.00
CONT_ASSIGN37611100.00
CONT_ASSIGN37611100.00
CONT_ASSIGN37611100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN37811100.00
CONT_ASSIGN37911100.00
CONT_ASSIGN37911100.00
CONT_ASSIGN37911100.00
CONT_ASSIGN37911100.00
CONT_ASSIGN39100
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_0.1/rtl/sensor_ctrl.sv' or '../src/lowrisc_systems_sensor_ctrl_0.1/rtl/sensor_ctrl.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
186 1 1
187 1 1
211 11 11
214 11 11
217 11 11
222 11 11
225 5 11
228 11 11
234 1 1
244 1 1
245 1 1
246 1 1
252 1 1
253 1 1
254 1 1
261 1 1
263 1 1
314 1 1
330 1 1
331 1 1
333 1 1
341 1 1
342 1 1
344 1 1
356 1 1
357 1 1
358 1 1
359 1 1
361 1 1
362 1 1
363 1 1
MISSING_ELSE
365 1 1
366 1 1
MISSING_ELSE
368 1 1
369 1 1
MISSING_ELSE
376 4 4
377 4 4
378 4 4
379 4 4
391 unreachable


Cond Coverage for Module : sensor_ctrl
TotalCoveredPercent
Conditions1008989.00
Logical1008989.00
Non-Logical00
Event00

 LINE       187
 EXPRESSION (alert_event_p[i] | ((~alert_event_n[i])))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT121,T107,T130
01Not Covered
10CoveredT367,T368,T369

 LINE       214
 EXPRESSION (alert_en_buf[0] && event_vld[0] && ((!reg2hw.fatal_alert_en[0])))
             -------1-------    ------2-----    --------------3--------------
-1--2--3-StatusTests
011CoveredT121,T123,T124
101CoveredT4,T5,T6
110Not Covered
111CoveredT121,T122,T14

 LINE       214
 EXPRESSION (alert_en_buf[1] && event_vld[1] && ((!reg2hw.fatal_alert_en[1])))
             -------1-------    ------2-----    --------------3--------------
-1--2--3-StatusTests
011CoveredT121,T123,T124
101CoveredT4,T5,T6
110CoveredT125
111CoveredT121,T123,T124

 LINE       214
 EXPRESSION (alert_en_buf[2] && event_vld[2] && ((!reg2hw.fatal_alert_en[2])))
             -------1-------    ------2-----    --------------3--------------
-1--2--3-StatusTests
011CoveredT121,T128,T123
101CoveredT4,T5,T6
110CoveredT128,T129
111CoveredT121,T128,T123

 LINE       214
 EXPRESSION (alert_en_buf[3] && event_vld[3] && ((!reg2hw.fatal_alert_en[3])))
             -------1-------    ------2-----    --------------3--------------
-1--2--3-StatusTests
011CoveredT121,T130,T123
101CoveredT4,T5,T6
110CoveredT130
111CoveredT121,T130,T123

 LINE       214
 EXPRESSION (alert_en_buf[4] && event_vld[4] && ((!reg2hw.fatal_alert_en[4])))
             -------1-------    ------2-----    --------------3--------------
-1--2--3-StatusTests
011CoveredT121,T131,T123
101CoveredT4,T5,T6
110CoveredT131,T125
111CoveredT121,T131,T123

 LINE       214
 EXPRESSION (alert_en_buf[5] && event_vld[5] && ((!reg2hw.fatal_alert_en[5])))
             -------1-------    ------2-----    --------------3--------------
-1--2--3-StatusTests
011CoveredT121,T123,T124
101CoveredT4,T5,T6
110Not Covered
111CoveredT121,T123,T124

 LINE       214
 EXPRESSION (alert_en_buf[6] && event_vld[6] && ((!reg2hw.fatal_alert_en[6])))
             -------1-------    ------2-----    --------------3--------------
-1--2--3-StatusTests
011CoveredT121,T128,T123
101CoveredT4,T5,T6
110CoveredT128,T129
111CoveredT121,T128,T123

 LINE       214
 EXPRESSION (alert_en_buf[7] && event_vld[7] && ((!reg2hw.fatal_alert_en[7])))
             -------1-------    ------2-----    --------------3--------------
-1--2--3-StatusTests
011CoveredT121,T123,T124
101CoveredT4,T5,T6
110Not Covered
111CoveredT121,T107,T134

 LINE       214
 EXPRESSION (alert_en_buf[8] && event_vld[8] && ((!reg2hw.fatal_alert_en[8])))
             -------1-------    ------2-----    --------------3--------------
-1--2--3-StatusTests
011CoveredT121,T123,T124
101CoveredT4,T5,T6
110Not Covered
111CoveredT121,T107,T134

 LINE       214
 EXPRESSION (alert_en_buf[9] && event_vld[9] && ((!reg2hw.fatal_alert_en[9])))
             -------1-------    ------2-----    --------------3--------------
-1--2--3-StatusTests
011CoveredT121,T123,T124
101CoveredT4,T5,T6
110Not Covered
111CoveredT121,T123,T124

 LINE       214
 EXPRESSION (alert_en_buf[10] && event_vld[10] && ((!reg2hw.fatal_alert_en[10])))
             --------1-------    ------2------    ---------------3--------------
-1--2--3-StatusTests
011CoveredT121,T123,T124
101CoveredT4,T5,T6
110Not Covered
111CoveredT121,T123,T124

 LINE       217
 EXPRESSION (alert_en_buf[0] && event_vld[0] && reg2hw.fatal_alert_en[0])
             -------1-------    ------2-----    ------------3-----------
-1--2--3-StatusTests
011Not Covered
101CoveredT7
110CoveredT121,T122,T14
111Not Covered

 LINE       228
 EXPRESSION (recov_event[0] & reg2hw.recov_alert[0].q)
             -------1------   -----------2-----------
-1--2-StatusTests
01CoveredT121,T122,T14
10CoveredT121,T122,T14
11CoveredT121,T122,T14

 LINE       228
 EXPRESSION (recov_event[1] & reg2hw.recov_alert[1].q)
             -------1------   -----------2-----------
-1--2-StatusTests
01CoveredT121,T123,T124
10CoveredT121,T123,T124
11CoveredT121,T123,T124

 LINE       228
 EXPRESSION (recov_event[2] & reg2hw.recov_alert[2].q)
             -------1------   -----------2-----------
-1--2-StatusTests
01CoveredT121,T128,T123
10CoveredT121,T128,T123
11CoveredT121,T128,T123

 LINE       228
 EXPRESSION (recov_event[3] & reg2hw.recov_alert[3].q)
             -------1------   -----------2-----------
-1--2-StatusTests
01CoveredT121,T130,T123
10CoveredT121,T130,T123
11CoveredT121,T130,T123

 LINE       228
 EXPRESSION (recov_event[4] & reg2hw.recov_alert[4].q)
             -------1------   -----------2-----------
-1--2-StatusTests
01CoveredT121,T131,T123
10CoveredT121,T131,T123
11CoveredT121,T131,T123

 LINE       228
 EXPRESSION (recov_event[5] & reg2hw.recov_alert[5].q)
             -------1------   -----------2-----------
-1--2-StatusTests
01CoveredT121,T123,T124
10CoveredT121,T123,T124
11CoveredT121,T123,T124

 LINE       228
 EXPRESSION (recov_event[6] & reg2hw.recov_alert[6].q)
             -------1------   -----------2-----------
-1--2-StatusTests
01CoveredT121,T128,T123
10CoveredT121,T128,T123
11CoveredT121,T128,T123

 LINE       228
 EXPRESSION (recov_event[7] & reg2hw.recov_alert[7].q)
             -------1------   -----------2-----------
-1--2-StatusTests
01CoveredT121,T107,T134
10CoveredT121,T107,T134
11CoveredT121,T107,T134

 LINE       228
 EXPRESSION (recov_event[8] & reg2hw.recov_alert[8].q)
             -------1------   -----------2-----------
-1--2-StatusTests
01CoveredT121,T107,T134
10CoveredT121,T107,T134
11CoveredT121,T107,T134

 LINE       228
 EXPRESSION (recov_event[9] & reg2hw.recov_alert[9].q)
             -------1------   -----------2-----------
-1--2-StatusTests
01CoveredT121,T123,T124
10CoveredT121,T123,T124
11CoveredT121,T123,T124

 LINE       228
 EXPRESSION (recov_event[10] & reg2hw.recov_alert[10].q)
             -------1-------   ------------2-----------
-1--2-StatusTests
01CoveredT121,T123,T124
10CoveredT121,T123,T124
11CoveredT121,T123,T124

 LINE       245
 EXPRESSION (alert_event_p[i] & event_clr[i])
             --------1-------   ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT121,T107,T130
11CoveredT121,T107,T130

 LINE       246
 SUB-EXPRESSION (((~alert_event_n[i])) & event_clr[i])
                 ----------1----------   ------2-----
-1--2-StatusTests
01CoveredT367,T368,T369
10CoveredT121,T107,T130
11CoveredT121,T107,T130

 LINE       261
 EXPRESSION (reg2hw.alert_test.recov_alert.qe & reg2hw.alert_test.recov_alert.q)
             ----------------1---------------   ---------------2---------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT60,T61,T244
11CoveredT60,T7,T61

 LINE       263
 EXPRESSION (reg2hw.alert_test.fatal_alert.qe & reg2hw.alert_test.fatal_alert.q)
             ----------------1---------------   ---------------2---------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT60,T61,T244
11CoveredT60,T7,T61

 LINE       314
 EXPRESSION (((|(async_alert_event_p & alert_en_buf))) | ((~&(async_alert_event_n | (~alert_en_buf)))) | ((|reg2hw.recov_alert)))
             --------------------1--------------------   ----------------------2----------------------   -----------3-----------
-1--2--3-StatusTests
000CoveredT4,T5,T6
001CoveredT121,T107,T130
010Not Covered
100CoveredT367,T368,T369

Toggle Coverage for Module : sensor_ctrl
TotalCoveredPercent
Totals 148 108 72.97
Total Bits 568 456 80.28
Total Bits 0->1 284 228 80.28
Total Bits 1->0 284 228 80.28

Ports 148 108 72.97
Port Bits 568 456 80.28
Port Bits 0->1 284 228 80.28
Port Bits 1->0 284 228 80.28

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T30,T41,T42 Yes T4,T5,T6 INPUT
clk_aon_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_aon_ni Yes Yes T30,T41,T42 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[18:17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[19] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[21:20] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[22] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T16,*T58,*T81 Yes T16,T58,T81 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T38,T39,T40 Yes T38,T39,T40 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[0] Yes Yes *T16,*T58,*T7 Yes T16,T58,T7 INPUT
tl_i.a_opcode[1] No No No INPUT
tl_i.a_opcode[2] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T56,T121,T107 Yes T56,T121,T107 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T56,T121,T107 Yes T60,T56,T121 OUTPUT
tl_o.d_user.rsp_intg[2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:3] Yes Yes *T38,*T39,*T40 Yes T38,T39,T40 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T30,T41,T42 Yes T4,T5,T6 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[5:0] Yes Yes *T7,*T30,*T60 Yes T7,T4,T5 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T38,T39,T40 Yes T38,T39,T40 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T30,*T60,*T41 Yes T4,T5,T6 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_alert_i.alerts[0].n Yes Yes T121,T122,T14 Yes T122,T14,T103 INPUT
ast_alert_i.alerts[0].p Yes Yes T122,T14,T367 Yes T121,T122,T14 INPUT
ast_alert_i.alerts[1].n Yes Yes T121,T123,T124 Yes T125 INPUT
ast_alert_i.alerts[1].p Yes Yes T125 Yes T121,T123,T124 INPUT
ast_alert_i.alerts[2].n Yes Yes T121,T128,T123 Yes T128,T129 INPUT
ast_alert_i.alerts[2].p Yes Yes T128,T129 Yes T121,T128,T123 INPUT
ast_alert_i.alerts[3].n Yes Yes T121,T130,T123 Yes T130 INPUT
ast_alert_i.alerts[3].p Yes Yes T130 Yes T121,T130,T123 INPUT
ast_alert_i.alerts[4].n Yes Yes T121,T131,T123 Yes T131,T125 INPUT
ast_alert_i.alerts[4].p Yes Yes T131,T125 Yes T121,T131,T123 INPUT
ast_alert_i.alerts[5].n No Yes T121,T123,T124 No INPUT
ast_alert_i.alerts[5].p No No Yes T121,T123,T124 INPUT
ast_alert_i.alerts[6].n Yes Yes T121,T128,T123 Yes T128,T129 INPUT
ast_alert_i.alerts[6].p Yes Yes T128,T129 Yes T121,T128,T123 INPUT
ast_alert_i.alerts[7].n Yes Yes T121,T107,T134 Yes T107,T134,T135 INPUT
ast_alert_i.alerts[7].p Yes Yes T107,T134,T135 Yes T121,T107,T134 INPUT
ast_alert_i.alerts[8].n Yes Yes T121,T107,T134 Yes T107,T134,T135 INPUT
ast_alert_i.alerts[8].p Yes Yes T107,T134,T135 Yes T121,T107,T134 INPUT
ast_alert_i.alerts[9].n No Yes T121,T123,T124 No INPUT
ast_alert_i.alerts[9].p No No Yes T121,T123,T124 INPUT
ast_alert_i.alerts[10].n No Yes T121,T123,T124 No INPUT
ast_alert_i.alerts[10].p No No Yes T121,T123,T124 INPUT
ast_alert_o.alerts_trig[0].n Yes Yes T121,T122,T14 Yes T121,T122,T14 OUTPUT
ast_alert_o.alerts_trig[0].p Yes Yes T121,T122,T14 Yes T121,T122,T14 OUTPUT
ast_alert_o.alerts_trig[1].n Yes Yes T121,T123,T124 Yes T121,T123,T124 OUTPUT
ast_alert_o.alerts_trig[1].p Yes Yes T121,T123,T124 Yes T121,T123,T124 OUTPUT
ast_alert_o.alerts_trig[2].n Yes Yes T121,T128,T123 Yes T121,T128,T123 OUTPUT
ast_alert_o.alerts_trig[2].p Yes Yes T121,T128,T123 Yes T121,T128,T123 OUTPUT
ast_alert_o.alerts_trig[3].n Yes Yes T121,T130,T123 Yes T121,T130,T123 OUTPUT
ast_alert_o.alerts_trig[3].p Yes Yes T121,T130,T123 Yes T121,T130,T123 OUTPUT
ast_alert_o.alerts_trig[4].n Yes Yes T121,T131,T123 Yes T121,T131,T123 OUTPUT
ast_alert_o.alerts_trig[4].p Yes Yes T121,T131,T123 Yes T121,T131,T123 OUTPUT
ast_alert_o.alerts_trig[5].n Yes Yes T121,T123,T124 Yes T121,T123,T124 OUTPUT
ast_alert_o.alerts_trig[5].p Yes Yes T121,T123,T124 Yes T121,T123,T124 OUTPUT
ast_alert_o.alerts_trig[6].n Yes Yes T121,T128,T123 Yes T121,T128,T123 OUTPUT
ast_alert_o.alerts_trig[6].p Yes Yes T121,T128,T123 Yes T121,T128,T123 OUTPUT
ast_alert_o.alerts_trig[7].n Yes Yes T121,T107,T134 Yes T121,T107,T134 OUTPUT
ast_alert_o.alerts_trig[7].p Yes Yes T121,T107,T134 Yes T121,T107,T134 OUTPUT
ast_alert_o.alerts_trig[8].n Yes Yes T121,T107,T134 Yes T121,T107,T134 OUTPUT
ast_alert_o.alerts_trig[8].p Yes Yes T121,T107,T134 Yes T121,T107,T134 OUTPUT
ast_alert_o.alerts_trig[9].n Yes Yes T121,T123,T124 Yes T121,T123,T124 OUTPUT
ast_alert_o.alerts_trig[9].p Yes Yes T121,T123,T124 Yes T121,T123,T124 OUTPUT
ast_alert_o.alerts_trig[10].n Yes Yes T121,T123,T124 Yes T121,T123,T124 OUTPUT
ast_alert_o.alerts_trig[10].p Yes Yes T121,T123,T124 Yes T121,T123,T124 OUTPUT
ast_alert_o.alerts_ack[0].n Yes Yes T121,T122,T14 Yes T121,T122,T14 OUTPUT
ast_alert_o.alerts_ack[0].p Yes Yes T121,T122,T14 Yes T121,T122,T14 OUTPUT
ast_alert_o.alerts_ack[1].n Yes Yes T121,T123,T124 Yes T121,T123,T124 OUTPUT
ast_alert_o.alerts_ack[1].p Yes Yes T121,T123,T124 Yes T121,T123,T124 OUTPUT
ast_alert_o.alerts_ack[2].n Yes Yes T121,T128,T123 Yes T121,T128,T123 OUTPUT
ast_alert_o.alerts_ack[2].p Yes Yes T121,T128,T123 Yes T121,T128,T123 OUTPUT
ast_alert_o.alerts_ack[3].n Yes Yes T121,T130,T123 Yes T121,T130,T123 OUTPUT
ast_alert_o.alerts_ack[3].p Yes Yes T121,T130,T123 Yes T121,T130,T123 OUTPUT
ast_alert_o.alerts_ack[4].n Yes Yes T121,T131,T123 Yes T121,T131,T123 OUTPUT
ast_alert_o.alerts_ack[4].p Yes Yes T121,T131,T123 Yes T121,T131,T123 OUTPUT
ast_alert_o.alerts_ack[5].n Yes Yes T121,T123,T124 Yes T121,T123,T124 OUTPUT
ast_alert_o.alerts_ack[5].p Yes Yes T121,T123,T124 Yes T121,T123,T124 OUTPUT
ast_alert_o.alerts_ack[6].n Yes Yes T121,T128,T123 Yes T121,T128,T123 OUTPUT
ast_alert_o.alerts_ack[6].p Yes Yes T121,T128,T123 Yes T121,T128,T123 OUTPUT
ast_alert_o.alerts_ack[7].n Yes Yes T121,T107,T134 Yes T121,T107,T134 OUTPUT
ast_alert_o.alerts_ack[7].p Yes Yes T121,T107,T134 Yes T121,T107,T134 OUTPUT
ast_alert_o.alerts_ack[8].n Yes Yes T121,T107,T134 Yes T121,T107,T134 OUTPUT
ast_alert_o.alerts_ack[8].p Yes Yes T121,T107,T134 Yes T121,T107,T134 OUTPUT
ast_alert_o.alerts_ack[9].n Yes Yes T121,T123,T124 Yes T121,T123,T124 OUTPUT
ast_alert_o.alerts_ack[9].p Yes Yes T121,T123,T124 Yes T121,T123,T124 OUTPUT
ast_alert_o.alerts_ack[10].n Yes Yes T121,T123,T124 Yes T121,T123,T124 OUTPUT
ast_alert_o.alerts_ack[10].p Yes Yes T121,T123,T124 Yes T121,T123,T124 OUTPUT
ast_status_i.io_pok[1:0] Yes Yes T120,T136,T137 Yes T4,T5,T6 INPUT
ast2pinmux_i[8:0] Unreachable Unreachable Unreachable INPUT
ast_init_done_i[3:0] Yes Yes T4,T5,T6 Yes T30,T28,T1 INPUT
cio_ast_debug_out_o[8:0] Unreachable Unreachable Unreachable OUTPUT
cio_ast_debug_out_en_o[8:0] Unreachable Unreachable Unreachable OUTPUT
intr_io_status_change_o Yes Yes T346,T147,T148 Yes T346,T147,T148 OUTPUT
intr_init_status_change_o Yes Yes T7,T147,T148 Yes T7,T147,T148 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T60,T121,T107 Yes T60,T121,T107 INPUT
alert_rx_i[0].ping_n Yes Yes T84,T85,T86 Yes T84,T85,T86 INPUT
alert_rx_i[0].ping_p Yes Yes T84,T85,T86 Yes T84,T85,T86 INPUT
alert_rx_i[1].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[1].ack_p Yes Yes T60,T130,T237 Yes T60,T130,T237 INPUT
alert_rx_i[1].ping_n Yes Yes T237,T85,T86 Yes T237,T85,T86 INPUT
alert_rx_i[1].ping_p Yes Yes T237,T85,T86 Yes T237,T85,T86 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T60,T121,T107 Yes T60,T121,T107 OUTPUT
alert_tx_o[1].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[1].alert_p Yes Yes T60,T130,T237 Yes T60,T130,T237 OUTPUT
wkup_req_o Yes Yes T121,T107,T130 Yes T121,T107,T130 OUTPUT
manual_pad_attr_o[0].invert No No No OUTPUT
manual_pad_attr_o[0].virt_od_en No No No OUTPUT
manual_pad_attr_o[0].pull_en Yes Yes T38,T39,T40 Yes T38,T39,T40 OUTPUT
manual_pad_attr_o[0].pull_select Yes Yes T38,T39,T40 Yes T38,T39,T40 OUTPUT
manual_pad_attr_o[0].keep_en No No No OUTPUT
manual_pad_attr_o[0].schmitt_en No No No OUTPUT
manual_pad_attr_o[0].od_en No No No OUTPUT
manual_pad_attr_o[0].input_disable Yes Yes T38,T39,T40 Yes T38,T39,T40 OUTPUT
manual_pad_attr_o[0].slew_rate[1:0] No No No OUTPUT
manual_pad_attr_o[0].drive_strength[3:0] No No No OUTPUT
manual_pad_attr_o[1].invert No No No OUTPUT
manual_pad_attr_o[1].virt_od_en No No No OUTPUT
manual_pad_attr_o[1].pull_en Yes Yes T38,T39,T40 Yes T38,T39,T40 OUTPUT
manual_pad_attr_o[1].pull_select Yes Yes T38,T39,T40 Yes T38,T39,T40 OUTPUT
manual_pad_attr_o[1].keep_en No No No OUTPUT
manual_pad_attr_o[1].schmitt_en No No No OUTPUT
manual_pad_attr_o[1].od_en No No No OUTPUT
manual_pad_attr_o[1].input_disable Yes Yes T38,T39,T40 Yes T38,T39,T40 OUTPUT
manual_pad_attr_o[1].slew_rate[1:0] No No No OUTPUT
manual_pad_attr_o[1].drive_strength[3:0] No No No OUTPUT
manual_pad_attr_o[2].invert No No No OUTPUT
manual_pad_attr_o[2].virt_od_en No No No OUTPUT
manual_pad_attr_o[2].pull_en Yes Yes T38,T39,T40 Yes T38,T39,T40 OUTPUT
manual_pad_attr_o[2].pull_select Yes Yes T38,T39,T40 Yes T38,T39,T40 OUTPUT
manual_pad_attr_o[2].keep_en No No No OUTPUT
manual_pad_attr_o[2].schmitt_en No No No OUTPUT
manual_pad_attr_o[2].od_en No No No OUTPUT
manual_pad_attr_o[2].input_disable Yes Yes T38,T39,T40 Yes T38,T39,T40 OUTPUT
manual_pad_attr_o[2].slew_rate[1:0] No No No OUTPUT
manual_pad_attr_o[2].drive_strength[3:0] No No No OUTPUT
manual_pad_attr_o[3].invert No No No OUTPUT
manual_pad_attr_o[3].virt_od_en No No No OUTPUT
manual_pad_attr_o[3].pull_en Yes Yes T38,T39,T40 Yes T38,T39,T40 OUTPUT
manual_pad_attr_o[3].pull_select Yes Yes T38,T39,T40 Yes T38,T39,T40 OUTPUT
manual_pad_attr_o[3].keep_en No No No OUTPUT
manual_pad_attr_o[3].schmitt_en No No No OUTPUT
manual_pad_attr_o[3].od_en No No No OUTPUT
manual_pad_attr_o[3].input_disable Yes Yes T38,T39,T40 Yes T38,T39,T40 OUTPUT
manual_pad_attr_o[3].slew_rate[1:0] No No No OUTPUT
manual_pad_attr_o[3].drive_strength[3:0] No No No OUTPUT

*Tests covering at least one bit in the range

Branch Coverage for Module : sensor_ctrl
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 330 2 2 100.00
IF 341 2 2 100.00
IF 356 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_0.1/rtl/sensor_ctrl.sv' or '../src/lowrisc_systems_sensor_ctrl_0.1/rtl/sensor_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 330 if ((!rst_aon_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 341 if ((!rst_aon_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 356 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


Assert Coverage for Module : sensor_ctrl
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
FpvSecCmRegWeOnehotCheck_A 137222743 4 0 0
NumAlertsMatch_A 1023 1023 0 0


FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 137222743 4 0 0
T176 17912 0 0 0
T362 60022 1 0 0
T363 0 1 0 0
T364 0 1 0 0
T370 0 1 0 0
T371 46973 0 0 0
T372 41182 0 0 0
T373 60570 0 0 0
T374 68828 0 0 0
T375 23403 0 0 0
T376 24044 0 0 0
T377 92079 0 0 0
T378 36823 0 0 0

NumAlertsMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1023 1023 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T15 1 1 0 0
T28 1 1 0 0
T30 1 1 0 0
T55 1 1 0 0
T87 1 1 0 0
T88 1 1 0 0
T89 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%