Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : xbar_main
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_xbar_main 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : xbar_main
TotalCoveredPercent
Totals 550 550 100.00
Total Bits 6824 6824 100.00
Total Bits 0->1 3412 3412 100.00
Total Bits 1->0 3412 3412 100.00

Ports 550 550 100.00
Port Bits 6824 6824 100.00
Port Bits 0->1 3412 3412 100.00
Port Bits 1->0 3412 3412 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_main_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_fixed_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_usb_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_spi_host0_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_spi_host1_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_main_ni Yes Yes T30,T28,T1 Yes T4,T5,T6 INPUT
rst_fixed_ni Yes Yes T30,T28,T1 Yes T4,T5,T6 INPUT
rst_usb_ni Yes Yes T30,T28,T1 Yes T4,T5,T6 INPUT
rst_spi_host0_ni Yes Yes T30,T28,T1 Yes T4,T5,T6 INPUT
rst_spi_host1_ni Yes Yes T30,T28,T1 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__corei_i.d_ready Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0] Yes Yes T78,T80,T82 Yes T78,T80,T82 INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_data[31:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_rv_core_ibex__corei_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__corei_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_rv_core_ibex__corei_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_rv_core_ibex__corei_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__corei_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_error Yes Yes T215,T216,T53 Yes T215,T216,T53 OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0] Yes Yes T67,T215,T216 Yes T67,T215,T216 OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_sink Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_i.d_ready Yes Yes T16,T58,T7 Yes T16,T58,T7 INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0] Yes Yes T16,T78,T80 Yes T16,T78,T80 INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_size[1:0] Yes Yes T16,T78,T79 Yes T16,T78,T79 INPUT
tl_rv_core_ibex__cored_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cored_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_error Yes Yes T41,T66,T67 Yes T41,T66,T67 OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_sink Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_dm__sba_i.d_ready Yes Yes T30,T28,T1 Yes T4,T5,T6 INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0] Yes Yes T16,T58,T68 Yes T16,T58,T68 INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0] Yes Yes T30,T28,T1 Yes T4,T5,T6 INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0] Yes Yes T30,T28,T1 Yes T4,T5,T6 INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_data[31:0] Yes Yes T16,T58,T68 Yes T16,T58,T68 INPUT
tl_rv_dm__sba_i.a_mask[3:0] Yes Yes T30,T28,T1 Yes T4,T5,T6 INPUT
tl_rv_dm__sba_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_source[5:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_rv_dm__sba_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_rv_dm__sba_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_opcode[2:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_rv_dm__sba_i.a_valid Yes Yes T16,T58,T68 Yes T16,T58,T68 INPUT
tl_rv_dm__sba_o.a_ready Yes Yes T30,T28,T1 Yes T4,T5,T6 OUTPUT
tl_rv_dm__sba_o.d_error Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0] Yes Yes T16,T58,T68 Yes T16,T58,T68 OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0] Yes Yes T16,T58,T68 Yes T16,T58,T68 OUTPUT
tl_rv_dm__sba_o.d_data[31:0] Yes Yes T16,T58,T68 Yes T16,T58,T68 OUTPUT
tl_rv_dm__sba_o.d_sink Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_rv_dm__sba_o.d_source[5:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_rv_dm__sba_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_rv_dm__sba_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_opcode[0] Yes Yes *T16,*T58,*T68 Yes T16,T58,T68 OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_valid Yes Yes T16,T58,T68 Yes T16,T58,T68 OUTPUT
tl_rv_dm__regs_o.d_ready Yes Yes T30,T28,T1 Yes T4,T5,T6 OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0] Yes Yes T7,T78,T79 Yes T7,T78,T79 OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0] Yes Yes T7,T78,T79 Yes T7,T78,T79 OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0] Yes Yes T7,T78,T79 Yes T7,T78,T79 OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_data[31:0] Yes Yes T7,T78,T79 Yes T7,T78,T79 OUTPUT
tl_rv_dm__regs_o.a_mask[3:0] Yes Yes T7,T78,T79 Yes T7,T78,T79 OUTPUT
tl_rv_dm__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_source[5:0] Yes Yes *T7,T78,T79 Yes T7,T78,T79 OUTPUT
tl_rv_dm__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_rv_dm__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_rv_dm__regs_o.a_valid Yes Yes T7,T78,T79 Yes T7,T78,T79 OUTPUT
tl_rv_dm__regs_i.a_ready Yes Yes T7,T78,T79 Yes T7,T78,T79 INPUT
tl_rv_dm__regs_i.d_error Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0] Yes Yes T7,T78,T79 Yes T7,T78,T79 INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0] Yes Yes T7,T78,T79 Yes T7,T78,T79 INPUT
tl_rv_dm__regs_i.d_data[31:0] Yes Yes T7,T78,T79 Yes T7,T78,T79 INPUT
tl_rv_dm__regs_i.d_sink Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_rv_dm__regs_i.d_source[5:0] Yes Yes *T7,T78,T79 Yes T7,T78,T79 INPUT
tl_rv_dm__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_rv_dm__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_opcode[0] Yes Yes *T7,*T78,*T79 Yes T7,T78,T79 INPUT
tl_rv_dm__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_valid Yes Yes T7,T78,T79 Yes T7,T78,T79 INPUT
tl_rv_dm__mem_o.d_ready Yes Yes T30,T28,T1 Yes T4,T5,T6 OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0] Yes Yes T81,T252,T7 Yes T81,T252,T7 OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0] Yes Yes T81,T252,T7 Yes T81,T252,T7 OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0] Yes Yes T81,T252,T7 Yes T81,T252,T7 OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_data[31:0] Yes Yes T81,T252,T7 Yes T81,T252,T7 OUTPUT
tl_rv_dm__mem_o.a_mask[3:0] Yes Yes T81,T252,T7 Yes T81,T252,T7 OUTPUT
tl_rv_dm__mem_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_source[5:0] Yes Yes *T81,*T252,*T253 Yes T81,T252,T253 OUTPUT
tl_rv_dm__mem_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_rv_dm__mem_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_rv_dm__mem_o.a_valid Yes Yes T81,T252,T7 Yes T81,T252,T7 OUTPUT
tl_rv_dm__mem_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_dm__mem_i.d_error Yes Yes T4,T5,T6 Yes T30,T28,T1 INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0] Yes Yes T81,T252,T253 Yes T81,T252,T253 INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0] Yes Yes T81,T252,T7 Yes T81,T252,T7 INPUT
tl_rv_dm__mem_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T30,T28,T1 INPUT
tl_rv_dm__mem_i.d_sink Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_rv_dm__mem_i.d_source[5:0] Yes Yes *T81,*T252,*T253 Yes T81,T252,T253 INPUT
tl_rv_dm__mem_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_rv_dm__mem_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T30,T28,T1 INPUT
tl_rv_dm__mem_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_valid Yes Yes T81,T252,T7 Yes T81,T252,T7 INPUT
tl_rom_ctrl__rom_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0] Yes Yes T55,T56,T16 Yes T55,T56,T16 OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0] Yes Yes T55,T56,T16 Yes T55,T56,T16 OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_rom_ctrl__rom_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_error Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_sink Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_rom_ctrl__rom_i.d_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_rom_ctrl__rom_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_opcode[0] Yes Yes *T78,*T79,*T80 Yes T78,T79,T80 INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__regs_o.d_ready Yes Yes T30,T28,T60 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0] Yes Yes T60,T7,T61 Yes T60,T7,T61 OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0] Yes Yes T60,T344,T263 Yes T60,T344,T263 OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0] Yes Yes T60,T344,T263 Yes T60,T344,T263 OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0] Yes Yes T60,T7,T61 Yes T60,T7,T61 OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0] Yes Yes T60,T344,T263 Yes T60,T344,T263 OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0] Yes Yes *T7,*T78,*T79 Yes T7,T78,T79 OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_rom_ctrl__regs_o.a_valid Yes Yes T60,T344,T263 Yes T60,T344,T263 OUTPUT
tl_rom_ctrl__regs_i.a_ready Yes Yes T60,T344,T263 Yes T60,T344,T263 INPUT
tl_rom_ctrl__regs_i.d_error Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0] Yes Yes T263,T396,T397 Yes T263,T396,T397 INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0] Yes Yes T7,T78,T79 Yes T60,T7,T61 INPUT
tl_rom_ctrl__regs_i.d_data[31:0] Yes Yes T263,T7,T396 Yes T60,T263,T7 INPUT
tl_rom_ctrl__regs_i.d_sink Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_rom_ctrl__regs_i.d_source[5:0] Yes Yes *T7,T78,*T79 Yes T7,T78,T79 INPUT
tl_rom_ctrl__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_rom_ctrl__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_opcode[0] Yes Yes *T344,*T263,*T7 Yes T344,T263,T7 INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_valid Yes Yes T60,T344,T263 Yes T60,T344,T263 INPUT
tl_peri_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_source[5:0] Yes Yes *T16,*T58,*T81 Yes T16,T58,T81 OUTPUT
tl_peri_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_peri_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_opcode[2:0] Yes Yes T16,T58,T7 Yes T16,T58,T7 OUTPUT
tl_peri_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_peri_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_peri_i.d_error Yes Yes T41,T66,T215 Yes T41,T66,T215 INPUT
tl_peri_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_peri_i.d_user.rsp_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_peri_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_peri_i.d_sink Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_peri_i.d_source[5:0] Yes Yes *T16,*T58,*T81 Yes T16,T58,T81 INPUT
tl_peri_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_peri_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_peri_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_spi_host0_o.d_ready Yes Yes T60,T22,T23 Yes T60,T22,T23 OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0] Yes Yes T60,T22,T23 Yes T60,T22,T23 OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0] Yes Yes T60,T22,T23 Yes T60,T22,T23 OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0] Yes Yes T60,T22,T23 Yes T60,T22,T23 OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_data[31:0] Yes Yes T60,T22,T23 Yes T60,T22,T23 OUTPUT
tl_spi_host0_o.a_mask[3:0] Yes Yes T60,T22,T23 Yes T60,T22,T23 OUTPUT
tl_spi_host0_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_source[5:0] Yes Yes *T7,*T78,*T79 Yes T7,T78,T79 OUTPUT
tl_spi_host0_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_spi_host0_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_opcode[2:0] Yes Yes T193,T194,T195 Yes T193,T194,T195 OUTPUT
tl_spi_host0_o.a_valid Yes Yes T60,T22,T23 Yes T60,T22,T23 OUTPUT
tl_spi_host0_i.a_ready Yes Yes T60,T22,T23 Yes T60,T22,T23 INPUT
tl_spi_host0_i.d_error Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_spi_host0_i.d_user.data_intg[6:0] Yes Yes T22,T23,T24 Yes T22,T23,T24 INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0] Yes Yes T22,T23,T24 Yes T60,T22,T23 INPUT
tl_spi_host0_i.d_data[31:0] Yes Yes T22,T23,T24 Yes T22,T23,T24 INPUT
tl_spi_host0_i.d_sink Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_spi_host0_i.d_source[5:0] Yes Yes *T7,*T78,*T79 Yes T7,T78,T79 INPUT
tl_spi_host0_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_spi_host0_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_opcode[0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 INPUT
tl_spi_host0_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_valid Yes Yes T60,T22,T23 Yes T60,T22,T23 INPUT
tl_spi_host1_o.d_ready Yes Yes T60,T382,T392 Yes T60,T382,T392 OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0] Yes Yes T60,T382,T7 Yes T60,T382,T7 OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0] Yes Yes T60,T382,T392 Yes T60,T382,T392 OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0] Yes Yes T60,T382,T392 Yes T60,T382,T392 OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_data[31:0] Yes Yes T60,T382,T7 Yes T60,T382,T7 OUTPUT
tl_spi_host1_o.a_mask[3:0] Yes Yes T60,T382,T392 Yes T60,T382,T392 OUTPUT
tl_spi_host1_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_source[5:0] Yes Yes *T7,*T78,*T79 Yes T7,T78,T79 OUTPUT
tl_spi_host1_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_spi_host1_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_opcode[2:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_spi_host1_o.a_valid Yes Yes T60,T382,T392 Yes T60,T382,T392 OUTPUT
tl_spi_host1_i.a_ready Yes Yes T60,T382,T392 Yes T60,T382,T392 INPUT
tl_spi_host1_i.d_error Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_spi_host1_i.d_user.data_intg[6:0] Yes Yes T382,T7,T43 Yes T382,T7,T43 INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0] Yes Yes T382,T392,T7 Yes T60,T382,T392 INPUT
tl_spi_host1_i.d_data[31:0] Yes Yes T382,T7,T43 Yes T382,T7,T43 INPUT
tl_spi_host1_i.d_sink Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_spi_host1_i.d_source[5:0] Yes Yes *T7,*T78,*T79 Yes T7,T78,T79 INPUT
tl_spi_host1_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_spi_host1_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_opcode[0] Yes Yes *T382,*T392,*T7 Yes T382,T392,T7 INPUT
tl_spi_host1_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_valid Yes Yes T60,T382,T392 Yes T60,T382,T392 INPUT
tl_usbdev_o.d_ready Yes Yes T28,T60,T1 Yes T28,T60,T1 OUTPUT
tl_usbdev_o.a_user.data_intg[6:0] Yes Yes T28,T60,T1 Yes T28,T60,T1 OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0] Yes Yes T28,T60,T1 Yes T28,T60,T1 OUTPUT
tl_usbdev_o.a_user.instr_type[3:0] Yes Yes T28,T60,T1 Yes T28,T60,T1 OUTPUT
tl_usbdev_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_data[31:0] Yes Yes T28,T60,T1 Yes T28,T60,T1 OUTPUT
tl_usbdev_o.a_mask[3:0] Yes Yes T28,T60,T1 Yes T28,T60,T1 OUTPUT
tl_usbdev_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_source[5:0] Yes Yes *T78,*T79,*T80 Yes T78,T79,T80 OUTPUT
tl_usbdev_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_usbdev_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_opcode[2:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_usbdev_o.a_valid Yes Yes T28,T60,T1 Yes T28,T60,T1 OUTPUT
tl_usbdev_i.a_ready Yes Yes T28,T60,T1 Yes T28,T60,T1 INPUT
tl_usbdev_i.d_error Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_usbdev_i.d_user.data_intg[6:0] Yes Yes T306,T29,T382 Yes T306,T29,T382 INPUT
tl_usbdev_i.d_user.rsp_intg[6:0] Yes Yes T306,T29,T382 Yes T306,T29,T382 INPUT
tl_usbdev_i.d_data[31:0] Yes Yes T28,T60,T1 Yes T28,T1,T306 INPUT
tl_usbdev_i.d_sink Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_usbdev_i.d_source[5:0] Yes Yes *T78,*T79,*T80 Yes T78,T79,T80 INPUT
tl_usbdev_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_usbdev_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_opcode[0] Yes Yes *T28,*T60,*T1 Yes T28,T1,T306 INPUT
tl_usbdev_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_valid Yes Yes T28,T60,T1 Yes T28,T60,T1 INPUT
tl_flash_ctrl__core_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_source[5:0] Yes Yes *T58,*T78,*T79 Yes T58,T78,T79 OUTPUT
tl_flash_ctrl__core_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_flash_ctrl__core_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_flash_ctrl__core_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_error Yes Yes T4,T5,T6 Yes T30,T28,T1 INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T30,T28,T55 INPUT
tl_flash_ctrl__core_i.d_sink Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_flash_ctrl__core_i.d_source[5:0] Yes Yes *T58,*T78,*T79 Yes T58,T78,T79 INPUT
tl_flash_ctrl__core_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_flash_ctrl__core_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__prim_o.d_ready Yes Yes T30,T28,T1 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0] Yes Yes T58,T78,T79 Yes T58,T78,T79 OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0] Yes Yes T58,T78,T79 Yes T58,T78,T79 OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0] Yes Yes T58,T78,T79 Yes T58,T78,T79 OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0] Yes Yes T58,T78,T79 Yes T58,T78,T79 OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0] Yes Yes T58,T78,T79 Yes T58,T78,T79 OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0] Yes Yes *T58,T78,T79 Yes T58,T78,T79 OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_flash_ctrl__prim_o.a_valid Yes Yes T58,T78,T79 Yes T58,T78,T79 OUTPUT
tl_flash_ctrl__prim_i.a_ready Yes Yes T58,T78,T79 Yes T58,T78,T79 INPUT
tl_flash_ctrl__prim_i.d_error Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0] Yes Yes T58,T78,T79 Yes T58,T78,T79 INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0] Yes Yes T58,T78,T79 Yes T58,T78,T79 INPUT
tl_flash_ctrl__prim_i.d_data[31:0] Yes Yes T58,T78,T79 Yes T58,T78,T79 INPUT
tl_flash_ctrl__prim_i.d_sink Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_flash_ctrl__prim_i.d_source[5:0] Yes Yes *T58,T78,T79 Yes T58,T78,T79 INPUT
tl_flash_ctrl__prim_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_flash_ctrl__prim_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_opcode[0] Yes Yes *T58,*T78,*T79 Yes T58,T78,T79 INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_valid Yes Yes T58,T78,T79 Yes T58,T78,T79 INPUT
tl_flash_ctrl__mem_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0] Yes Yes T4,T5,T15 Yes T4,T5,T15 OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_flash_ctrl__mem_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_error Yes Yes T4,T5,T6 Yes T30,T28,T1 INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_sink Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_flash_ctrl__mem_i.d_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_flash_ctrl__mem_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_opcode[0] Yes Yes *T78,*T79,*T80 Yes T78,T79,T80 INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_hmac_o.d_ready Yes Yes T30,T28,T55 Yes T4,T5,T6 OUTPUT
tl_hmac_o.a_user.data_intg[6:0] Yes Yes T55,T60,T56 Yes T55,T60,T56 OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0] Yes Yes T55,T60,T56 Yes T55,T60,T56 OUTPUT
tl_hmac_o.a_user.instr_type[3:0] Yes Yes T55,T60,T56 Yes T55,T60,T56 OUTPUT
tl_hmac_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_data[31:0] Yes Yes T55,T60,T56 Yes T55,T60,T56 OUTPUT
tl_hmac_o.a_mask[3:0] Yes Yes T55,T60,T56 Yes T55,T60,T56 OUTPUT
tl_hmac_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_source[5:0] Yes Yes *T58,*T78,*T79 Yes T58,T78,T79 OUTPUT
tl_hmac_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_hmac_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_opcode[2:0] Yes Yes T701,T366,T702 Yes T701,T366,T702 OUTPUT
tl_hmac_o.a_valid Yes Yes T55,T60,T56 Yes T55,T60,T56 OUTPUT
tl_hmac_i.a_ready Yes Yes T55,T60,T56 Yes T55,T60,T56 INPUT
tl_hmac_i.d_error Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_hmac_i.d_user.data_intg[6:0] Yes Yes T55,T56,T57 Yes T55,T56,T57 INPUT
tl_hmac_i.d_user.rsp_intg[6:0] Yes Yes T55,T56,T57 Yes T55,T56,T57 INPUT
tl_hmac_i.d_data[31:0] Yes Yes T55,T60,T56 Yes T55,T56,T57 INPUT
tl_hmac_i.d_sink Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_hmac_i.d_source[5:0] Yes Yes *T58,*T78,*T79 Yes T58,T78,T79 INPUT
tl_hmac_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_hmac_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_opcode[0] Yes Yes *T55,*T60,*T56 Yes T55,T56,T57 INPUT
tl_hmac_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_valid Yes Yes T55,T60,T56 Yes T55,T60,T56 INPUT
tl_kmac_o.d_ready Yes Yes T30,T28,T60 Yes T4,T5,T6 OUTPUT
tl_kmac_o.a_user.data_intg[6:0] Yes Yes T60,T431,T217 Yes T60,T431,T217 OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0] Yes Yes T60,T113,T160 Yes T60,T113,T160 OUTPUT
tl_kmac_o.a_user.instr_type[3:0] Yes Yes T60,T113,T160 Yes T60,T113,T160 OUTPUT
tl_kmac_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_data[31:0] Yes Yes T60,T431,T217 Yes T60,T431,T217 OUTPUT
tl_kmac_o.a_mask[3:0] Yes Yes T60,T113,T160 Yes T60,T113,T160 OUTPUT
tl_kmac_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_source[5:0] Yes Yes *T58,*T78,*T79 Yes T58,T78,T79 OUTPUT
tl_kmac_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_kmac_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_opcode[2:0] Yes Yes T431,T432,T224 Yes T431,T432,T224 OUTPUT
tl_kmac_o.a_valid Yes Yes T60,T113,T160 Yes T60,T113,T160 OUTPUT
tl_kmac_i.a_ready Yes Yes T60,T113,T160 Yes T60,T113,T160 INPUT
tl_kmac_i.d_error Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_kmac_i.d_user.data_intg[6:0] Yes Yes T113,T160,T431 Yes T113,T160,T431 INPUT
tl_kmac_i.d_user.rsp_intg[6:0] Yes Yes T113,T160,T431 Yes T113,T160,T431 INPUT
tl_kmac_i.d_data[31:0] Yes Yes T60,T113,T160 Yes T160,T431,T218 INPUT
tl_kmac_i.d_sink Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_kmac_i.d_source[5:0] Yes Yes *T58,*T78,*T79 Yes T58,T78,T79 INPUT
tl_kmac_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_kmac_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_opcode[0] Yes Yes *T60,*T113,*T160 Yes T160,T431,T218 INPUT
tl_kmac_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_valid Yes Yes T60,T113,T160 Yes T60,T113,T160 INPUT
tl_aes_o.d_ready Yes Yes T6,T30,T28 Yes T4,T5,T6 OUTPUT
tl_aes_o.a_user.data_intg[6:0] Yes Yes T6,T60,T110 Yes T6,T60,T110 OUTPUT
tl_aes_o.a_user.cmd_intg[6:0] Yes Yes T6,T60,T110 Yes T6,T60,T110 OUTPUT
tl_aes_o.a_user.instr_type[3:0] Yes Yes T6,T60,T110 Yes T6,T60,T110 OUTPUT
tl_aes_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_data[31:0] Yes Yes T6,T60,T110 Yes T6,T60,T110 OUTPUT
tl_aes_o.a_mask[3:0] Yes Yes T6,T60,T110 Yes T6,T60,T110 OUTPUT
tl_aes_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_source[5:0] Yes Yes *T196,*T78,*T79 Yes T196,T78,T79 OUTPUT
tl_aes_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_aes_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_opcode[2:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_aes_o.a_valid Yes Yes T6,T60,T110 Yes T6,T60,T110 OUTPUT
tl_aes_i.a_ready Yes Yes T6,T60,T110 Yes T6,T60,T110 INPUT
tl_aes_i.d_error Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_aes_i.d_user.data_intg[6:0] Yes Yes T6,T110,T113 Yes T6,T110,T113 INPUT
tl_aes_i.d_user.rsp_intg[6:0] Yes Yes T6,T110,T113 Yes T6,T60,T110 INPUT
tl_aes_i.d_data[31:0] Yes Yes T6,T110,T657 Yes T6,T60,T110 INPUT
tl_aes_i.d_sink Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_aes_i.d_source[5:0] Yes Yes *T196,*T78,*T79 Yes T196,T78,T79 INPUT
tl_aes_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_aes_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_opcode[0] Yes Yes *T6,*T110,*T113 Yes T6,T110,T113 INPUT
tl_aes_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_valid Yes Yes T6,T60,T110 Yes T6,T60,T110 INPUT
tl_entropy_src_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_source[5:0] Yes Yes *T58,*T78,*T79 Yes T58,T78,T79 OUTPUT
tl_entropy_src_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_entropy_src_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_opcode[2:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_entropy_src_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_entropy_src_i.d_error Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_entropy_src_i.d_user.data_intg[6:0] Yes Yes T88,T106,T113 Yes T88,T106,T113 INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0] Yes Yes T30,T88,T28 Yes T4,T5,T6 INPUT
tl_entropy_src_i.d_data[31:0] Yes Yes T30,T88,T28 Yes T4,T5,T6 INPUT
tl_entropy_src_i.d_sink Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_entropy_src_i.d_source[5:0] Yes Yes *T58,*T78,*T79 Yes T58,T78,T79 INPUT
tl_entropy_src_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_entropy_src_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_opcode[0] Yes Yes *T88,*T106,*T113 Yes T88,T55,T56 INPUT
tl_entropy_src_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_csrng_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_data[31:0] Yes Yes T88,T60,T110 Yes T88,T60,T110 OUTPUT
tl_csrng_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_source[5:0] Yes Yes *T58,*T196,*T78 Yes T58,T196,T78 OUTPUT
tl_csrng_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_csrng_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_opcode[2:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_csrng_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_csrng_i.d_error Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_csrng_i.d_user.data_intg[6:0] Yes Yes T88,T110,T106 Yes T88,T110,T106 INPUT
tl_csrng_i.d_user.rsp_intg[6:0] Yes Yes T30,T88,T28 Yes T4,T5,T6 INPUT
tl_csrng_i.d_data[31:0] Yes Yes T30,T28,T110 Yes T4,T5,T6 INPUT
tl_csrng_i.d_sink Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_csrng_i.d_source[5:0] Yes Yes *T58,*T196,*T78 Yes T58,T196,T78 INPUT
tl_csrng_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_csrng_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_opcode[0] Yes Yes *T88,*T110,*T106 Yes T88,T110,T106 INPUT
tl_csrng_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_edn0_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_user.data_intg[6:0] Yes Yes T88,T60,T110 Yes T88,T60,T110 OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_data[31:0] Yes Yes T88,T60,T110 Yes T88,T60,T110 OUTPUT
tl_edn0_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_source[5:0] Yes Yes *T58,*T78,*T79 Yes T58,T78,T79 OUTPUT
tl_edn0_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_edn0_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_opcode[2:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_edn0_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_edn0_i.d_error Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_edn0_i.d_user.data_intg[6:0] Yes Yes T88,T110,T106 Yes T88,T110,T106 INPUT
tl_edn0_i.d_user.rsp_intg[6:0] Yes Yes T30,T88,T28 Yes T4,T5,T6 INPUT
tl_edn0_i.d_data[31:0] Yes Yes T30,T88,T28 Yes T4,T5,T6 INPUT
tl_edn0_i.d_sink Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_edn0_i.d_source[5:0] Yes Yes *T58,*T78,*T79 Yes T58,T78,T79 INPUT
tl_edn0_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_edn0_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_opcode[0] Yes Yes *T88,*T110,*T106 Yes T88,T110,T106 INPUT
tl_edn0_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_edn1_o.d_ready Yes Yes T30,T88,T28 Yes T4,T5,T6 OUTPUT
tl_edn1_o.a_user.data_intg[6:0] Yes Yes T88,T60,T106 Yes T88,T60,T106 OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0] Yes Yes T88,T60,T106 Yes T88,T60,T106 OUTPUT
tl_edn1_o.a_user.instr_type[3:0] Yes Yes T88,T60,T106 Yes T88,T60,T106 OUTPUT
tl_edn1_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_data[31:0] Yes Yes T88,T60,T106 Yes T88,T60,T106 OUTPUT
tl_edn1_o.a_mask[3:0] Yes Yes T88,T60,T106 Yes T88,T60,T106 OUTPUT
tl_edn1_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_source[5:0] Yes Yes *T58,*T78,*T79 Yes T58,T78,T79 OUTPUT
tl_edn1_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_edn1_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_opcode[2:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_edn1_o.a_valid Yes Yes T88,T60,T106 Yes T88,T60,T106 OUTPUT
tl_edn1_i.a_ready Yes Yes T88,T60,T106 Yes T88,T60,T106 INPUT
tl_edn1_i.d_error Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_edn1_i.d_user.data_intg[6:0] Yes Yes T88,T106,T113 Yes T88,T106,T113 INPUT
tl_edn1_i.d_user.rsp_intg[6:0] Yes Yes T106,T113,T107 Yes T88,T60,T106 INPUT
tl_edn1_i.d_data[31:0] Yes Yes T106,T113,T107 Yes T88,T60,T106 INPUT
tl_edn1_i.d_sink Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_edn1_i.d_source[5:0] Yes Yes *T58,*T78,*T79 Yes T58,T78,T79 INPUT
tl_edn1_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_edn1_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_opcode[0] Yes Yes *T88,*T106,*T113 Yes T88,T106,T113 INPUT
tl_edn1_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_valid Yes Yes T88,T60,T106 Yes T88,T60,T106 INPUT
tl_rv_plic_o.d_ready Yes Yes T4,T5,T30 Yes T4,T5,T6 OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0] Yes Yes T4,T5,T15 Yes T4,T5,T15 OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T15 Yes T4,T5,T15 OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0] Yes Yes T4,T5,T15 Yes T4,T5,T15 OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_data[31:0] Yes Yes T4,T15,T60 Yes T4,T15,T60 OUTPUT
tl_rv_plic_o.a_mask[3:0] Yes Yes T4,T5,T15 Yes T4,T5,T15 OUTPUT
tl_rv_plic_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_source[5:0] Yes Yes *T7,*T78,*T79 Yes T7,T78,T79 OUTPUT
tl_rv_plic_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_rv_plic_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_opcode[2:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_rv_plic_o.a_valid Yes Yes T4,T5,T15 Yes T4,T5,T15 OUTPUT
tl_rv_plic_i.a_ready Yes Yes T4,T5,T15 Yes T4,T5,T15 INPUT
tl_rv_plic_i.d_error Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_rv_plic_i.d_user.data_intg[6:0] Yes Yes T4,T15,T1 Yes T4,T15,T1 INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0] Yes Yes T4,T5,T15 Yes T4,T5,T15 INPUT
tl_rv_plic_i.d_data[31:0] Yes Yes T4,T5,T15 Yes T4,T5,T15 INPUT
tl_rv_plic_i.d_sink Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_rv_plic_i.d_source[5:0] Yes Yes *T7,*T78,*T79 Yes T7,T78,T79 INPUT
tl_rv_plic_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_rv_plic_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_opcode[0] Yes Yes *T4,*T5,*T15 Yes T4,T5,T15 INPUT
tl_rv_plic_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_valid Yes Yes T4,T5,T15 Yes T4,T5,T15 INPUT
tl_otbn_o.d_ready Yes Yes T30,T28,T55 Yes T4,T5,T6 OUTPUT
tl_otbn_o.a_user.data_intg[6:0] Yes Yes T55,T60,T56 Yes T55,T60,T56 OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0] Yes Yes T55,T60,T56 Yes T55,T60,T56 OUTPUT
tl_otbn_o.a_user.instr_type[3:0] Yes Yes T55,T60,T56 Yes T55,T60,T56 OUTPUT
tl_otbn_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_data[31:0] Yes Yes T55,T60,T56 Yes T55,T60,T56 OUTPUT
tl_otbn_o.a_mask[3:0] Yes Yes T55,T60,T56 Yes T55,T60,T56 OUTPUT
tl_otbn_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_source[5:0] Yes Yes *T16,*T58,*T197 Yes T16,T58,T197 OUTPUT
tl_otbn_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_otbn_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_opcode[2:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_otbn_o.a_valid Yes Yes T55,T60,T56 Yes T55,T60,T56 OUTPUT
tl_otbn_i.a_ready Yes Yes T55,T60,T56 Yes T55,T60,T56 INPUT
tl_otbn_i.d_error Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_otbn_i.d_user.data_intg[6:0] Yes Yes T55,T56,T106 Yes T55,T56,T106 INPUT
tl_otbn_i.d_user.rsp_intg[6:0] Yes Yes T55,T56,T106 Yes T55,T56,T106 INPUT
tl_otbn_i.d_data[31:0] Yes Yes T55,T60,T56 Yes T55,T56,T106 INPUT
tl_otbn_i.d_sink Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_otbn_i.d_source[5:0] Yes Yes *T16,*T58,*T197 Yes T16,T58,T197 INPUT
tl_otbn_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_otbn_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_opcode[0] Yes Yes *T55,*T60,*T56 Yes T55,T56,T106 INPUT
tl_otbn_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_valid Yes Yes T55,T60,T56 Yes T55,T60,T56 INPUT
tl_keymgr_o.d_ready Yes Yes T30,T28,T55 Yes T4,T5,T6 OUTPUT
tl_keymgr_o.a_user.data_intg[6:0] Yes Yes T55,T60,T56 Yes T55,T60,T56 OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0] Yes Yes T55,T60,T56 Yes T55,T60,T56 OUTPUT
tl_keymgr_o.a_user.instr_type[3:0] Yes Yes T55,T60,T56 Yes T55,T60,T56 OUTPUT
tl_keymgr_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_data[31:0] Yes Yes T55,T60,T113 Yes T55,T60,T113 OUTPUT
tl_keymgr_o.a_mask[3:0] Yes Yes T55,T60,T56 Yes T55,T60,T56 OUTPUT
tl_keymgr_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_source[5:0] Yes Yes *T58,*T78,*T79 Yes T58,T78,T79 OUTPUT
tl_keymgr_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_keymgr_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_opcode[2:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_keymgr_o.a_valid Yes Yes T55,T60,T56 Yes T55,T60,T56 OUTPUT
tl_keymgr_i.a_ready Yes Yes T55,T60,T56 Yes T55,T60,T56 INPUT
tl_keymgr_i.d_error Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_keymgr_i.d_user.data_intg[6:0] Yes Yes T113,T160,T217 Yes T113,T160,T217 INPUT
tl_keymgr_i.d_user.rsp_intg[6:0] Yes Yes T55,T56,T113 Yes T55,T60,T56 INPUT
tl_keymgr_i.d_data[31:0] Yes Yes T55,T56,T113 Yes T55,T60,T56 INPUT
tl_keymgr_i.d_sink Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_keymgr_i.d_source[5:0] Yes Yes *T58,*T78,*T79 Yes T58,T78,T79 INPUT
tl_keymgr_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_keymgr_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_opcode[0] Yes Yes *T55,*T56,*T113 Yes T55,T56,T113 INPUT
tl_keymgr_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_valid Yes Yes T55,T60,T56 Yes T55,T60,T56 INPUT
tl_rv_core_ibex__cfg_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0] Yes Yes *T7,*T253,*T254 Yes T7,T253,T254 OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_rv_core_ibex__cfg_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cfg_i.d_error Yes Yes T7,T78,T79 Yes T7,T78,T79 INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0] Yes Yes T4,T5,T15 Yes T4,T5,T15 INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0] Yes Yes T4,T5,T15 Yes T4,T5,T15 INPUT
tl_rv_core_ibex__cfg_i.d_sink Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0] Yes Yes *T7,*T78,*T79 Yes T7,T253,T254 INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__regs_o.d_ready Yes Yes T30,T28,T55 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0] Yes Yes T55,T60,T56 Yes T55,T60,T56 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0] Yes Yes T55,T60,T56 Yes T55,T60,T56 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0] Yes Yes T55,T60,T56 Yes T55,T60,T56 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0] Yes Yes T55,T60,T56 Yes T55,T60,T56 OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0] Yes Yes T55,T60,T56 Yes T55,T60,T56 OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0] Yes Yes *T7,*T422,*T423 Yes T7,T422,T423 OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_sram_ctrl_main__regs_o.a_valid Yes Yes T55,T60,T56 Yes T55,T60,T56 OUTPUT
tl_sram_ctrl_main__regs_i.a_ready Yes Yes T55,T60,T56 Yes T55,T60,T56 INPUT
tl_sram_ctrl_main__regs_i.d_error Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0] Yes Yes T175,T7,T302 Yes T175,T7,T302 INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0] Yes Yes T114,T52,T53 Yes T55,T60,T56 INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0] Yes Yes T114,T52,T53 Yes T55,T60,T56 INPUT
tl_sram_ctrl_main__regs_i.d_sink Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0] Yes Yes *T7,*T78,*T79 Yes T7,T422,T423 INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0] Yes Yes *T114,*T175,*T7 Yes T114,T424,T425 INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_valid Yes Yes T55,T60,T56 Yes T55,T60,T56 INPUT
tl_sram_ctrl_main__ram_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__ram_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_error Yes Yes T4,T5,T6 Yes T30,T28,T1 INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_sink Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%