Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3810189	1			T78	2264		T79	111		T80	97
values[2]	763830	1			T79	53		T80	31		T84	1050
values[3]	107398	1			T80	1		T84	161		T251	13
values[4]	56698	1			T84	142		T251	13		T126	13
values[5]	38358	1			T84	80		T251	13		T126	1
values[6]	28827	1			T84	61		T251	13		T452	149
values[7]	23604	1			T84	60		T251	13		T452	178
values[8]	20231	1			T84	65		T251	13		T452	133
values[9]	17845	1			T84	60		T251	13		T452	85
values[10]	15958	1			T84	90		T251	13		T452	88
values[11]	14805	1			T84	86		T251	13		T452	70
values[12]	14210	1			T84	75		T251	13		T452	74
values[13]	13567	1			T84	46		T251	13		T452	84
values[14]	12813	1			T84	17		T251	13		T452	81
values[15]	12169	1			T84	22		T251	13		T452	65
values[16]	11880	1			T84	38		T251	13		T452	53
values[17]	11648	1			T84	33		T251	13		T452	49
values[18]	11481	1			T84	16		T251	13		T452	57
values[19]	10754	1			T84	14		T251	13		T452	66
values[20]	10693	1			T84	10		T251	13		T452	40
values[21]	10072	1			T84	8		T251	14		T452	28
values[22]	9698	1			T84	10		T251	13		T452	33
values[23]	9300	1			T84	5		T251	13		T452	44
values[24]	8925	1			T84	8		T251	13		T452	35
values[25]	8514	1			T84	4		T251	13		T452	27
values[26]	7894	1			T84	8		T251	13		T452	31
values[27]	8048	1			T84	8		T251	13		T452	40
values[28]	7469	1			T84	6		T251	13		T452	21
values[29]	7253	1			T84	9		T251	14		T452	24
values[30]	6548	1			T84	13		T251	13		T452	17
values[31]	5869	1			T84	5		T251	13		T452	15
values[32]	5561	1			T84	4		T251	13		T452	17
values[33]	5366	1			T84	5		T251	14		T452	18
values[34]	4928	1			T84	6		T251	13		T452	22
values[35]	4621	1			T84	8		T251	13		T452	23
values[36]	4230	1			T84	7		T251	13		T452	22
values[37]	4088	1			T84	5		T251	13		T452	16
values[38]	3999	1			T84	5		T251	13		T452	19
values[39]	3747	1			T84	6		T251	13		T452	16
values[40]	3626	1			T84	9		T251	13		T452	22
values[41]	3551	1			T84	7		T251	13		T452	14
values[42]	3386	1			T84	11		T251	13		T452	18
values[43]	3417	1			T84	10		T251	13		T452	20
values[44]	3314	1			T84	9		T251	14		T452	18
values[45]	3262	1			T84	5		T251	14		T452	14
values[46]	3177	1			T84	5		T251	13		T452	18
values[47]	3139	1			T84	5		T251	13		T452	14
values[48]	3108	1			T84	4		T251	14		T452	15
values[49]	2947	1			T84	6		T251	13		T452	22
values[50]	2933	1			T84	6		T251	13		T452	27
values[51]	2842	1			T84	5		T251	13		T452	17
values[52]	2720	1			T84	5		T251	13		T452	19
values[53]	2639	1			T84	10		T251	13		T452	20
values[54]	2536	1			T84	6		T251	13		T452	13
values[55]	2491	1			T84	4		T251	13		T452	18
values[56]	2452	1			T84	5		T251	13		T452	18
values[57]	2460	1			T84	12		T251	13		T452	24
values[58]	2428	1			T84	7		T251	13		T452	25
values[59]	2450	1			T84	13		T251	14		T452	13
values[60]	2465	1			T84	10		T251	13		T452	11
values[61]	2764	1			T84	13		T251	13		T452	23
values[62]	4229	1			T84	17		T251	13		T452	29
values[63]	11143	1			T84	59		T251	16		T452	123
values[64]	220951	1			T84	206		T251	2203		T452	739

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4867997	1			T78	2313		T79	111		T80	122
values[2]	822703	1			T79	25		T80	32		T84	1674
values[3]	86513	1			T79	1		T80	6		T84	284
values[4]	15226	1			T80	1		T84	87		T251	55
values[5]	5864	1			T84	22		T251	16		T452	1
values[6]	3689	1			T84	11		T251	11		T452	2
values[7]	2753	1			T84	17		T251	3		T452	3
values[8]	2295	1			T84	14		T251	2		T452	5
values[9]	1836	1			T251	1		T452	4		T570	5
values[10]	1678	1			T251	1		T452	2		T570	5
values[11]	1470	1			T251	1		T452	2		T570	5
values[12]	1433	1			T251	1		T452	4		T570	5
values[13]	1294	1			T251	1		T452	1		T570	5
values[14]	1209	1			T251	1		T452	1		T570	5
values[15]	1194	1			T251	1		T452	5		T570	5
values[16]	1128	1			T251	1		T452	9		T570	5
values[17]	977	1			T251	1		T452	11		T570	5
values[18]	932	1			T251	1		T452	6		T570	5
values[19]	932	1			T251	1		T452	1		T570	5
values[20]	928	1			T251	1		T452	6		T570	5
values[21]	863	1			T251	1		T452	6		T570	5
values[22]	780	1			T251	1		T452	2		T570	5
values[23]	796	1			T251	1		T452	1		T570	5
values[24]	722	1			T251	1		T452	1		T570	5
values[25]	732	1			T251	1		T452	3		T570	5
values[26]	637	1			T251	1		T452	1		T570	5
values[27]	626	1			T251	1		T452	2		T570	5
values[28]	589	1			T251	1		T452	4		T570	5
values[29]	587	1			T251	1		T452	2		T570	5
values[30]	554	1			T251	1		T452	8		T570	5
values[31]	597	1			T251	1		T452	8		T570	5
values[32]	516	1			T251	1		T452	9		T570	5
values[33]	482	1			T251	1		T452	2		T570	5
values[34]	495	1			T251	1		T452	1		T570	5
values[35]	482	1			T251	1		T452	3		T570	5
values[36]	489	1			T251	1		T452	2		T570	5
values[37]	477	1			T251	1		T452	1		T570	5
values[38]	463	1			T251	1		T452	1		T570	6
values[39]	474	1			T251	1		T452	1		T570	5
values[40]	441	1			T251	1		T452	1		T570	5
values[41]	426	1			T251	1		T452	2		T570	5
values[42]	444	1			T251	1		T452	1		T570	5
values[43]	434	1			T251	1		T452	1		T570	5
values[44]	417	1			T251	1		T452	3		T570	5
values[45]	390	1			T251	1		T452	10		T570	5
values[46]	400	1			T251	1		T452	3		T570	5
values[47]	369	1			T251	1		T452	3		T570	5
values[48]	384	1			T251	1		T452	1		T570	6
values[49]	402	1			T251	1		T452	2		T570	5
values[50]	390	1			T251	1		T452	4		T570	5
values[51]	393	1			T251	1		T452	6		T570	5
values[52]	403	1			T251	1		T452	3		T570	5
values[53]	390	1			T251	2		T452	4		T570	5
values[54]	399	1			T251	1		T452	1		T570	5
values[55]	399	1			T251	1		T452	2		T570	5
values[56]	364	1			T251	1		T452	2		T570	5
values[57]	348	1			T251	1		T452	2		T570	5
values[58]	389	1			T251	1		T452	4		T570	5
values[59]	353	1			T251	1		T452	5		T570	5
values[60]	364	1			T251	1		T452	4		T570	5
values[61]	416	1			T251	1		T452	11		T570	5
values[62]	693	1			T251	1		T452	4		T570	5
values[63]	2426	1			T251	1		T452	19		T570	5
values[64]	26407	1			T251	153		T452	24		T570	941

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	584666	1			T78	2397		T79	1		T80	2
values[2]	2693404	1			T79	127		T80	8		T84	5037
values[3]	1212434	1			T79	54		T80	113		T84	2253
values[4]	157390	1			T80	5		T84	494		T251	13
values[5]	82884	1			T84	314		T251	13		T126	6
values[6]	52919	1			T84	204		T251	13		T126	9
values[7]	38910	1			T84	139		T251	13		T126	2
values[8]	30928	1			T84	95		T251	13		T452	122
values[9]	25960	1			T84	105		T251	13		T452	97
values[10]	22402	1			T84	74		T251	13		T452	127
values[11]	20184	1			T84	54		T251	13		T452	91
values[12]	18323	1			T84	73		T251	13		T452	91
values[13]	17030	1			T84	60		T251	13		T452	79
values[14]	15790	1			T84	57		T251	13		T452	91
values[15]	14648	1			T84	45		T251	14		T452	93
values[16]	14171	1			T84	45		T251	14		T452	88
values[17]	13591	1			T84	40		T251	13		T452	76
values[18]	13322	1			T84	56		T251	13		T452	64
values[19]	12832	1			T84	31		T251	13		T452	71
values[20]	12286	1			T84	44		T251	13		T452	55
values[21]	11686	1			T84	51		T251	13		T452	52
values[22]	11245	1			T84	40		T251	13		T452	59
values[23]	10964	1			T84	36		T251	13		T452	59
values[24]	10261	1			T84	27		T251	13		T452	30
values[25]	9638	1			T84	22		T251	13		T452	31
values[26]	9364	1			T84	21		T251	13		T452	23
values[27]	9052	1			T84	26		T251	13		T452	34
values[28]	8793	1			T84	17		T251	13		T452	47
values[29]	8257	1			T84	25		T251	13		T452	38
values[30]	7462	1			T84	24		T251	13		T452	41
values[31]	7027	1			T84	12		T251	13		T452	34
values[32]	6432	1			T84	8		T251	14		T452	41
values[33]	6135	1			T84	13		T251	13		T452	30
values[34]	5435	1			T84	23		T251	13		T452	30
values[35]	5212	1			T84	13		T251	13		T452	42
values[36]	4992	1			T84	8		T251	13		T452	39
values[37]	4899	1			T84	15		T251	13		T452	37
values[38]	4639	1			T84	8		T251	14		T452	32
values[39]	4402	1			T84	13		T251	13		T452	19
values[40]	4111	1			T84	21		T251	13		T452	15
values[41]	4007	1			T84	9		T251	13		T452	20
values[42]	3865	1			T84	13		T251	13		T452	23
values[43]	3864	1			T84	12		T251	14		T452	32
values[44]	3781	1			T84	14		T251	13		T452	42
values[45]	3712	1			T84	7		T251	13		T452	47
values[46]	3549	1			T84	8		T251	13		T452	34
values[47]	3485	1			T84	13		T251	13		T452	35
values[48]	3426	1			T84	19		T251	13		T452	39
values[49]	3302	1			T84	6		T251	14		T452	30
values[50]	3274	1			T84	7		T251	13		T452	31
values[51]	3136	1			T84	12		T251	13		T452	29
values[52]	3153	1			T84	11		T251	13		T452	18
values[53]	3204	1			T84	11		T251	13		T452	21
values[54]	3192	1			T84	12		T251	13		T452	14
values[55]	3108	1			T84	14		T251	13		T452	20
values[56]	2960	1			T84	10		T251	13		T452	23
values[57]	2903	1			T84	13		T251	13		T452	30
values[58]	2920	1			T84	17		T251	13		T452	25
values[59]	2865	1			T84	16		T251	13		T452	14
values[60]	2802	1			T84	5		T251	13		T452	38
values[61]	2957	1			T84	9		T251	13		T452	29
values[62]	3938	1			T84	15		T251	14		T452	31
values[63]	9429	1			T84	45		T251	15		T452	91
values[64]	210361	1			T84	140		T251	2351		T452	455