Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1841338	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

37847570

1

T4

10332

T5

10808

T6

6843

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	27753467	1			T4	4084		T5	4452		T6	1611
values[0x0]	10522987	1			T4	6248		T5	6356		T6	5232
values[0x1]	1412454	1			T4	704		T5	764		T6	219

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	602491	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

39086417

1

T4

11036

T5

11572

T6

7062

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18733771	1			T4	5519		T5	5786		T6	3532
valid_sources[0x01]	18732815	1			T4	5517		T5	5786		T6	3530
valid_sources[0x02]	35382	1			T183	160		T408	17		T578	21
valid_sources[0x03]	35605	1			T203	3		T9	1		T183	144
valid_sources[0x04]	35566	1			T203	1		T9	1		T183	151
valid_sources[0x05]	35975	1			T9	1		T204	39		T183	173
valid_sources[0x06]	35541	1			T183	172		T408	20		T578	23
valid_sources[0x07]	36180	1			T183	174		T408	14		T578	31
valid_sources[0x08]	35549	1			T36	1		T203	2		T183	140
valid_sources[0x09]	35858	1			T9	2		T183	193		T408	14
valid_sources[0x0a]	35610	1			T203	1		T9	1		T183	134
valid_sources[0x0b]	34952	1			T203	1		T183	156		T408	12
valid_sources[0x0c]	35864	1			T183	139		T408	14		T578	21
valid_sources[0x0d]	36101	1			T203	1		T9	2		T183	165
valid_sources[0x0e]	36522	1			T203	1		T183	161		T408	19
valid_sources[0x0f]	35613	1			T183	160		T408	16		T578	23
valid_sources[0x10]	35772	1			T203	5		T183	157		T408	13
valid_sources[0x11]	35357	1			T9	1		T183	167		T408	17
valid_sources[0x12]	35471	1			T36	3		T9	1		T183	107
valid_sources[0x13]	37769	1			T183	177		T408	19		T578	31
valid_sources[0x14]	35407	1			T183	171		T408	16		T578	24
valid_sources[0x15]	35707	1			T36	2		T183	172		T408	14
valid_sources[0x16]	35914	1			T183	152		T408	15		T578	24
valid_sources[0x17]	35367	1			T36	1		T183	195		T408	22
valid_sources[0x18]	35437	1			T203	1		T183	118		T408	7
valid_sources[0x19]	35191	1			T36	2		T203	1		T183	161
valid_sources[0x1a]	36069	1			T183	171		T408	18		T578	28
valid_sources[0x1b]	36565	1			T9	3		T183	158		T408	18
valid_sources[0x1c]	35440	1			T203	1		T9	5		T183	135
valid_sources[0x1d]	36040	1			T36	1		T183	109		T408	12
valid_sources[0x1e]	36159	1			T9	3		T183	132		T408	18
valid_sources[0x1f]	35771	1			T36	1		T183	140		T408	18
valid_sources[0x20]	36287	1			T36	2		T203	2		T183	196

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27112190

1

T4

4084

T5

4452

T6

1611

values[0x0]

all_enables

biggest_size

10469497

1

T4

6248

T5

6356

T6

5232

values[0x1]

all_enables

biggest_size

265883

1

T36

20

T82

16

T83

20

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2958285	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

468537

1

T78

309

T79

23

T80

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1159991	1			T78	784		T79	50		T80	45
values[0x0]	1108730	1			T78	723		T79	64		T80	42
values[0x1]	1158101	1			T78	757		T79	50		T80	42

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2291162	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1135660

1

T78

763

T79

61

T80

33

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54238	1			T78	26		T80	2		T84	123
valid_sources[0x01]	53525	1			T78	45		T79	1		T80	2
valid_sources[0x02]	53607	1			T78	21		T80	2		T84	271
valid_sources[0x03]	53880	1			T78	7		T80	2		T84	84
valid_sources[0x04]	52960	1			T78	25		T79	9		T80	1
valid_sources[0x05]	51302	1			T78	33		T80	1		T84	122
valid_sources[0x06]	53114	1			T78	20		T84	175		T251	46
valid_sources[0x07]	53137	1			T78	43		T80	1		T84	316
valid_sources[0x08]	54189	1			T78	10		T79	7		T80	1
valid_sources[0x09]	53811	1			T78	33		T79	1		T80	3
valid_sources[0x0a]	53377	1			T78	88		T79	4		T80	4
valid_sources[0x0b]	53992	1			T80	5		T84	143		T251	57
valid_sources[0x0c]	53202	1			T78	22		T84	359		T251	38
valid_sources[0x0d]	52439	1			T79	24		T80	3		T84	118
valid_sources[0x0e]	53732	1			T78	69		T79	9		T84	157
valid_sources[0x0f]	53883	1			T78	39		T80	2		T84	236
valid_sources[0x10]	53209	1			T78	75		T80	1		T84	118
valid_sources[0x11]	52999	1			T78	36		T80	2		T84	157
valid_sources[0x12]	53810	1			T78	83		T80	1		T84	205
valid_sources[0x13]	54401	1			T78	31		T79	7		T80	3
valid_sources[0x14]	52888	1			T78	6		T79	1		T80	1
valid_sources[0x15]	53170	1			T78	19		T80	2		T84	135
valid_sources[0x16]	54744	1			T78	44		T80	2		T84	209
valid_sources[0x17]	53229	1			T78	37		T80	1		T84	197
valid_sources[0x18]	54311	1			T78	42		T79	8		T80	3
valid_sources[0x19]	52769	1			T78	54		T84	140		T251	44
valid_sources[0x1a]	53402	1			T78	25		T80	2		T84	198
valid_sources[0x1b]	54201	1			T78	36		T80	3		T84	184
valid_sources[0x1c]	53514	1			T78	72		T79	15		T80	1
valid_sources[0x1d]	53468	1			T78	11		T80	1		T84	178
valid_sources[0x1e]	53985	1			T80	5		T84	165		T251	55
valid_sources[0x1f]	53616	1			T78	105		T80	2		T84	170
valid_sources[0x20]	53337	1			T78	50		T79	2		T84	242

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49252

1

T78

36

T79

1

T84

167

values[0x0]

all_enables

biggest_size

370234

1

T78

243

T79

22

T80

12

values[0x1]

all_enables

biggest_size

49051

1

T78

30

T80

1

T84

125

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3146407	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

512883

1

T78

334

T79

17

T80

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1252294	1			T78	835		T79	52		T80	65
values[0x0]	1155540	1			T78	701		T79	41		T80	39
values[0x1]	1251456	1			T78	777		T79	44		T80	57

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2415196	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1244094

1

T78

815

T79

42

T80

47

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	57402	1			T78	21		T79	5		T84	177
valid_sources[0x01]	57257	1			T78	40		T79	1		T80	5
valid_sources[0x02]	57256	1			T78	28		T79	4		T84	233
valid_sources[0x03]	56851	1			T78	5		T79	3		T84	189
valid_sources[0x04]	58062	1			T78	32		T79	1		T84	220
valid_sources[0x05]	56506	1			T78	32		T79	2		T84	175
valid_sources[0x06]	57078	1			T78	31		T79	3		T84	234
valid_sources[0x07]	56864	1			T78	76		T79	2		T84	259
valid_sources[0x08]	57397	1			T78	10		T79	1		T84	159
valid_sources[0x09]	57441	1			T78	16		T79	4		T84	253
valid_sources[0x0a]	56019	1			T78	76		T79	3		T84	232
valid_sources[0x0b]	57409	1			T79	4		T80	1		T84	233
valid_sources[0x0c]	57195	1			T78	21		T79	1		T80	3
valid_sources[0x0d]	56314	1			T79	2		T80	7		T84	208
valid_sources[0x0e]	57675	1			T78	66		T79	1		T84	199
valid_sources[0x0f]	57466	1			T78	22		T79	2		T80	9
valid_sources[0x10]	57247	1			T78	55		T79	7		T84	165
valid_sources[0x11]	56799	1			T78	37		T79	3		T84	262
valid_sources[0x12]	57201	1			T78	105		T79	1		T80	2
valid_sources[0x13]	58038	1			T78	19		T79	2		T80	28
valid_sources[0x14]	56791	1			T78	8		T79	1		T84	212
valid_sources[0x15]	56599	1			T78	23		T79	2		T80	3
valid_sources[0x16]	57181	1			T78	53		T79	3		T84	194
valid_sources[0x17]	56179	1			T78	25		T79	1		T80	5
valid_sources[0x18]	56268	1			T78	48		T84	194		T251	42
valid_sources[0x19]	56334	1			T78	71		T79	1		T84	190
valid_sources[0x1a]	57591	1			T78	43		T79	5		T80	12
valid_sources[0x1b]	57208	1			T78	40		T79	1		T80	3
valid_sources[0x1c]	56429	1			T78	63		T84	192		T251	43
valid_sources[0x1d]	57080	1			T78	6		T79	2		T84	212
valid_sources[0x1e]	57322	1			T79	2		T84	218		T251	45
valid_sources[0x1f]	58146	1			T78	96		T79	1		T84	202
valid_sources[0x20]	57825	1			T78	42		T80	2		T84	223

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

53936

1

T78

34

T80

2

T84

183

values[0x0]

all_enables

biggest_size

405062

1

T78

278

T79

15

T80

12

values[0x1]

all_enables

biggest_size

53885

1

T78

22

T79

2

T80

4

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2985315	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

473244

1

T78

339

T79

26

T80

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1170631	1			T78	810		T79	63		T80	42
values[0x0]	1117690	1			T78	769		T79	63		T80	47
values[0x1]	1170238	1			T78	818		T79	56		T80	39

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2310014	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1148545

1

T78

811

T79

68

T80

42

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53712	1			T78	17		T79	1		T80	3
valid_sources[0x01]	54107	1			T78	32		T79	1		T84	149
valid_sources[0x02]	53332	1			T78	23		T80	1		T84	198
valid_sources[0x03]	54774	1			T78	7		T84	163		T251	58
valid_sources[0x04]	53930	1			T78	40		T79	11		T80	1
valid_sources[0x05]	53239	1			T78	33		T80	2		T84	174
valid_sources[0x06]	54411	1			T78	24		T80	5		T84	176
valid_sources[0x07]	53868	1			T78	46		T80	5		T84	198
valid_sources[0x08]	54766	1			T78	20		T84	149		T251	46
valid_sources[0x09]	53384	1			T78	21		T79	1		T80	6
valid_sources[0x0a]	53910	1			T78	108		T84	214		T251	48
valid_sources[0x0b]	52937	1			T84	205		T251	56		T389	1
valid_sources[0x0c]	53718	1			T78	23		T79	9		T80	6
valid_sources[0x0d]	53536	1			T80	6		T84	179		T251	43
valid_sources[0x0e]	53844	1			T78	66		T80	6		T84	187
valid_sources[0x0f]	54245	1			T78	23		T79	2		T80	2
valid_sources[0x10]	53475	1			T78	43		T79	5		T80	1
valid_sources[0x11]	53901	1			T78	45		T80	1		T84	231
valid_sources[0x12]	53039	1			T78	95		T84	204		T251	37
valid_sources[0x13]	54319	1			T78	24		T80	4		T84	184
valid_sources[0x14]	55365	1			T78	16		T79	13		T84	220
valid_sources[0x15]	54064	1			T78	41		T84	208		T251	50
valid_sources[0x16]	53390	1			T78	43		T79	18		T80	1
valid_sources[0x17]	53898	1			T78	28		T80	1		T84	191
valid_sources[0x18]	55070	1			T78	64		T79	4		T84	222
valid_sources[0x19]	52839	1			T78	77		T79	3		T80	2
valid_sources[0x1a]	55069	1			T78	42		T84	174		T251	53
valid_sources[0x1b]	53630	1			T78	44		T80	1		T84	193
valid_sources[0x1c]	52686	1			T78	60		T80	4		T84	148
valid_sources[0x1d]	55362	1			T78	10		T79	7		T80	7
valid_sources[0x1e]	53647	1			T80	3		T84	197		T251	54
valid_sources[0x1f]	54578	1			T78	110		T80	3		T84	197
valid_sources[0x20]	53658	1			T78	72		T80	1		T84	153

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49642

1

T78

37

T79

5

T80

1

values[0x0]

all_enables

biggest_size

373827

1

T78

264

T79

19

T80

14

values[0x1]

all_enables

biggest_size

49775

1

T78

38

T79

2

T80

1