Unified Coverage Report :: Module :: prim_alert_sender

Module : prim_alert_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender	75.00			75.00
tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.74	96.47	89.29	99.75		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.51	98.93	83.85	98.84		78.92	92.00	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.97	99.83	100.00	100.00		100.00	90.00	u_rv_plic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.74	96.47	89.29	99.75		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.74	96.47	89.29	99.75		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.74	96.47	89.29	99.75		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T197,T36,T246	Yes	T197,T36,T246	INPUT
alert_req_i	Yes	Yes	T248,T241,T119	Yes	T248,T241,T119	INPUT
alert_ack_o	Yes	Yes	T248,T241,T119	Yes	T248,T241,T119	OUTPUT
alert_state_o	Yes	Yes	T248,T119,T249	Yes	T248,T241,T119	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T197,T85,T86	Yes	T197,T85,T86	INPUT
alert_rx_i.ping_n	Yes	Yes	T85,T86,T444	Yes	T85,T86,T444	INPUT
alert_rx_i.ping_p	Yes	Yes	T85,T86,T444	Yes	T85,T86,T444	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T197,T85,T86	Yes	T197,T85,T86	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender

	Total	Covered	Percent
Totals	12	9	75.00
Total Bits	24	18	75.00
Total Bits 0->1	12	9	75.00
Total Bits 1->0	12	9	75.00

Ports	12	9	75.00
Port Bits	24	18	75.00
Port Bits 0->1	12	9	75.00
Port Bits 1->0	12	9	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T64,T65,T66	Yes	T64,T65,T66	INPUT
alert_req_i	No	No		No		INPUT
alert_ack_o	No	No		No		OUTPUT
alert_state_o	No	No		No		OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T86,T64,T88	Yes	T86,T64,T88	INPUT
alert_rx_i.ping_n	Yes	Yes	T86,T88,T157	Yes	T86,T157,T261	INPUT
alert_rx_i.ping_p	Yes	Yes	T86,T157,T261	Yes	T86,T88,T157	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T86,T64,T88	Yes	T86,T64,T88	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T64,T65,T66	Yes	T64,T65,T66	INPUT
alert_req_i	Yes	Yes	T87	Yes	T87,T90,T91	INPUT
alert_ack_o	Yes	Yes	T87,T90,T91	Yes	T87,T90,T91	OUTPUT
alert_state_o	Yes	Yes	T87	Yes	T87,T90,T91	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
alert_rx_i.ping_n	Yes	Yes	T85,T86,T88	Yes	T85,T86,T88	INPUT
alert_rx_i.ping_p	Yes	Yes	T85,T86,T88	Yes	T85,T86,T88	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T36,T64,T65	Yes	T36,T64,T65	INPUT
alert_req_i	Yes	Yes	T370,T472	Yes	T370,T470,T471	INPUT
alert_ack_o	Yes	Yes	T370,T470,T471	Yes	T370,T470,T471	OUTPUT
alert_state_o	Yes	Yes	T370,T472	Yes	T370,T470,T471	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T86,T370,T36	Yes	T86,T370,T36	INPUT
alert_rx_i.ping_n	Yes	Yes	T86,T444,T88	Yes	T86,T444,T88	INPUT
alert_rx_i.ping_p	Yes	Yes	T86,T444,T88	Yes	T86,T444,T88	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T86,T370,T36	Yes	T86,T370,T36	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T64,T65,T66	Yes	T64,T65,T66	INPUT
alert_req_i	Yes	Yes	T259,T681	Yes	T259,T681	INPUT
alert_ack_o	Yes	Yes	T259,T681	Yes	T259,T681	OUTPUT
alert_state_o	Yes	Yes	T259,T681	Yes	T259,T681	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T85,T86,T259	Yes	T85,T86,T259	INPUT
alert_rx_i.ping_n	Yes	Yes	T85,T86,T88	Yes	T85,T86,T88	INPUT
alert_rx_i.ping_p	Yes	Yes	T85,T86,T88	Yes	T85,T86,T88	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T85,T86,T259	Yes	T85,T86,T259	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T197,T246,T247	Yes	T197,T246,T247	INPUT
alert_req_i	Yes	Yes	T9	Yes	T9	INPUT
alert_ack_o	Yes	Yes	T9	Yes	T9	OUTPUT
alert_state_o	Yes	Yes	T9	Yes	T9	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T197,T86,T246	Yes	T197,T86,T246	INPUT
alert_rx_i.ping_n	Yes	Yes	T86,T260,T88	Yes	T86,T260,T88	INPUT
alert_rx_i.ping_p	Yes	Yes	T86,T260,T88	Yes	T86,T260,T88	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T197,T86,T246	Yes	T197,T86,T246	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_test_i	Yes	Yes	T64,T65,T66	Yes	T64,T65,T66	INPUT
alert_req_i	Yes	Yes	T248,T241,T119	Yes	T248,T241,T119	INPUT
alert_ack_o	Yes	Yes	T248,T241,T119	Yes	T248,T241,T119	OUTPUT
alert_state_o	Yes	Yes	T248,T119,T249	Yes	T248,T241,T119	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i.ack_p	Yes	Yes	T85,T248,T86	Yes	T85,T248,T86	INPUT
alert_rx_i.ping_n	Yes	Yes	T85,T86,T260	Yes	T85,T86,T260	INPUT
alert_rx_i.ping_p	Yes	Yes	T85,T86,T260	Yes	T85,T86,T260	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T85,T248,T86	Yes	T85,T248,T86	OUTPUT