Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : pinmux_jtag_breakout
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_jtag_breakout.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_dft_tap_breakout 100.00 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_dft_tap_breakout

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : pinmux_jtag_breakout
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN1711100.00
CONT_ASSIGN1811100.00
CONT_ASSIGN1911100.00
CONT_ASSIGN2011100.00
CONT_ASSIGN2100
CONT_ASSIGN2200
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_jtag_breakout.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_jtag_breakout.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1
18 1 1
19 1 1
20 1 1
21 unreachable
22 unreachable


Toggle Coverage for Module : pinmux_jtag_breakout
TotalCoveredPercent
Totals 10 10 100.00
Total Bits 20 20 100.00
Total Bits 0->1 10 10 100.00
Total Bits 1->0 10 10 100.00

Ports 10 10 100.00
Port Bits 20 20 100.00
Port Bits 0->1 10 10 100.00
Port Bits 1->0 10 10 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
req_i.tdi Yes Yes T60,T71,T72 Yes T60,T71,T72 INPUT
req_i.trst_n Yes Yes T60,T71,T72 Yes T60,T71,T72 INPUT
req_i.tms Yes Yes T60,T71,T72 Yes T60,T71,T72 INPUT
req_i.tck Yes Yes T60,T71,T72 Yes T60,T71,T72 INPUT
rsp_o.tdo_oe Yes Yes T60,T71,T76 Yes T60,T71,T76 OUTPUT
rsp_o.tdo Yes Yes T60,T71,T76 Yes T60,T71,T76 OUTPUT
tck_o Yes Yes T60,T71,T72 Yes T60,T71,T72 OUTPUT
trst_no Yes Yes T60,T71,T72 Yes T60,T71,T72 OUTPUT
tms_o Yes Yes T60,T71,T72 Yes T60,T71,T72 OUTPUT
tdi_o Yes Yes T60,T71,T72 Yes T60,T71,T72 OUTPUT
tdo_i Unreachable Unreachable Unreachable INPUT
tdo_oe_i Unreachable Unreachable Unreachable INPUT

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%