Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	527493468	61088736	0	0
DepthKnown_A	527493468	527384467	0	0
RvalidKnown_A	527493468	527384467	0	0
WreadyKnown_A	527493468	527384467	0	0
gen_passthru_fifo.paramCheckPass	1024	1024	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	61088736	0	0
T4	207618	18684	0	0
T5	212221	19292	0	0
T6	133219	12592	0	0
T18	126611	17149	0	0
T19	87618	11414	0	0
T20	243050	25160	0	0
T21	346002	9182	0	0
T23	104509	11356	0	0
T48	176011	20355	0	0
T62	41272	0	0	0
T172	0	19894	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	527384467	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	527384467	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	527384467	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1024	1024	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T23	1	1	0	0
T48	1	1	0	0
T62	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	527493468	47038876	0	0
DepthKnown_A	527493468	527384467	0	0
RvalidKnown_A	527493468	527384467	0	0
WreadyKnown_A	527493468	527384467	0	0
gen_passthru_fifo.paramCheckPass	1024	1024	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	47038876	0	0
T4	207618	14923	0	0
T5	212221	15527	0	0
T6	133219	9126	0	0
T18	126611	12016	0	0
T19	87618	8238	0	0
T20	243050	17716	0	0
T21	346002	7306	0	0
T23	104509	8846	0	0
T48	176011	15338	0	0
T62	41272	0	0	0
T172	0	17351	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	527384467	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	527384467	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	527384467	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1024	1024	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T23	1	1	0	0
T48	1	1	0	0
T62	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	527493468	44718115	0	0
DepthKnown_A	527493468	527384467	0	0
RvalidKnown_A	527493468	527384467	0	0
WreadyKnown_A	527493468	527384467	0	0
gen_passthru_fifo.paramCheckPass	1024	1024	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	44718115	0	0
T4	207618	11333	0	0
T5	212221	11815	0	0
T6	133219	7292	0	0
T18	126611	6627	0	0
T19	87618	5245	0	0
T20	243050	13075	0	0
T21	346002	5603	0	0
T23	104509	9056	0	0
T48	176011	11307	0	0
T62	41272	0	0	0
T172	0	6681	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	527384467	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	527384467	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	527384467	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1024	1024	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T23	1	1	0	0
T48	1	1	0	0
T62	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	527493468	37480610	0	0
DepthKnown_A	527493468	527384467	0	0
RvalidKnown_A	527493468	527384467	0	0
WreadyKnown_A	527493468	527384467	0	0
gen_passthru_fifo.paramCheckPass	1024	1024	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	37480610	0	0
T4	207618	11036	0	0
T5	212221	11572	0	0
T6	133219	7062	0	0
T18	126611	6349	0	0
T19	87618	5099	0	0
T20	243050	12631	0	0
T21	346002	5486	0	0
T23	104509	8600	0	0
T48	176011	10957	0	0
T62	41272	0	0	0
T172	0	6503	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	527384467	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	527384467	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	527384467	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1024	1024	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T23	1	1	0	0
T48	1	1	0	0
T62	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	608071069	99421	0	0
DepthKnown_A	608071069	607945868	0	0
RvalidKnown_A	608071069	607945868	0	0
WreadyKnown_A	608071069	607945868	0	0
gen_passthru_fifo.paramCheckPass	2934	2934	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608071069	99421	0	0
T4	207618	27	0	0
T5	212221	28	0	0
T6	133219	27	0	0
T18	126611	26	0	0
T19	87618	16	0	0
T20	243050	64	0	0
T21	346002	15	0	0
T23	104509	208	0	0
T48	176011	74	0	0
T62	41272	0	0	0
T172	0	48	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608071069	607945868	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608071069	607945868	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608071069	607945868	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2934	2934	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T23	1	1	0	0
T48	1	1	0	0
T62	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	608071069	102067	0	0
DepthKnown_A	608071069	607945868	0	0
RvalidKnown_A	608071069	607945868	0	0
WreadyKnown_A	608071069	607945868	0	0
gen_passthru_fifo.paramCheckPass	2934	2934	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608071069	102067	0	0
T4	207618	27	0	0
T5	212221	28	0	0
T6	133219	27	0	0
T18	126611	26	0	0
T19	87618	16	0	0
T20	243050	64	0	0
T21	346002	15	0	0
T23	104509	208	0	0
T48	176011	74	0	0
T62	41272	0	0	0
T172	0	48	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608071069	607945868	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608071069	607945868	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608071069	607945868	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2934	2934	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T23	1	1	0	0
T48	1	1	0	0
T62	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	608071069	52107	0	0
DepthKnown_A	608071069	607945868	0	0
RvalidKnown_A	608071069	607945868	0	0
WreadyKnown_A	608071069	607945868	0	0
gen_passthru_fifo.paramCheckPass	2934	2934	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608071069	52107	0	0
T4	207618	25	0	0
T5	212221	26	0	0
T6	133219	25	0	0
T18	126611	23	0	0
T19	87618	13	0	0
T20	243050	59	0	0
T21	346002	14	0	0
T23	104509	205	0	0
T48	176011	72	0	0
T62	41272	0	0	0
T172	0	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608071069	607945868	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608071069	607945868	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608071069	607945868	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2934	2934	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T23	1	1	0	0
T48	1	1	0	0
T62	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	608071069	52107	0	0
DepthKnown_A	608071069	607945868	0	0
RvalidKnown_A	608071069	607945868	0	0
WreadyKnown_A	608071069	607945868	0	0
gen_passthru_fifo.paramCheckPass	2934	2934	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608071069	52107	0	0
T4	207618	25	0	0
T5	212221	26	0	0
T6	133219	25	0	0
T18	126611	23	0	0
T19	87618	13	0	0
T20	243050	59	0	0
T21	346002	14	0	0
T23	104509	205	0	0
T48	176011	72	0	0
T62	41272	0	0	0
T172	0	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608071069	607945868	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608071069	607945868	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608071069	607945868	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2934	2934	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T23	1	1	0	0
T48	1	1	0	0
T62	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	608071069	47314	0	0
DepthKnown_A	608071069	607945868	0	0
RvalidKnown_A	608071069	607945868	0	0
WreadyKnown_A	608071069	607945868	0	0
gen_passthru_fifo.paramCheckPass	2934	2934	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608071069	47314	0	0
T4	207618	2	0	0
T5	212221	2	0	0
T6	133219	2	0	0
T18	126611	3	0	0
T19	87618	3	0	0
T20	243050	5	0	0
T21	346002	1	0	0
T23	104509	3	0	0
T48	176011	2	0	0
T62	41272	0	0	0
T172	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608071069	607945868	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608071069	607945868	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608071069	607945868	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2934	2934	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T23	1	1	0	0
T48	1	1	0	0
T62	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	608071069	49960	0	0
DepthKnown_A	608071069	607945868	0	0
RvalidKnown_A	608071069	607945868	0	0
WreadyKnown_A	608071069	607945868	0	0
gen_passthru_fifo.paramCheckPass	2934	2934	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608071069	49960	0	0
T4	207618	2	0	0
T5	212221	2	0	0
T6	133219	2	0	0
T18	126611	3	0	0
T19	87618	3	0	0
T20	243050	5	0	0
T21	346002	1	0	0
T23	104509	3	0	0
T48	176011	2	0	0
T62	41272	0	0	0
T172	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608071069	607945868	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608071069	607945868	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	608071069	607945868	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2934	2934	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T23	1	1	0	0
T48	1	1	0	0
T62	1	1	0	0