LINE 18005
EXPRESSION (addr_hit[200] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|---|---|---|---|
| 0 | 1 | 1 | Covered | T18,T19,T20 |
| 1 | 0 | 1 | Covered | T112,T36,T83 |
| 1 | 1 | 0 | Covered | T408,T585,T582 |
| 1 | 1 | 1 | Covered | T112,T253,T36 |
LINE 18008
EXPRESSION (addr_hit[201] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|---|---|---|---|
| 0 | 1 | 1 | Covered | T18,T19,T20 |
| 1 | 0 | 1 | Covered | T36,T83,T408 |
| 1 | 1 | 0 | Covered | T408,T582,T584 |
| 1 | 1 | 1 | Covered | T36,T64,T83 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |