Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_plic_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.98 100.00 99.90 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_plic.u_reg 99.98 100.00 99.90 100.00 100.00

Line Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
TOTAL15601560100.00
ALWAYS6844100.00
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CONT_ASSIGN1659311100.00
CONT_ASSIGN1662711100.00
CONT_ASSIGN1664111100.00
ALWAYS16647203203100.00
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CONT_ASSIGN1940200
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WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 1 1
MISSING_ELSE
77 1 1
89 1 1
90 1 1
118 1 1
119 1 1
16579 1 1
16593 1 1
16627 1 1
16641 1 1
16647 1 1
16648 1 1
16649 1 1
16650 1 1
16651 1 1
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19314 1 1
19315 1 1
19316 1 1
19317 1 1
19318 1 1
19319 1 1
19320 1 1
19321 1 1
19322 1 1
19323 1 1
19324 1 1
19325 1 1
19326 1 1
19327 1 1
19328 1 1
19329 1 1
19330 1 1
19331 1 1
19332 1 1
19333 1 1
19334 1 1
19335 1 1
19336 1 1
19337 1 1
19338 1 1
19339 1 1
19340 1 1
19341 1 1
19342 1 1
19343 1 1
19347 1 1
19348 1 1
19349 1 1
19350 1 1
19351 1 1
19352 1 1
19353 1 1
19354 1 1
19355 1 1
19356 1 1
19357 1 1
19358 1 1
19359 1 1
19360 1 1
19361 1 1
19362 1 1
19363 1 1
19364 1 1
19365 1 1
19366 1 1
19367 1 1
19368 1 1
19369 1 1
19370 1 1
19371 1 1
19372 1 1
19376 1 1
19380 1 1
19384 1 1
19388 1 1
19402 unreachable
19410 1 1
19411 1 1


Cond Coverage for Module : rv_plic_reg_top
TotalCoveredPercent
Conditions2023202199.90
Logical2023202199.90
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
58-1682999.74
16830-16856100.00
16856100.00
16856-17323100.00
17326-1800299.77
18005-18008100.00

Branch Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
Branches 208 208 100.00
TERNARY 16852 2 2 100.00
IF 68 3 3 100.00
CASE 18222 203 203 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 16852 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T18,T19,T20
0 Covered T4,T5,T6


LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T370,T470,T471
0 0 Covered T4,T5,T6


LineNo. Expression -1-: 18222 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T18,T19,T20
addr_hit[1] Covered T221,T222,T153
addr_hit[2] Covered T221,T222,T153
addr_hit[3] Covered T345,T221,T222
addr_hit[4] Covered T345,T221,T222
addr_hit[5] Covered T221,T222,T153
addr_hit[6] Covered T221,T222,T153
addr_hit[7] Covered T221,T222,T153
addr_hit[8] Covered T221,T222,T153
addr_hit[9] Covered T221,T222,T153
addr_hit[10] Covered T216,T217,T218
addr_hit[11] Covered T216,T217,T218
addr_hit[12] Covered T216,T217,T218
addr_hit[13] Covered T216,T217,T218
addr_hit[14] Covered T216,T217,T218
addr_hit[15] Covered T216,T217,T218
addr_hit[16] Covered T216,T217,T218
addr_hit[17] Covered T216,T217,T218
addr_hit[18] Covered T216,T217,T218
addr_hit[19] Covered T146,T147,T153
addr_hit[20] Covered T146,T147,T153
addr_hit[21] Covered T146,T147,T153
addr_hit[22] Covered T146,T147,T153
addr_hit[23] Covered T146,T147,T153
addr_hit[24] Covered T146,T147,T153
addr_hit[25] Covered T146,T147,T153
addr_hit[26] Covered T146,T147,T153
addr_hit[27] Covered T146,T147,T153
addr_hit[28] Covered T29,T30,T31
addr_hit[29] Covered T29,T30,T31
addr_hit[30] Covered T29,T30,T31
addr_hit[31] Covered T29,T30,T31
addr_hit[32] Covered T29,T30,T31
addr_hit[33] Covered T29,T30,T31
addr_hit[34] Covered T29,T30,T31
addr_hit[35] Covered T29,T30,T31
addr_hit[36] Covered T29,T30,T31
addr_hit[37] Covered T153,T253,T36
addr_hit[38] Covered T153,T253,T36
addr_hit[39] Covered T153,T253,T36
addr_hit[40] Covered T153,T253,T36
addr_hit[41] Covered T153,T253,T36
addr_hit[42] Covered T153,T253,T36
addr_hit[43] Covered T153,T253,T36
addr_hit[44] Covered T153,T253,T36
addr_hit[45] Covered T153,T253,T36
addr_hit[46] Covered T153,T253,T36
addr_hit[47] Covered T153,T253,T36
addr_hit[48] Covered T153,T253,T36
addr_hit[49] Covered T153,T253,T36
addr_hit[50] Covered T153,T253,T36
addr_hit[51] Covered T153,T253,T36
addr_hit[52] Covered T153,T253,T36
addr_hit[53] Covered T153,T253,T36
addr_hit[54] Covered T153,T253,T36
addr_hit[55] Covered T153,T253,T36
addr_hit[56] Covered T153,T253,T36
addr_hit[57] Covered T153,T253,T36
addr_hit[58] Covered T153,T253,T36
addr_hit[59] Covered T153,T253,T36
addr_hit[60] Covered T153,T253,T36
addr_hit[61] Covered T153,T253,T36
addr_hit[62] Covered T153,T253,T36
addr_hit[63] Covered T153,T253,T36
addr_hit[64] Covered T153,T253,T36
addr_hit[65] Covered T153,T253,T36
addr_hit[66] Covered T153,T253,T36
addr_hit[67] Covered T153,T253,T36
addr_hit[68] Covered T153,T253,T36
addr_hit[69] Covered T51,T26,T153
addr_hit[70] Covered T51,T153,T253
addr_hit[71] Covered T51,T153,T253
addr_hit[72] Covered T51,T26,T153
addr_hit[73] Covered T51,T26,T153
addr_hit[74] Covered T51,T153,T253
addr_hit[75] Covered T153,T253,T36
addr_hit[76] Covered T153,T253,T36
addr_hit[77] Covered T153,T253,T36
addr_hit[78] Covered T153,T253,T36
addr_hit[79] Covered T153,T253,T36
addr_hit[80] Covered T153,T253,T36
addr_hit[81] Covered T153,T253,T36
addr_hit[82] Covered T153,T253,T36
addr_hit[83] Covered T153,T253,T36
addr_hit[84] Covered T153,T253,T36
addr_hit[85] Covered T153,T253,T36
addr_hit[86] Covered T153,T253,T36
addr_hit[87] Covered T153,T253,T36
addr_hit[88] Covered T153,T253,T36
addr_hit[89] Covered T153,T253,T36
addr_hit[90] Covered T153,T253,T36
addr_hit[91] Covered T153,T253,T36
addr_hit[92] Covered T219,T153,T253
addr_hit[93] Covered T219,T153,T253
addr_hit[94] Covered T153,T253,T36
addr_hit[95] Covered T219,T153,T253
addr_hit[96] Covered T219,T153,T253
addr_hit[97] Covered T219,T153,T253
addr_hit[98] Covered T219,T153,T253
addr_hit[99] Covered T219,T153,T253
addr_hit[100] Covered T153,T253,T36
addr_hit[101] Covered T219,T153,T253
addr_hit[102] Covered T153,T253,T36
addr_hit[103] Covered T153,T253,T36
addr_hit[104] Covered T153,T253,T36
addr_hit[105] Covered T153,T253,T36
addr_hit[106] Covered T153,T253,T36
addr_hit[107] Covered T220,T153,T253
addr_hit[108] Covered T220,T153,T253
addr_hit[109] Covered T153,T253,T36
addr_hit[110] Covered T220,T153,T253
addr_hit[111] Covered T220,T153,T253
addr_hit[112] Covered T220,T153,T253
addr_hit[113] Covered T220,T153,T253
addr_hit[114] Covered T220,T153,T253
addr_hit[115] Covered T153,T253,T36
addr_hit[116] Covered T220,T153,T253
addr_hit[117] Covered T153,T253,T36
addr_hit[118] Covered T153,T253,T36
addr_hit[119] Covered T153,T253,T36
addr_hit[120] Covered T153,T253,T36
addr_hit[121] Covered T153,T253,T36
addr_hit[122] Covered T153,T253,T36
addr_hit[123] Covered T153,T253,T36
addr_hit[124] Covered T153,T253,T36
addr_hit[125] Covered T153,T253,T36
addr_hit[126] Covered T153,T253,T36
addr_hit[127] Covered T68,T69,T70
addr_hit[128] Covered T68,T69,T70
addr_hit[129] Covered T68,T69,T70
addr_hit[130] Covered T68,T69,T70
addr_hit[131] Covered T26,T153,T253
addr_hit[132] Covered T26,T153,T253
addr_hit[133] Covered T153,T253,T36
addr_hit[134] Covered T153,T253,T36
addr_hit[135] Covered T153,T253,T36
addr_hit[136] Covered T153,T253,T36
addr_hit[137] Covered T153,T253,T36
addr_hit[138] Covered T153,T253,T36
addr_hit[139] Covered T153,T253,T36
addr_hit[140] Covered T153,T253,T36
addr_hit[141] Covered T153,T253,T36
addr_hit[142] Covered T153,T253,T36
addr_hit[143] Covered T153,T253,T36
addr_hit[144] Covered T153,T253,T36
addr_hit[145] Covered T153,T253,T36
addr_hit[146] Covered T153,T253,T36
addr_hit[147] Covered T153,T253,T36
addr_hit[148] Covered T153,T253,T36
addr_hit[149] Covered T153,T253,T36
addr_hit[150] Covered T153,T253,T36
addr_hit[151] Covered T153,T253,T36
addr_hit[152] Covered T153,T253,T36
addr_hit[153] Covered T18,T20,T341
addr_hit[154] Covered T153,T253,T36
addr_hit[155] Covered T153,T253,T36
addr_hit[156] Covered T68,T69,T70
addr_hit[157] Covered T68,T69,T70
addr_hit[158] Covered T153,T253,T36
addr_hit[159] Covered T153,T253,T36
addr_hit[160] Covered T335,T352,T354
addr_hit[161] Covered T335,T352,T354
addr_hit[162] Covered T335,T352,T354
addr_hit[163] Covered T335,T352,T354
addr_hit[164] Covered T335,T352,T354
addr_hit[165] Covered T153,T253,T36
addr_hit[166] Covered T19,T105,T153
addr_hit[167] Covered T19,T105,T153
addr_hit[168] Covered T153,T253,T36
addr_hit[169] Covered T153,T253,T36
addr_hit[170] Covered T153,T253,T36
addr_hit[171] Covered T153,T253,T36
addr_hit[172] Covered T117,T149,T150
addr_hit[173] Covered T153,T253,T36
addr_hit[174] Covered T153,T253,T36
addr_hit[175] Covered T153,T253,T36
addr_hit[176] Covered T153,T253,T36
addr_hit[177] Covered T153,T253,T36
addr_hit[178] Covered T153,T253,T36
addr_hit[179] Covered T153,T253,T36
addr_hit[180] Covered T153,T253,T36
addr_hit[181] Covered T153,T253,T36
addr_hit[182] Covered T153,T253,T36
addr_hit[183] Covered T153,T253,T36
addr_hit[184] Covered T153,T253,T36
addr_hit[185] Covered T153,T253,T36
addr_hit[186] Covered T36,T83,T408
addr_hit[187] Covered T36,T83,T408
addr_hit[188] Covered T36,T83,T408
addr_hit[189] Covered T36,T83,T408
addr_hit[190] Covered T351,T36,T83
addr_hit[191] Covered T36,T83,T408
addr_hit[192] Covered T345,T216,T146
addr_hit[193] Covered T29,T30,T31
addr_hit[194] Covered T51,T219,T26
addr_hit[195] Covered T68,T69,T70
addr_hit[196] Covered T18,T20,T68
addr_hit[197] Covered T19,T105,T335
addr_hit[198] Covered T18,T19,T20
addr_hit[199] Covered T18,T19,T20
addr_hit[200] Covered T112,T253,T36
addr_hit[201] Covered T36,T64,T83
default Covered T78,T79,T80


Assert Coverage for Module : rv_plic_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 608071069 223911 0 0
reAfterRv 608071069 223911 0 0
rePulse 608071069 147861 0 0
wePulse 608071069 76050 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 608071069 223911 0 0
T18 126611 8 0 0
T19 87618 11 0 0
T20 243050 6 0 0
T21 346002 0 0 0
T23 104509 0 0 0
T48 176011 0 0 0
T60 784464 0 0 0
T62 41272 0 0 0
T63 194110 0 0 0
T68 0 44 0 0
T69 0 44 0 0
T70 0 44 0 0
T172 158110 0 0 0
T216 0 48 0 0
T341 0 8 0 0
T345 0 11 0 0
T349 0 21 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 608071069 223911 0 0
T18 126611 8 0 0
T19 87618 11 0 0
T20 243050 6 0 0
T21 346002 0 0 0
T23 104509 0 0 0
T48 176011 0 0 0
T60 784464 0 0 0
T62 41272 0 0 0
T63 194110 0 0 0
T68 0 44 0 0
T69 0 44 0 0
T70 0 44 0 0
T172 158110 0 0 0
T216 0 48 0 0
T341 0 8 0 0
T345 0 11 0 0
T349 0 21 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 608071069 147861 0 0
T18 126611 3 0 0
T19 87618 4 0 0
T20 243050 2 0 0
T21 346002 0 0 0
T23 104509 0 0 0
T48 176011 0 0 0
T60 784464 0 0 0
T62 41272 0 0 0
T63 194110 0 0 0
T68 0 14 0 0
T69 0 14 0 0
T70 0 14 0 0
T172 158110 0 0 0
T216 0 19 0 0
T341 0 3 0 0
T345 0 4 0 0
T349 0 8 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 608071069 76050 0 0
T18 126611 5 0 0
T19 87618 7 0 0
T20 243050 4 0 0
T21 346002 0 0 0
T23 104509 0 0 0
T48 176011 0 0 0
T60 784464 0 0 0
T62 41272 0 0 0
T63 194110 0 0 0
T68 0 30 0 0
T69 0 30 0 0
T70 0 30 0 0
T172 158110 0 0 0
T216 0 29 0 0
T341 0 5 0 0
T345 0 7 0 0
T349 0 13 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%