Toggle Coverage for Module :
pattgen
| Total | Covered | Percent |
Totals |
35 |
35 |
100.00 |
Total Bits |
300 |
300 |
100.00 |
Total Bits 0->1 |
150 |
150 |
100.00 |
Total Bits 1->0 |
150 |
150 |
100.00 |
| | | |
Ports |
35 |
35 |
100.00 |
Port Bits |
300 |
300 |
100.00 |
Port Bits 0->1 |
150 |
150 |
100.00 |
Port Bits 1->0 |
150 |
150 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
rst_ni |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T153,T36,T154 |
Yes |
T153,T36,T154 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T153,T36,T154 |
Yes |
T153,T36,T154 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[5:0] |
Yes |
Yes |
*T78,*T79,*T80 |
Yes |
T78,T79,T80 |
INPUT |
tl_i.a_address[16:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[19:17] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[29:20] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[30] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_source[5:0] |
Yes |
Yes |
*T73,*T74,*T81 |
Yes |
T73,T74,T81 |
INPUT |
tl_i.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T78,T79,T80 |
Yes |
T78,T79,T80 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T36,T82,T83 |
Yes |
T36,T82,T83 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T153,T36,T64 |
Yes |
T153,T36,T64 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T153,T36,T64 |
Yes |
T153,T36,T64 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T78,T79,T80 |
Yes |
T78,T79,T80 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T153,T36,T154 |
Yes |
T153,T36,T154 |
OUTPUT |
tl_o.d_user.rsp_intg[6:0] |
Yes |
Yes |
T153,T36,T154 |
Yes |
T153,T36,T64 |
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T153,T36,T154 |
Yes |
T153,T36,T64 |
OUTPUT |
tl_o.d_sink |
Yes |
Yes |
T78,T79,T80 |
Yes |
T78,T79,T80 |
OUTPUT |
tl_o.d_source[5:0] |
Yes |
Yes |
*T36,T78,T79 |
Yes |
T36,T78,T79 |
OUTPUT |
tl_o.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T78,T79,T80 |
Yes |
T78,T79,T80 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T153,*T36,*T154 |
Yes |
T153,T36,T154 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T153,T36,T64 |
Yes |
T153,T36,T64 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T86,T260,T64 |
Yes |
T86,T260,T64 |
INPUT |
alert_rx_i[0].ping_n |
Yes |
Yes |
T86,T260,T88 |
Yes |
T86,T260,T88 |
INPUT |
alert_rx_i[0].ping_p |
Yes |
Yes |
T86,T260,T88 |
Yes |
T86,T260,T88 |
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T86,T260,T64 |
Yes |
T86,T260,T64 |
OUTPUT |
cio_pda0_tx_o |
Yes |
Yes |
T367,T580,T383 |
Yes |
T367,T580,T383 |
OUTPUT |
cio_pcl0_tx_o |
Yes |
Yes |
T36,T367,T580 |
Yes |
T36,T367,T580 |
OUTPUT |
cio_pda1_tx_o |
Yes |
Yes |
T36,T357,T358 |
Yes |
T36,T357,T358 |
OUTPUT |
cio_pcl1_tx_o |
Yes |
Yes |
T36,T357,T358 |
Yes |
T36,T357,T358 |
OUTPUT |
cio_pda0_tx_en_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cio_pcl0_tx_en_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cio_pda1_tx_en_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cio_pcl1_tx_en_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
intr_done_ch0_o |
Yes |
Yes |
T153,T154,T367 |
Yes |
T153,T154,T367 |
OUTPUT |
intr_done_ch1_o |
Yes |
Yes |
T153,T154,T357 |
Yes |
T153,T154,T357 |
OUTPUT |
*Tests covering at least one bit in the range