Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T57,T345,T216	Yes	T57,T345,T216	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T57,T345,T216	Yes	T57,T345,T216	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T73,*T74,*T81	Yes	T73,T74,T81	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T36,T82,T83	Yes	T36,T82,T83	INPUT
tl_i.a_valid	Yes	Yes	T57,T345,T216	Yes	T57,T345,T216	INPUT
tl_o.a_ready	Yes	Yes	T57,T345,T216	Yes	T57,T345,T216	OUTPUT
tl_o.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T57,T216,T58	Yes	T57,T216,T58	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T57,T345,T216	Yes	T57,T345,T216	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T57,T345,T216	Yes	T57,T345,T216	OUTPUT
tl_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T84	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T469,*T718,*T78	Yes	T469,T718,T78	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T57,*T345,*T216	Yes	T57,T345,T216	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T57,T345,T216	Yes	T57,T345,T216	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T368,T85,T86	Yes	T368,T85,T86	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T85,T86,T260	Yes	T85,T86,T260	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T85,T86,T260	Yes	T85,T86,T260	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T368,T85,T86	Yes	T368,T85,T86	OUTPUT
cio_rx_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cio_tx_o	Yes	Yes	T57,T216,T58	Yes	T57,T216,T58	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T216,T146,T217	Yes	T216,T146,T217	OUTPUT
intr_tx_empty_o	Yes	Yes	T216,T146,T217	Yes	T216,T146,T217	OUTPUT
intr_rx_watermark_o	Yes	Yes	T216,T146,T217	Yes	T216,T146,T217	OUTPUT
intr_tx_done_o	Yes	Yes	T345,T216,T146	Yes	T345,T216,T146	OUTPUT
intr_rx_overflow_o	Yes	Yes	T345,T216,T146	Yes	T345,T216,T146	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T330,T332,T337	Yes	T330,T332,T337	OUTPUT
intr_rx_break_err_o	Yes	Yes	T330,T332,T337	Yes	T330,T332,T337	OUTPUT
intr_rx_timeout_o	Yes	Yes	T330,T332,T337	Yes	T330,T332,T337	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T330,T332,T337	Yes	T330,T332,T337	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T57,T345,T58	Yes	T57,T345,T58	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T57,T345,T58	Yes	T57,T345,T58	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T73,*T74,*T81	Yes	T73,T74,T81	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T36,T82,T83	Yes	T36,T82,T83	INPUT
tl_i.a_valid	Yes	Yes	T57,T345,T58	Yes	T57,T345,T58	INPUT
tl_o.a_ready	Yes	Yes	T57,T345,T58	Yes	T57,T345,T58	OUTPUT
tl_o.d_error	Yes	Yes	T78,T79,T84	Yes	T78,T79,T84	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T57,T58,T59	Yes	T57,T58,T59	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T57,T345,T58	Yes	T57,T345,T58	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T57,T345,T58	Yes	T57,T345,T58	OUTPUT
tl_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T84	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T469,*T718,*T78	Yes	T469,T718,T78	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T80,T84	Yes	T78,T80,T84	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T57,*T345,*T58	Yes	T57,T345,T58	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T57,T345,T58	Yes	T57,T345,T58	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T86,T246,T719	Yes	T86,T246,T719	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T86,T260,T88	Yes	T86,T260,T88	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T86,T260,T88	Yes	T86,T260,T88	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T86,T246,T719	Yes	T86,T246,T719	OUTPUT
cio_rx_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
cio_tx_o	Yes	Yes	T57,T58,T59	Yes	T57,T58,T59	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T221,T222,T321	Yes	T221,T222,T321	OUTPUT
intr_tx_empty_o	Yes	Yes	T221,T222,T321	Yes	T221,T222,T321	OUTPUT
intr_rx_watermark_o	Yes	Yes	T221,T222,T321	Yes	T221,T222,T321	OUTPUT
intr_tx_done_o	Yes	Yes	T345,T221,T222	Yes	T345,T221,T222	OUTPUT
intr_rx_overflow_o	Yes	Yes	T345,T221,T222	Yes	T345,T221,T222	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T330,T332,T337	Yes	T330,T332,T337	OUTPUT
intr_rx_break_err_o	Yes	Yes	T330,T332,T337	Yes	T330,T332,T337	OUTPUT
intr_rx_timeout_o	Yes	Yes	T330,T332,T337	Yes	T330,T332,T337	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T330,T332,T337	Yes	T330,T332,T337	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T73,*T74,*T81	Yes	T73,T74,T81	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T36,T82,T83	Yes	T36,T82,T83	INPUT
tl_i.a_valid	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	INPUT
tl_o.a_ready	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
tl_o.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T84	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
tl_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T84,T389	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T78,*T84,*T126	Yes	T78,T79,T80	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T79,T84	Yes	T78,T79,T80	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T216,*T217,*T218	Yes	T216,T217,T218	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T85,T86,T316	Yes	T85,T86,T316	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T85,T86,T88	Yes	T85,T86,T88	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T85,T86,T88	Yes	T85,T86,T88	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T85,T86,T316	Yes	T85,T86,T316	OUTPUT
cio_rx_i	Yes	Yes	T216,T217,T218	Yes	T23,T216,T217	INPUT
cio_tx_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_tx_empty_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_rx_watermark_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_tx_done_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_rx_overflow_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T330,T332,T337	Yes	T330,T332,T337	OUTPUT
intr_rx_break_err_o	Yes	Yes	T330,T332,T337	Yes	T330,T332,T337	OUTPUT
intr_rx_timeout_o	Yes	Yes	T330,T332,T337	Yes	T330,T332,T337	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T330,T332,T337	Yes	T330,T332,T337	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T146,T147,T143	Yes	T146,T147,T143	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T146,T147,T143	Yes	T146,T147,T143	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T73,*T74,*T81	Yes	T73,T74,T81	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T36,T82,T83	Yes	T36,T82,T83	INPUT
tl_i.a_valid	Yes	Yes	T146,T147,T143	Yes	T146,T147,T143	INPUT
tl_o.a_ready	Yes	Yes	T146,T147,T143	Yes	T146,T147,T143	OUTPUT
tl_o.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T84,T126	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T146,T147,T143	Yes	T146,T147,T143	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T146,T147,T143	Yes	T146,T147,T143	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T146,T147,T143	Yes	T146,T147,T143	OUTPUT
tl_o.d_sink	Yes	Yes	T78,T79,T84	Yes	T78,T84,T389	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T78,*T84,*T126	Yes	T78,T79,T80	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T84	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T146,*T147,*T143	Yes	T146,T147,T143	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T146,T147,T143	Yes	T146,T147,T143	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T86,T246,T720	Yes	T86,T246,T720	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T86,T88,T157	Yes	T86,T88,T157	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T86,T88,T157	Yes	T86,T88,T157	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T86,T246,T720	Yes	T86,T246,T720	OUTPUT
cio_rx_i	Yes	Yes	T146,T147,T143	Yes	T146,T147,T143	INPUT
cio_tx_o	Yes	Yes	T146,T147,T143	Yes	T146,T147,T143	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T146,T147,T143	Yes	T146,T147,T143	OUTPUT
intr_tx_empty_o	Yes	Yes	T146,T147,T143	Yes	T146,T147,T143	OUTPUT
intr_rx_watermark_o	Yes	Yes	T146,T147,T143	Yes	T146,T147,T143	OUTPUT
intr_tx_done_o	Yes	Yes	T146,T147,T143	Yes	T146,T147,T143	OUTPUT
intr_rx_overflow_o	Yes	Yes	T146,T147,T143	Yes	T146,T147,T143	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T330,T332,T337	Yes	T330,T332,T337	OUTPUT
intr_rx_break_err_o	Yes	Yes	T330,T332,T337	Yes	T330,T332,T337	OUTPUT
intr_rx_timeout_o	Yes	Yes	T330,T332,T337	Yes	T330,T332,T337	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T330,T332,T337	Yes	T330,T332,T337	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T73,*T74,*T81	Yes	T73,T74,T81	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T36,T82,T83	Yes	T36,T82,T83	INPUT
tl_i.a_valid	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
tl_o.a_ready	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
tl_o.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
tl_o.d_sink	Yes	Yes	T78,T79,T84	Yes	T78,T79,T84	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T78,*T84,*T251	Yes	T78,T79,T80	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T79,T84	Yes	T78,T79,T84	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T29,*T30,*T31	Yes	T29,T30,T31	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T368,T86,T721	Yes	T368,T86,T721	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T86,T88,T157	Yes	T86,T88,T157	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T86,T88,T157	Yes	T86,T88,T157	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T368,T86,T721	Yes	T368,T86,T721	OUTPUT
cio_rx_i	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cio_tx_o	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
intr_tx_empty_o	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
intr_rx_watermark_o	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
intr_tx_done_o	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
intr_rx_overflow_o	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T330,T332,T337	Yes	T330,T332,T337	OUTPUT
intr_rx_break_err_o	Yes	Yes	T330,T332,T337	Yes	T330,T332,T337	OUTPUT
intr_rx_timeout_o	Yes	Yes	T330,T332,T337	Yes	T330,T332,T337	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T330,T332,T337	Yes	T330,T332,T337	OUTPUT

*Tests covering at least one bit in the range