Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_fixed_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_usb_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host0_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host1_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_main_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_fixed_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_usb_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_spi_host0_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_spi_host1_ni	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T80,T84,T251	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T251,T126,T252	Yes	T251,T126,T252	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T69,T73,T223	Yes	T69,T73,T223	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T69,T73,T223	Yes	T69,T73,T223	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T36,T82,T83	Yes	T36,T82,T83	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T36,T82,T83	Yes	T36,T82,T83	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T36,T82,T83	Yes	T36,T82,T83	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T68,T69,T73	Yes	T68,T69,T73	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T73,T74,T81	Yes	T73,T74,T81	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T73,T74,T81	Yes	T73,T74,T81	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T73,T74,T81	Yes	T73,T74,T81	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T73,T74,T71	Yes	T73,T74,T71	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T74,T81,T71	Yes	T74,T81,T71	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T73,T74,T71	Yes	T73,T74,T71	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T73,*T74,*T81	Yes	T73,T74,T81	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T73,T74,T81	Yes	T73,T74,T81	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T9,T78,T79	Yes	T9,T78,T79	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T9,T78,T80	Yes	T9,T78,T80	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T9,T78,T79	Yes	T9,T78,T79	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T9,T78,T79	Yes	T9,T78,T79	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T9,T78,T79	Yes	T9,T78,T79	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T9,T78,*T80	Yes	T9,T78,T80	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T78,T80,T84	Yes	T78,T80,T84	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T78,T80,T84	Yes	T78,T80,T84	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T9,T78,T79	Yes	T9,T78,T79	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T9,T80,T84	Yes	T9,T78,T79	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T78,T84,T126	Yes	T78,T84,T251	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T9,T78,T84	Yes	T9,T78,T84	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T9,T78,T80	Yes	T9,T78,T80	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T9,T78,T80	Yes	T9,T78,T80	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T78,T80,T84	Yes	T78,T84,T126	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T9,T78,T84	Yes	T9,T78,T80	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T78,T80,T84	Yes	T78,T80,T84	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T9,*T78,*T80	Yes	T9,T78,T84	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T9,T78,T79	Yes	T9,T78,T79	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T73,T81,T36	Yes	T73,T81,T36	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T73,T81,T36	Yes	T73,T81,T36	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T73,T81,T36	Yes	T73,T81,T36	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T73,T81,T36	Yes	T73,T81,T36	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T73,T81,T36	Yes	T73,T81,T36	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T73,*T81,*T258	Yes	T73,T81,T258	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T73,T81,T36	Yes	T73,T81,T36	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T73,T81,T258	Yes	T73,T81,T258	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T73,T81,T36	Yes	T73,T81,T36	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T73,*T81,*T258	Yes	T73,T81,T258	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T73,T81,T36	Yes	T73,T81,T36	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T60,T57,T58	Yes	T60,T57,T58	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T57,T58,T59	Yes	T57,T58,T59	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T64,T65,T9	Yes	T64,T65,T9	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T21,T411,T415	Yes	T21,T411,T415	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T21,T411,T415	Yes	T21,T411,T415	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T64,T65,T9	Yes	T64,T65,T9	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T21,T411,T415	Yes	T21,T411,T415	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T9,*T78,*T79	Yes	T9,T78,T79	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T21,T411,T415	Yes	T21,T411,T415	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T21,T411,T415	Yes	T21,T411,T415	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T21,T411,T415	Yes	T21,T411,T415	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T9,T78,T79	Yes	T64,T65,T9	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T21,T411,T415	Yes	T21,T411,T415	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T78,T79,T84	Yes	T78,T79,T80	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T9,T78,*T84	Yes	T9,T78,T79	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T78,T79,T84	Yes	T78,T79,T80	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T21,*T416,*T417	Yes	T21,T411,T415	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T21,T411,T415	Yes	T21,T411,T415	INPUT
tl_peri_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T73,*T74,*T81	Yes	T73,T74,T81	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T36,T82,T83	Yes	T36,T82,T83	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_error	Yes	Yes	T68,T329,T248	Yes	T68,T329,T248	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T73,*T74,*T36	Yes	T73,T74,T81	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T213,T26,T153	Yes	T213,T26,T153	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T213,T26,T153	Yes	T213,T26,T153	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T213,T26,T153	Yes	T213,T26,T153	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T213,T26,T153	Yes	T213,T26,T153	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T213,T26,T153	Yes	T213,T26,T153	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T213,T26,T153	Yes	T213,T26,T153	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T36,*T83,*T78	Yes	T36,T83,T78	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T78,T79,T84	Yes	T78,T79,T84	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T28,T199,T201	Yes	T28,T199,T201	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T213,T26,T153	Yes	T213,T26,T153	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T213,T26,T153	Yes	T213,T26,T153	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T78,T79,T84	Yes	T78,T79,T84	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T213,T26,T153	Yes	T213,T26,T153	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T213,T26,T153	Yes	T213,T26,T153	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T213,T26,T153	Yes	T213,T26,T153	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T78,T79,T84	Yes	T78,T79,T84	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T36,*T83,*T78	Yes	T36,T83,T78	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T78,T79,T84	Yes	T78,T79,T84	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T213,*T26,*T153	Yes	T213,T26,T153	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T213,T26,T153	Yes	T213,T26,T153	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T213,T153,T36	Yes	T213,T153,T36	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T213,T153,T36	Yes	T213,T153,T36	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T213,T153,T36	Yes	T213,T153,T36	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T213,T153,T36	Yes	T213,T153,T36	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T213,T153,T36	Yes	T213,T153,T36	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T213,T153,T36	Yes	T213,T153,T36	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T36,*T83,*T78	Yes	T36,T83,T78	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T78,T80,T84	Yes	T78,T80,T84	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T213,T153,T36	Yes	T213,T153,T36	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T213,T153,T36	Yes	T213,T153,T36	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T78,T79,T84	Yes	T78,T79,T84	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T213,T153,T36	Yes	T213,T153,T36	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T213,T153,T36	Yes	T213,T153,T36	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T213,T153,T36	Yes	T213,T153,T36	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T36,*T83,*T78	Yes	T36,T83,T78	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T84	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T213,*T153,*T36	Yes	T213,T153,T36	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T213,T153,T36	Yes	T213,T153,T36	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T32,T1,T33	Yes	T32,T1,T33	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T32,T1,T33	Yes	T32,T1,T33	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T32,T1,T33	Yes	T32,T1,T33	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T32,T1,T33	Yes	T32,T1,T33	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T32,T1,T33	Yes	T32,T1,T33	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T32,T1,T33	Yes	T32,T1,T33	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T78,T80,T84	Yes	T78,T80,T84	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T32,T1,T33	Yes	T32,T1,T33	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T32,T1,T33	Yes	T32,T1,T33	INPUT
tl_usbdev_i.d_error	Yes	Yes	T78,T79,T84	Yes	T78,T79,T84	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T32,T33,T213	Yes	T32,T33,T213	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T32,T33,T213	Yes	T32,T33,T213	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T32,T1,T33	Yes	T32,T1,T33	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T78,T80,T84	Yes	T78,T79,T80	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T78,*T84,*T251	Yes	T78,T80,T84	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T78,T80,T84	Yes	T78,T79,T80	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T32,*T1,*T33	Yes	T32,T1,T33	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T32,T1,T33	Yes	T32,T1,T33	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T83,*T78,*T79	Yes	T83,T78,T79	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T78,T79,T84	Yes	T78,T79,T84	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T78,T79,T84	Yes	T78,T79,T84	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T83,*T78,*T84	Yes	T83,T78,T79	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T83,T78,T79	Yes	T83,T78,T79	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T83,T78,T79	Yes	T83,T78,T79	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T83,T78,T79	Yes	T83,T78,T79	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T83,T78,T79	Yes	T83,T78,T79	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T83,T78,T79	Yes	T83,T78,T79	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T83,T78,T79	Yes	T83,T78,T79	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T78,T80,T84	Yes	T78,T80,T84	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T83,T78,T79	Yes	T83,T78,T79	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T83,T80,T84	Yes	T83,T78,T79	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T78,T79,T84	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T83,T78,T79	Yes	T83,T78,T79	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T83,T78,T79	Yes	T83,T78,T79	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T83,T78,T79	Yes	T83,T78,T79	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T83,T78,T84	Yes	T83,T78,T79	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T83,*T78,*T79	Yes	T83,T78,T79	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T83,T78,T79	Yes	T83,T78,T79	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T5,T6,T18	Yes	T5,T6,T18	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_hmac_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T19,T57,T58	Yes	T19,T57,T58	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T19,T57,T58	Yes	T19,T57,T58	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T19,T57,T58	Yes	T19,T57,T58	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T19,T57,T58	Yes	T19,T57,T58	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T19,T57,T58	Yes	T19,T57,T58	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T83,*T78,*T79	Yes	T83,T78,T79	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T78,T80,T84	Yes	T78,T80,T84	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T19,T105,T304	Yes	T19,T105,T304	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T19,T57,T58	Yes	T19,T57,T58	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T19,T57,T58	Yes	T19,T57,T58	INPUT
tl_hmac_i.d_error	Yes	Yes	T78,T84,T251	Yes	T78,T84,T251	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T19,T57,T58	Yes	T19,T57,T58	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T19,T57,T58	Yes	T19,T57,T58	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T19,T57,T58	Yes	T19,T57,T58	INPUT
tl_hmac_i.d_sink	Yes	Yes	T78,T79,T84	Yes	T78,T79,T84	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T83,*T78,*T84	Yes	T83,T78,T79	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T78,T80,T84	Yes	T78,T80,T84	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T19,*T57,*T58	Yes	T19,T57,T58	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T19,T57,T58	Yes	T19,T57,T58	INPUT
tl_kmac_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T116,T111,T224	Yes	T116,T111,T224	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T68,T69,T116	Yes	T68,T69,T116	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T68,T69,T116	Yes	T68,T69,T116	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T116,T111,T224	Yes	T116,T111,T224	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T68,T69,T116	Yes	T68,T69,T116	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T36,*T83,*T78	Yes	T36,T83,T78	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T111,T479,T298	Yes	T111,T479,T298	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T68,T69,T116	Yes	T68,T69,T116	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T68,T69,T116	Yes	T68,T69,T116	INPUT
tl_kmac_i.d_error	Yes	Yes	T78,T80,T84	Yes	T78,T80,T84	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T116,T111,T480	Yes	T68,T69,T116	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T68,T69,T116	Yes	T68,T69,T116	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T68,T69,T116	Yes	T68,T69,T111	INPUT
tl_kmac_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T80,T84	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T36,*T83,*T78	Yes	T36,T83,T78	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T80,T84	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T116,*T111,*T480	Yes	T111,T479,T298	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T68,T69,T116	Yes	T68,T69,T116	INPUT
tl_aes_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T296,T700,T123	Yes	T296,T700,T123	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T296,T700,T123	Yes	T296,T700,T123	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T125,T108,T306	Yes	T125,T108,T306	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T296,T700,T123	Yes	T296,T700,T123	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T125,T108,T306	Yes	T125,T108,T306	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T125,T108,T306	Yes	T125,T108,T306	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T125,T108,T306	Yes	T125,T108,T306	INPUT
tl_aes_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T125,T108,T306	Yes	T125,T108,T306	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T125,T108,T113	Yes	T125,T108,T113	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T125,T108,T306	Yes	T125,T108,T306	INPUT
tl_aes_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T78,*T84,*T251	Yes	T78,T79,T80	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T125,*T108,*T306	Yes	T125,T108,T306	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T125,T108,T306	Yes	T125,T108,T306	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T83,*T78,*T79	Yes	T83,T78,T79	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T78,T79,T84	Yes	T78,T79,T84	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T125,T116,T108	Yes	T125,T116,T108	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T83,*T78,*T84	Yes	T83,T78,T79	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T125,*T116,*T108	Yes	T57,T125,T58	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T125,T116,T108	Yes	T125,T116,T108	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T83,*T78,*T79	Yes	T83,T78,T79	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T78,T79,T84	Yes	T78,T79,T84	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T78,T79,T84	Yes	T78,T79,T84	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_error	Yes	Yes	T78,T79,T84	Yes	T78,T79,T80	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T125,T116,T108	Yes	T125,T116,T108	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_sink	Yes	Yes	T78,T79,T84	Yes	T78,T79,T84	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T83,*T78,*T84	Yes	T83,T78,T79	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T78,T79,T84	Yes	T78,T79,T84	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T125,*T116,*T108	Yes	T125,T116,T108	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T125,T116,T108	Yes	T125,T116,T108	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T125,T116,T108	Yes	T125,T116,T108	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T83,*T78,*T79	Yes	T83,T78,T79	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T80,T84	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T125,T116,T108	Yes	T125,T116,T108	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T83,*T78,*T80	Yes	T83,T78,T79	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T125,*T116,*T108	Yes	T125,T116,T108	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn1_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T125,T116,T108	Yes	T125,T116,T108	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T125,T116,T108	Yes	T125,T116,T108	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T125,T116,T108	Yes	T125,T116,T108	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T125,T116,T108	Yes	T125,T116,T108	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T125,T116,T108	Yes	T125,T116,T108	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T83,*T78,*T79	Yes	T83,T78,T79	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T125,T116,T108	Yes	T125,T116,T108	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T125,T116,T108	Yes	T125,T116,T108	INPUT
tl_edn1_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T125,T116,T108	Yes	T125,T116,T108	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T125,T116,T108	Yes	T125,T116,T108	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T125,T116,T108	Yes	T125,T116,T108	INPUT
tl_edn1_i.d_sink	Yes	Yes	T78,T79,T84	Yes	T78,T79,T80	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T83,*T78,*T79	Yes	T83,T78,T79	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T125,*T116,*T108	Yes	T125,T116,T108	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T125,T116,T108	Yes	T125,T116,T108	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T36,*T83,*T78	Yes	T36,T83,T78	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T18,T20,T68	Yes	T18,T20,T68	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T78,T79,T84	Yes	T78,T79,T80	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T36,*T83,*T78	Yes	T36,T83,T78	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T18,*T19,*T20	Yes	T18,T19,T20	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
tl_otbn_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T57,T125,T58	Yes	T57,T125,T58	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T57,T125,T58	Yes	T57,T125,T58	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T57,T125,T58	Yes	T57,T125,T58	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T57,T125,T58	Yes	T57,T125,T58	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T57,T125,T58	Yes	T57,T125,T58	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T36,*T82,*T203	Yes	T36,T82,T203	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T57,T125,T58	Yes	T57,T125,T58	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T57,T125,T58	Yes	T57,T125,T58	INPUT
tl_otbn_i.d_error	Yes	Yes	T78,T79,T84	Yes	T78,T79,T84	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T57,T125,T58	Yes	T57,T125,T58	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T57,T125,T58	Yes	T57,T125,T58	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T57,T125,T58	Yes	T57,T125,T58	INPUT
tl_otbn_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T36,*T82,*T203	Yes	T36,T82,T203	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T57,*T125,*T58	Yes	T57,T125,T58	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T57,T125,T58	Yes	T57,T125,T58	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T57,T58,T59	Yes	T57,T58,T59	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T57,T58,T59	Yes	T57,T58,T59	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T57,T58,T59	Yes	T57,T58,T59	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T57,T197,T116	Yes	T57,T197,T116	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T57,T58,T59	Yes	T57,T58,T59	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T83,*T78,*T79	Yes	T83,T78,T79	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T78,T79,T84	Yes	T78,T79,T84	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T57,T58,T59	Yes	T57,T58,T59	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T57,T58,T59	Yes	T57,T58,T59	INPUT
tl_keymgr_i.d_error	Yes	Yes	T78,T79,T84	Yes	T78,T79,T80	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T58,T59,T197	Yes	T58,T59,T197	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T57,T58,T59	Yes	T57,T58,T59	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T57,T58,T59	Yes	T57,T58,T59	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T78,T79,T84	Yes	T78,T79,T80	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T83,*T78,*T84	Yes	T83,T78,T79	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T78,T79,T84	Yes	T78,T80,T84	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T57,*T58,*T59	Yes	T57,T58,T59	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T57,T58,T59	Yes	T57,T58,T59	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T9,*T78,*T79	Yes	T9,T78,T79	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T78,T80,T84	Yes	T78,T80,T84	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T78,T80,T84	Yes	T78,T80,T84	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T9,T78,T80	Yes	T9,T78,T80	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T78,T80,T84	Yes	T78,T80,T84	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T9,*T78,*T80	Yes	T9,T78,T80	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T78,T80,T84	Yes	T78,T80,T84	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T57,T58,T59	Yes	T57,T58,T59	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T57,T58,T59	Yes	T57,T58,T59	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T57,T58,T59	Yes	T57,T58,T59	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T57,T58,T59	Yes	T57,T58,T59	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T57,T58,T59	Yes	T57,T58,T59	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T81,*T36,*T83	Yes	T81,T36,T83	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T78,T79,T84	Yes	T78,T79,T84	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T57,T58,T59	Yes	T57,T58,T59	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T57,T58,T59	Yes	T57,T58,T59	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T36,T175,T83	Yes	T36,T175,T83	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T119,T54,T55	Yes	T57,T58,T59	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T119,T54,T55	Yes	T57,T58,T59	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T36,*T83,*T78	Yes	T81,T36,T83	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T78,T79,T84	Yes	T78,T79,T84	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T119,*T36,*T175	Yes	T119,T467,T36	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T57,T58,T59	Yes	T57,T58,T59	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range