Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T177,T178,T309
0	1	Covered	T177,T178,T309
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T177,T178,T309
1	Covered	T177,T178,T309

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T177,T178,T309
1	Covered	T177,T178,T309

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T177,T178,T309
1	1	Covered	T177,T178,T309

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T177,T178,T309
1	0	Covered	T177,T178,T309
1	1	Covered	T177,T178,T309

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T177,T178,T309

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T177,T178,T309
0	Covered	T177,T178,T309

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T177,T178,T309
0	Covered	T177,T178,T309

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1054986936	1035725978	0	0
CheckNGreaterZero_A	2048	2048	0	0
GntImpliesReady_A	1054986936	8375	0	0
GntImpliesValid_A	1054986936	8375	0	0
GrantKnown_A	1054986936	1035725978	0	0
IdxKnown_A	1054986936	1035725978	0	0
IndexIsCorrect_A	1054986936	8375	0	0
NoReadyValidNoGrant_A	1054986936	0	0	0
Priority_A	1054986936	8375	0	0
ReadyAndValidImplyGrant_A	1054986936	8375	0	0
ReqAndReadyImplyGrant_A	1054986936	8375	0	0
ReqImpliesValid_A	1054986936	8375	0	0
ValidKnown_A	1054986936	1035725978	0	0
gen_data_port_assertion.DataFlow_A	1054986936	8375	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1054986936	1035725978	0	0
T4	415236	414868	0	0
T5	424442	424094	0	0
T6	266438	265412	0	0
T18	253222	253120	0	0
T19	175236	175126	0	0
T20	486100	485766	0	0
T21	692004	691764	0	0
T23	209018	208908	0	0
T48	352022	351806	0	0
T62	82544	82434	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2048	2048	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T18	2	2	0	0
T19	2	2	0	0
T20	2	2	0	0
T21	2	2	0	0
T23	2	2	0	0
T48	2	2	0	0
T62	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1054986936	8375	0	0
T129	355846	0	0	0
T157	306028	0	0	0
T177	191622	2785	0	0
T178	0	2798	0	0
T299	289958	0	0	0
T309	0	2792	0	0
T399	146282	0	0	0
T400	363068	0	0	0
T401	564326	0	0	0
T402	174052	0	0	0
T403	304366	0	0	0
T404	127306	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1054986936	8375	0	0
T129	355846	0	0	0
T157	306028	0	0	0
T177	191622	2785	0	0
T178	0	2798	0	0
T299	289958	0	0	0
T309	0	2792	0	0
T399	146282	0	0	0
T400	363068	0	0	0
T401	564326	0	0	0
T402	174052	0	0	0
T403	304366	0	0	0
T404	127306	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1054986936	1035725978	0	0
T4	415236	414868	0	0
T5	424442	424094	0	0
T6	266438	265412	0	0
T18	253222	253120	0	0
T19	175236	175126	0	0
T20	486100	485766	0	0
T21	692004	691764	0	0
T23	209018	208908	0	0
T48	352022	351806	0	0
T62	82544	82434	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1054986936	1035725978	0	0
T4	415236	414868	0	0
T5	424442	424094	0	0
T6	266438	265412	0	0
T18	253222	253120	0	0
T19	175236	175126	0	0
T20	486100	485766	0	0
T21	692004	691764	0	0
T23	209018	208908	0	0
T48	352022	351806	0	0
T62	82544	82434	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1054986936	8375	0	0
T129	355846	0	0	0
T157	306028	0	0	0
T177	191622	2785	0	0
T178	0	2798	0	0
T299	289958	0	0	0
T309	0	2792	0	0
T399	146282	0	0	0
T400	363068	0	0	0
T401	564326	0	0	0
T402	174052	0	0	0
T403	304366	0	0	0
T404	127306	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1054986936	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1054986936	8375	0	0
T129	355846	0	0	0
T157	306028	0	0	0
T177	191622	2785	0	0
T178	0	2798	0	0
T299	289958	0	0	0
T309	0	2792	0	0
T399	146282	0	0	0
T400	363068	0	0	0
T401	564326	0	0	0
T402	174052	0	0	0
T403	304366	0	0	0
T404	127306	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1054986936	8375	0	0
T129	355846	0	0	0
T157	306028	0	0	0
T177	191622	2785	0	0
T178	0	2798	0	0
T299	289958	0	0	0
T309	0	2792	0	0
T399	146282	0	0	0
T400	363068	0	0	0
T401	564326	0	0	0
T402	174052	0	0	0
T403	304366	0	0	0
T404	127306	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1054986936	8375	0	0
T129	355846	0	0	0
T157	306028	0	0	0
T177	191622	2785	0	0
T178	0	2798	0	0
T299	289958	0	0	0
T309	0	2792	0	0
T399	146282	0	0	0
T400	363068	0	0	0
T401	564326	0	0	0
T402	174052	0	0	0
T403	304366	0	0	0
T404	127306	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1054986936	8375	0	0
T129	355846	0	0	0
T157	306028	0	0	0
T177	191622	2785	0	0
T178	0	2798	0	0
T299	289958	0	0	0
T309	0	2792	0	0
T399	146282	0	0	0
T400	363068	0	0	0
T401	564326	0	0	0
T402	174052	0	0	0
T403	304366	0	0	0
T404	127306	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1054986936	1035725978	0	0
T4	415236	414868	0	0
T5	424442	424094	0	0
T6	266438	265412	0	0
T18	253222	253120	0	0
T19	175236	175126	0	0
T20	486100	485766	0	0
T21	692004	691764	0	0
T23	209018	208908	0	0
T48	352022	351806	0	0
T62	82544	82434	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1054986936	8375	0	0
T129	355846	0	0	0
T157	306028	0	0	0
T177	191622	2785	0	0
T178	0	2798	0	0
T299	289958	0	0	0
T309	0	2792	0	0
T399	146282	0	0	0
T400	363068	0	0	0
T401	564326	0	0	0
T402	174052	0	0	0
T403	304366	0	0	0
T404	127306	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T177,T178,T309
0	1	Covered	T177,T178,T309
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T177,T178,T309
1	Covered	T177,T178,T309

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T177,T178,T309
1	Covered	T177,T178,T309

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T177,T178,T309
1	1	Covered	T177,T178,T309

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T177,T178,T309
1	0	Covered	T177,T178,T309
1	1	Covered	T177,T178,T309

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T177,T178,T309

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T177,T178,T309
0	Covered	T177,T178,T309

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T177,T178,T309
0	Covered	T177,T178,T309

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	527493468	517862989	0	0
CheckNGreaterZero_A	1024	1024	0	0
GntImpliesReady_A	527493468	5184	0	0
GntImpliesValid_A	527493468	5184	0	0
GrantKnown_A	527493468	517862989	0	0
IdxKnown_A	527493468	517862989	0	0
IndexIsCorrect_A	527493468	5184	0	0
NoReadyValidNoGrant_A	527493468	0	0	0
Priority_A	527493468	5184	0	0
ReadyAndValidImplyGrant_A	527493468	5184	0	0
ReqAndReadyImplyGrant_A	527493468	5184	0	0
ReqImpliesValid_A	527493468	5184	0	0
ValidKnown_A	527493468	517862989	0	0
gen_data_port_assertion.DataFlow_A	527493468	5184	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	517862989	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1024	1024	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T23	1	1	0	0
T48	1	1	0	0
T62	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	5184	0	0
T129	177923	0	0	0
T157	153014	0	0	0
T177	95811	1722	0	0
T178	0	1734	0	0
T299	144979	0	0	0
T309	0	1728	0	0
T399	73141	0	0	0
T400	181534	0	0	0
T401	282163	0	0	0
T402	87026	0	0	0
T403	152183	0	0	0
T404	63653	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	5184	0	0
T129	177923	0	0	0
T157	153014	0	0	0
T177	95811	1722	0	0
T178	0	1734	0	0
T299	144979	0	0	0
T309	0	1728	0	0
T399	73141	0	0	0
T400	181534	0	0	0
T401	282163	0	0	0
T402	87026	0	0	0
T403	152183	0	0	0
T404	63653	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	517862989	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	517862989	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	5184	0	0
T129	177923	0	0	0
T157	153014	0	0	0
T177	95811	1722	0	0
T178	0	1734	0	0
T299	144979	0	0	0
T309	0	1728	0	0
T399	73141	0	0	0
T400	181534	0	0	0
T401	282163	0	0	0
T402	87026	0	0	0
T403	152183	0	0	0
T404	63653	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	5184	0	0
T129	177923	0	0	0
T157	153014	0	0	0
T177	95811	1722	0	0
T178	0	1734	0	0
T299	144979	0	0	0
T309	0	1728	0	0
T399	73141	0	0	0
T400	181534	0	0	0
T401	282163	0	0	0
T402	87026	0	0	0
T403	152183	0	0	0
T404	63653	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	5184	0	0
T129	177923	0	0	0
T157	153014	0	0	0
T177	95811	1722	0	0
T178	0	1734	0	0
T299	144979	0	0	0
T309	0	1728	0	0
T399	73141	0	0	0
T400	181534	0	0	0
T401	282163	0	0	0
T402	87026	0	0	0
T403	152183	0	0	0
T404	63653	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	5184	0	0
T129	177923	0	0	0
T157	153014	0	0	0
T177	95811	1722	0	0
T178	0	1734	0	0
T299	144979	0	0	0
T309	0	1728	0	0
T399	73141	0	0	0
T400	181534	0	0	0
T401	282163	0	0	0
T402	87026	0	0	0
T403	152183	0	0	0
T404	63653	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	5184	0	0
T129	177923	0	0	0
T157	153014	0	0	0
T177	95811	1722	0	0
T178	0	1734	0	0
T299	144979	0	0	0
T309	0	1728	0	0
T399	73141	0	0	0
T400	181534	0	0	0
T401	282163	0	0	0
T402	87026	0	0	0
T403	152183	0	0	0
T404	63653	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	517862989	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	5184	0	0
T129	177923	0	0	0
T157	153014	0	0	0
T177	95811	1722	0	0
T178	0	1734	0	0
T299	144979	0	0	0
T309	0	1728	0	0
T399	73141	0	0	0
T400	181534	0	0	0
T401	282163	0	0	0
T402	87026	0	0	0
T403	152183	0	0	0
T404	63653	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T177,T178,T309
0	1	Covered	T177,T178,T309
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T177,T178,T309
1	Covered	T177,T178,T309

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T177,T178,T309
1	Covered	T177,T178,T309

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T177,T178,T309
1	1	Covered	T177,T178,T309

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T177,T178,T309
1	0	Covered	T177,T178,T309
1	1	Covered	T177,T178,T309

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T177,T178,T309

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T177,T178,T309
0	Covered	T177,T178,T309

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T177,T178,T309
0	Covered	T177,T178,T309

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	527493468	517862989	0	0
CheckNGreaterZero_A	1024	1024	0	0
GntImpliesReady_A	527493468	3191	0	0
GntImpliesValid_A	527493468	3191	0	0
GrantKnown_A	527493468	517862989	0	0
IdxKnown_A	527493468	517862989	0	0
IndexIsCorrect_A	527493468	3191	0	0
NoReadyValidNoGrant_A	527493468	0	0	0
Priority_A	527493468	3191	0	0
ReadyAndValidImplyGrant_A	527493468	3191	0	0
ReqAndReadyImplyGrant_A	527493468	3191	0	0
ReqImpliesValid_A	527493468	3191	0	0
ValidKnown_A	527493468	517862989	0	0
gen_data_port_assertion.DataFlow_A	527493468	3191	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	517862989	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1024	1024	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T23	1	1	0	0
T48	1	1	0	0
T62	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	3191	0	0
T129	177923	0	0	0
T157	153014	0	0	0
T177	95811	1063	0	0
T178	0	1064	0	0
T299	144979	0	0	0
T309	0	1064	0	0
T399	73141	0	0	0
T400	181534	0	0	0
T401	282163	0	0	0
T402	87026	0	0	0
T403	152183	0	0	0
T404	63653	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	3191	0	0
T129	177923	0	0	0
T157	153014	0	0	0
T177	95811	1063	0	0
T178	0	1064	0	0
T299	144979	0	0	0
T309	0	1064	0	0
T399	73141	0	0	0
T400	181534	0	0	0
T401	282163	0	0	0
T402	87026	0	0	0
T403	152183	0	0	0
T404	63653	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	517862989	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	517862989	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	3191	0	0
T129	177923	0	0	0
T157	153014	0	0	0
T177	95811	1063	0	0
T178	0	1064	0	0
T299	144979	0	0	0
T309	0	1064	0	0
T399	73141	0	0	0
T400	181534	0	0	0
T401	282163	0	0	0
T402	87026	0	0	0
T403	152183	0	0	0
T404	63653	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	3191	0	0
T129	177923	0	0	0
T157	153014	0	0	0
T177	95811	1063	0	0
T178	0	1064	0	0
T299	144979	0	0	0
T309	0	1064	0	0
T399	73141	0	0	0
T400	181534	0	0	0
T401	282163	0	0	0
T402	87026	0	0	0
T403	152183	0	0	0
T404	63653	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	3191	0	0
T129	177923	0	0	0
T157	153014	0	0	0
T177	95811	1063	0	0
T178	0	1064	0	0
T299	144979	0	0	0
T309	0	1064	0	0
T399	73141	0	0	0
T400	181534	0	0	0
T401	282163	0	0	0
T402	87026	0	0	0
T403	152183	0	0	0
T404	63653	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	3191	0	0
T129	177923	0	0	0
T157	153014	0	0	0
T177	95811	1063	0	0
T178	0	1064	0	0
T299	144979	0	0	0
T309	0	1064	0	0
T399	73141	0	0	0
T400	181534	0	0	0
T401	282163	0	0	0
T402	87026	0	0	0
T403	152183	0	0	0
T404	63653	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	3191	0	0
T129	177923	0	0	0
T157	153014	0	0	0
T177	95811	1063	0	0
T178	0	1064	0	0
T299	144979	0	0	0
T309	0	1064	0	0
T399	73141	0	0	0
T400	181534	0	0	0
T401	282163	0	0	0
T402	87026	0	0	0
T403	152183	0	0	0
T404	63653	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	517862989	0	0
T4	207618	207434	0	0
T5	212221	212047	0	0
T6	133219	132706	0	0
T18	126611	126560	0	0
T19	87618	87563	0	0
T20	243050	242883	0	0
T21	346002	345882	0	0
T23	104509	104454	0	0
T48	176011	175903	0	0
T62	41272	41217	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527493468	3191	0	0
T129	177923	0	0	0
T157	153014	0	0	0
T177	95811	1063	0	0
T178	0	1064	0	0
T299	144979	0	0	0
T309	0	1064	0	0
T399	73141	0	0	0
T400	181534	0	0	0
T401	282163	0	0	0
T402	87026	0	0	0
T403	152183	0	0	0
T404	63653	0	0	0