SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
93.33 | 100.00 | 80.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex.u_rsp_chk | 93.33 | 100.00 | 80.00 | 100.00 | |||
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex.u_rsp_chk | 93.33 | 100.00 | 80.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
93.33 | 100.00 | 80.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
93.33 | 100.00 | 80.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
87.26 | 90.91 | 69.23 | 88.89 | 100.00 | tl_adapter_host_i_ibex |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
93.33 | 100.00 | 80.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
93.33 | 100.00 | 80.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
90.91 | 91.30 | 82.35 | 90.00 | 100.00 | tl_adapter_host_d_ibex |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 23 | 1 | 1 | 100.00 |
CONT_ASSIGN | 47 | 1 | 1 | 100.00 |
CONT_ASSIGN | 50 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
23 | 1 | 1 | |
47 | 1 | 1 | |
50 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 5 | 4 | 80.00 |
Logical | 5 | 4 | 80.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 47 EXPRESSION (tl_i.d_valid & (((|rsp_err)) | rsp_data_err)) ------1----- --------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Not Covered |
LINE 47 SUB-EXPRESSION (((|rsp_err)) | rsp_data_err) ------1----- ------2-----
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T5,T6 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
PayLoadWidthCheck | 2048 | 2048 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2048 | 2048 | 0 | 0 |
T4 | 2 | 2 | 0 | 0 |
T5 | 2 | 2 | 0 | 0 |
T6 | 2 | 2 | 0 | 0 |
T18 | 2 | 2 | 0 | 0 |
T19 | 2 | 2 | 0 | 0 |
T20 | 2 | 2 | 0 | 0 |
T21 | 2 | 2 | 0 | 0 |
T23 | 2 | 2 | 0 | 0 |
T48 | 2 | 2 | 0 | 0 |
T62 | 2 | 2 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 23 | 1 | 1 | 100.00 |
CONT_ASSIGN | 47 | 1 | 1 | 100.00 |
CONT_ASSIGN | 50 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
23 | 1 | 1 | |
47 | 1 | 1 | |
50 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 5 | 4 | 80.00 |
Logical | 5 | 4 | 80.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 47 EXPRESSION (tl_i.d_valid & (((|rsp_err)) | rsp_data_err)) ------1----- --------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Not Covered |
LINE 47 SUB-EXPRESSION (((|rsp_err)) | rsp_data_err) ------1----- ------2-----
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T5,T6 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
PayLoadWidthCheck | 1024 | 1024 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1024 | 1024 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T23 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
T62 | 1 | 1 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 23 | 1 | 1 | 100.00 |
CONT_ASSIGN | 47 | 1 | 1 | 100.00 |
CONT_ASSIGN | 50 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
23 | 1 | 1 | |
47 | 1 | 1 | |
50 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 5 | 4 | 80.00 |
Logical | 5 | 4 | 80.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 47 EXPRESSION (tl_i.d_valid & (((|rsp_err)) | rsp_data_err)) ------1----- --------------2--------------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Not Covered |
LINE 47 SUB-EXPRESSION (((|rsp_err)) | rsp_data_err) ------1----- ------2-----
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T5,T6 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 1 | 1 | 100.00 | 1 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
PayLoadWidthCheck | 1024 | 1024 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1024 | 1024 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T23 | 1 | 1 | 0 | 0 |
T48 | 1 | 1 | 0 | 0 |
T62 | 1 | 1 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |