Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2068060	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

38807297

1

T4

106444

T5

12614

T6

17596

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	28538284	1			T4	102877		T5	5286		T6	8836
values[0x0]	10831605	1			T4	3567		T5	7328		T6	8760
values[0x1]	1505468	1			T4	3172		T5	857		T6	752

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	705110	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

40170247

1

T4

109616

T5

13471

T6

18348

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19119197	1			T4	54808		T5	6736		T6	9174
valid_sources[0x01]	19117687	1			T4	54808		T5	6735		T6	9174
valid_sources[0x02]	42136	1			T153	707		T403	664		T576	26
valid_sources[0x03]	41779	1			T153	750		T403	696		T576	25
valid_sources[0x04]	42436	1			T88	1		T153	837		T403	710
valid_sources[0x05]	42215	1			T153	777		T403	578		T576	21
valid_sources[0x06]	42248	1			T87	3		T153	835		T403	639
valid_sources[0x07]	42203	1			T153	816		T403	719		T576	26
valid_sources[0x08]	42688	1			T88	1		T206	8		T153	813
valid_sources[0x09]	41901	1			T88	2		T153	700		T403	703
valid_sources[0x0a]	42082	1			T153	770		T403	673		T576	23
valid_sources[0x0b]	42750	1			T87	3		T153	839		T403	709
valid_sources[0x0c]	44183	1			T153	779		T403	675		T576	14
valid_sources[0x0d]	42400	1			T153	745		T403	721		T576	22
valid_sources[0x0e]	41354	1			T153	833		T403	691		T576	26
valid_sources[0x0f]	42323	1			T87	4		T153	795		T403	642
valid_sources[0x10]	41633	1			T153	812		T403	702		T576	14
valid_sources[0x11]	42265	1			T153	805		T403	737		T576	31
valid_sources[0x12]	42386	1			T206	1		T153	785		T403	707
valid_sources[0x13]	42615	1			T88	2		T153	797		T403	708
valid_sources[0x14]	41449	1			T153	841		T403	658		T576	26
valid_sources[0x15]	42579	1			T88	1		T153	861		T403	683
valid_sources[0x16]	42364	1			T88	2		T153	807		T403	677
valid_sources[0x17]	42678	1			T153	805		T403	718		T576	31
valid_sources[0x18]	44754	1			T88	2		T153	804		T403	710
valid_sources[0x19]	42988	1			T87	1		T153	861		T403	737
valid_sources[0x1a]	41661	1			T87	3		T88	4		T153	809
valid_sources[0x1b]	44554	1			T153	792		T403	687		T576	19
valid_sources[0x1c]	42079	1			T88	3		T206	11		T153	789
valid_sources[0x1d]	42280	1			T206	1		T153	815		T403	696
valid_sources[0x1e]	42017	1			T153	734		T403	662		T576	32
valid_sources[0x1f]	42207	1			T153	855		T403	698		T576	30
valid_sources[0x20]	41833	1			T88	2		T153	854		T403	690

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27730038

1

T4

102877

T5

5286

T6

8836

values[0x0]

all_enables

biggest_size

10783492

1

T4

3567

T5

7328

T6

8760

values[0x1]

all_enables

biggest_size

293767

1

T60

20

T87

17

T88

21

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2867827	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

453681

1

T81

21

T82

275

T133

23

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1125215	1			T81	65		T82	654		T83	1
values[0x0]	1072612	1			T81	48		T82	642		T133	72
values[0x1]	1123681	1			T81	57		T82	639		T83	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2220204	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1101304

1

T81

53

T82

688

T83

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52378	1			T81	1		T82	38		T133	6
valid_sources[0x01]	52367	1			T82	39		T133	2		T134	9
valid_sources[0x02]	51131	1			T81	9		T82	28		T133	5
valid_sources[0x03]	52585	1			T82	35		T133	3		T134	2
valid_sources[0x04]	52755	1			T82	40		T134	3		T135	7
valid_sources[0x05]	52784	1			T82	36		T133	1		T134	7
valid_sources[0x06]	53749	1			T82	30		T133	4		T134	2
valid_sources[0x07]	52220	1			T81	4		T82	31		T133	3
valid_sources[0x08]	51587	1			T81	1		T82	23		T133	3
valid_sources[0x09]	51845	1			T81	1		T82	29		T133	3
valid_sources[0x0a]	50133	1			T81	5		T82	20		T133	2
valid_sources[0x0b]	51223	1			T81	3		T82	30		T133	6
valid_sources[0x0c]	52620	1			T81	4		T82	37		T133	2
valid_sources[0x0d]	50483	1			T82	38		T133	2		T134	2
valid_sources[0x0e]	52217	1			T82	57		T133	2		T134	3
valid_sources[0x0f]	51254	1			T82	28		T133	4		T134	2
valid_sources[0x10]	52857	1			T81	3		T82	33		T133	1
valid_sources[0x11]	52135	1			T81	2		T82	29		T133	4
valid_sources[0x12]	51533	1			T81	5		T82	17		T133	2
valid_sources[0x13]	51323	1			T81	1		T82	31		T133	2
valid_sources[0x14]	51961	1			T81	1		T82	27		T133	2
valid_sources[0x15]	52131	1			T81	7		T82	24		T133	3
valid_sources[0x16]	50855	1			T81	13		T82	27		T83	1
valid_sources[0x17]	51780	1			T81	6		T82	17		T133	1
valid_sources[0x18]	51966	1			T81	5		T82	29		T133	6
valid_sources[0x19]	51107	1			T81	6		T82	28		T133	3
valid_sources[0x1a]	52092	1			T81	2		T82	29		T133	2
valid_sources[0x1b]	51288	1			T81	1		T82	35		T133	4
valid_sources[0x1c]	51639	1			T82	31		T133	2		T134	4
valid_sources[0x1d]	51795	1			T82	31		T133	4		T134	2
valid_sources[0x1e]	51884	1			T81	16		T82	29		T133	7
valid_sources[0x1f]	52133	1			T82	42		T133	2		T134	4
valid_sources[0x20]	52452	1			T81	3		T82	29		T133	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47813

1

T81

1

T82

27

T133

2

values[0x0]

all_enables

biggest_size

358652

1

T81

16

T82

221

T133

20

values[0x1]

all_enables

biggest_size

47216

1

T81

4

T82

27

T133

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3049514	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

496713

1

T81

18

T82

259

T133

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1213100	1			T81	40		T82	617		T83	7
values[0x0]	1119724	1			T81	42		T82	596		T133	51
values[0x1]	1213403	1			T81	45		T82	645		T83	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2339625	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1206602

1

T81

44

T82

606

T83

4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	56031	1			T82	28		T133	5		T134	24
valid_sources[0x01]	56317	1			T81	9		T82	30		T133	2
valid_sources[0x02]	54971	1			T81	2		T82	27		T133	3
valid_sources[0x03]	56115	1			T81	1		T82	31		T133	3
valid_sources[0x04]	55923	1			T82	36		T133	1		T134	6
valid_sources[0x05]	55426	1			T81	4		T82	25		T133	5
valid_sources[0x06]	55883	1			T81	9		T82	20		T134	4
valid_sources[0x07]	55376	1			T81	2		T82	40		T133	3
valid_sources[0x08]	55681	1			T81	2		T82	30		T135	16
valid_sources[0x09]	54993	1			T81	2		T82	24		T133	3
valid_sources[0x0a]	55460	1			T81	1		T82	36		T133	2
valid_sources[0x0b]	56119	1			T81	2		T82	24		T133	4
valid_sources[0x0c]	56640	1			T81	2		T82	30		T133	1
valid_sources[0x0d]	54773	1			T81	1		T82	27		T134	21
valid_sources[0x0e]	55323	1			T82	32		T133	4		T134	16
valid_sources[0x0f]	56165	1			T82	33		T134	3		T135	8
valid_sources[0x10]	56403	1			T81	5		T82	29		T134	4
valid_sources[0x11]	55273	1			T81	1		T82	25		T134	1
valid_sources[0x12]	56304	1			T81	1		T82	27		T133	2
valid_sources[0x13]	55307	1			T81	2		T82	29		T133	1
valid_sources[0x14]	55698	1			T82	31		T133	1		T134	37
valid_sources[0x15]	55824	1			T81	3		T82	37		T133	3
valid_sources[0x16]	55204	1			T82	29		T133	2		T134	22
valid_sources[0x17]	55331	1			T81	1		T82	19		T133	2
valid_sources[0x18]	55186	1			T81	5		T82	23		T134	6
valid_sources[0x19]	56012	1			T81	3		T82	29		T83	2
valid_sources[0x1a]	56128	1			T81	2		T82	31		T133	8
valid_sources[0x1b]	54575	1			T82	36		T133	1		T134	7
valid_sources[0x1c]	55221	1			T81	5		T82	23		T134	7
valid_sources[0x1d]	55288	1			T81	2		T82	20		T133	1
valid_sources[0x1e]	55148	1			T81	3		T82	22		T133	3
valid_sources[0x1f]	55520	1			T81	6		T82	32		T133	4
valid_sources[0x20]	56765	1			T82	28		T83	1		T133	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

51813

1

T81

2

T82

21

T133

3

values[0x0]

all_enables

biggest_size

392843

1

T81

15

T82

212

T133

21

values[0x1]

all_enables

biggest_size

52057

1

T81

1

T82

26

T133

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2898039	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

458574

1

T81

15

T82

243

T83

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1135945	1			T81	38		T82	628		T83	2
values[0x0]	1084591	1			T81	38		T82	617		T83	1
values[0x1]	1136077	1			T81	36		T82	592		T83	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2244687	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1111926

1

T81

35

T82

589

T83

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53276	1			T82	29		T133	3		T134	7
valid_sources[0x01]	52468	1			T82	35		T133	2		T134	10
valid_sources[0x02]	52786	1			T82	30		T133	5		T134	18
valid_sources[0x03]	52980	1			T81	1		T82	31		T133	4
valid_sources[0x04]	52856	1			T81	1		T82	32		T133	3
valid_sources[0x05]	52376	1			T82	39		T133	3		T134	5
valid_sources[0x06]	52298	1			T81	14		T82	27		T133	3
valid_sources[0x07]	52632	1			T82	35		T133	9		T134	4
valid_sources[0x08]	51851	1			T82	49		T133	1		T134	3
valid_sources[0x09]	52102	1			T82	30		T133	2		T134	1
valid_sources[0x0a]	51617	1			T82	23		T134	8		T135	8
valid_sources[0x0b]	51649	1			T82	33		T133	1		T134	2
valid_sources[0x0c]	53283	1			T82	23		T133	1		T134	1
valid_sources[0x0d]	51984	1			T81	2		T82	29		T134	2
valid_sources[0x0e]	52796	1			T81	11		T82	31		T133	3
valid_sources[0x0f]	52340	1			T82	16		T133	3		T135	4
valid_sources[0x10]	52580	1			T82	26		T133	2		T134	3
valid_sources[0x11]	52447	1			T82	36		T133	2		T134	4
valid_sources[0x12]	53377	1			T81	10		T82	35		T133	6
valid_sources[0x13]	52545	1			T82	28		T133	4		T134	11
valid_sources[0x14]	52065	1			T82	24		T133	4		T134	5
valid_sources[0x15]	52493	1			T82	32		T133	4		T134	5
valid_sources[0x16]	52179	1			T82	28		T133	2		T134	1
valid_sources[0x17]	52003	1			T82	23		T133	1		T134	1
valid_sources[0x18]	51992	1			T81	3		T82	32		T133	5
valid_sources[0x19]	52289	1			T81	10		T82	25		T133	1
valid_sources[0x1a]	52528	1			T82	18		T133	5		T134	8
valid_sources[0x1b]	51940	1			T82	25		T83	1		T133	2
valid_sources[0x1c]	52299	1			T82	13		T133	5		T134	7
valid_sources[0x1d]	52231	1			T82	21		T133	1		T135	12
valid_sources[0x1e]	52194	1			T82	32		T135	9		T257	49
valid_sources[0x1f]	51899	1			T81	1		T82	35		T133	2
valid_sources[0x20]	53191	1			T81	3		T82	30		T133	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47810

1

T81

1

T82

27

T133

1

values[0x0]

all_enables

biggest_size

362707

1

T81

13

T82

195

T133

20

values[0x1]

all_enables

biggest_size

48057

1

T81

1

T82

21

T83

1