Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522890296	60745016	0	0
DepthKnown_A	522890296	522782540	0	0
RvalidKnown_A	522890296	522782540	0	0
WreadyKnown_A	522890296	522782540	0	0
gen_passthru_fifo.paramCheckPass	1022	1022	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	60745016	0	0
T4	880922	119763	0	0
T5	261894	27115	0	0
T6	268510	33873	0	0
T15	348510	35080	0	0
T16	119109	131618	0	0
T41	268135	35149	0	0
T64	155389	21599	0	0
T65	147327	19817	0	0
T96	96467	11034	0	0
T97	214515	21725	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	522782540	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	522782540	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	522782540	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T41	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T96	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522890296	46858532	0	0
DepthKnown_A	522890296	522782540	0	0
RvalidKnown_A	522890296	522782540	0	0
WreadyKnown_A	522890296	522782540	0	0
gen_passthru_fifo.paramCheckPass	1022	1022	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	46858532	0	0
T4	880922	116533	0	0
T5	261894	20152	0	0
T6	268510	28031	0	0
T15	348510	30589	0	0
T16	119109	113846	0	0
T41	268135	25578	0	0
T64	155389	14329	0	0
T65	147327	14680	0	0
T96	96467	8658	0	0
T97	214515	17731	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	522782540	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	522782540	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	522782540	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T41	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T96	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522890296	44849218	0	0
DepthKnown_A	522890296	522782540	0	0
RvalidKnown_A	522890296	522782540	0	0
WreadyKnown_A	522890296	522782540	0	0
gen_passthru_fifo.paramCheckPass	1022	1022	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	44849218	0	0
T4	880922	109796	0	0
T5	261894	13822	0	0
T6	268510	18785	0	0
T15	348510	31377	0	0
T16	119109	173771	0	0
T41	268135	18214	0	0
T64	155389	8873	0	0
T65	147327	8571	0	0
T96	96467	5763	0	0
T97	214515	20350	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	522782540	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	522782540	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	522782540	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T41	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T96	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	522890296	38247960	0	0
DepthKnown_A	522890296	522782540	0	0
RvalidKnown_A	522890296	522782540	0	0
WreadyKnown_A	522890296	522782540	0	0
gen_passthru_fifo.paramCheckPass	1022	1022	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	38247960	0	0
T4	880922	109616	0	0
T5	261894	13471	0	0
T6	268510	18348	0	0
T15	348510	31059	0	0
T16	119109	105922	0	0
T41	268135	17834	0	0
T64	155389	8488	0	0
T65	147327	8293	0	0
T96	96467	5617	0	0
T97	214515	20145	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	522782540	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	522782540	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	522782540	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T41	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T96	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	610967533	100976	0	0
DepthKnown_A	610967533	610843402	0	0
RvalidKnown_A	610967533	610843402	0	0
WreadyKnown_A	610967533	610843402	0	0
gen_passthru_fifo.paramCheckPass	2932	2932	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610967533	100976	0	0
T4	880922	17	0	0
T5	261894	103	0	0
T6	268510	235	0	0
T15	348510	23	0	0
T16	119109	27	0	0
T41	268135	151	0	0
T64	155389	40	0	0
T65	147327	26	0	0
T96	96467	13	0	0
T97	214515	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610967533	610843402	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610967533	610843402	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610967533	610843402	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2932	2932	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T41	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T96	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	610967533	104685	0	0
DepthKnown_A	610967533	610843402	0	0
RvalidKnown_A	610967533	610843402	0	0
WreadyKnown_A	610967533	610843402	0	0
gen_passthru_fifo.paramCheckPass	2932	2932	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610967533	104685	0	0
T4	880922	17	0	0
T5	261894	103	0	0
T6	268510	235	0	0
T15	348510	23	0	0
T16	119109	27	0	0
T41	268135	151	0	0
T64	155389	40	0	0
T65	147327	26	0	0
T96	96467	13	0	0
T97	214515	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610967533	610843402	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610967533	610843402	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610967533	610843402	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2932	2932	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T41	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T96	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	610967533	52092	0	0
DepthKnown_A	610967533	610843402	0	0
RvalidKnown_A	610967533	610843402	0	0
WreadyKnown_A	610967533	610843402	0	0
gen_passthru_fifo.paramCheckPass	2932	2932	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610967533	52092	0	0
T4	880922	16	0	0
T5	261894	95	0	0
T6	268510	232	0	0
T15	348510	20	0	0
T16	119109	0	0	0
T41	268135	95	0	0
T64	155389	34	0	0
T65	147327	23	0	0
T96	96467	12	0	0
T97	214515	52	0	0
T201	0	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610967533	610843402	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610967533	610843402	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610967533	610843402	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2932	2932	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T41	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T96	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	610967533	52092	0	0
DepthKnown_A	610967533	610843402	0	0
RvalidKnown_A	610967533	610843402	0	0
WreadyKnown_A	610967533	610843402	0	0
gen_passthru_fifo.paramCheckPass	2932	2932	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610967533	52092	0	0
T4	880922	16	0	0
T5	261894	95	0	0
T6	268510	232	0	0
T15	348510	20	0	0
T16	119109	0	0	0
T41	268135	95	0	0
T64	155389	34	0	0
T65	147327	23	0	0
T96	96467	12	0	0
T97	214515	52	0	0
T201	0	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610967533	610843402	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610967533	610843402	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610967533	610843402	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2932	2932	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T41	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T96	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	610967533	48884	0	0
DepthKnown_A	610967533	610843402	0	0
RvalidKnown_A	610967533	610843402	0	0
WreadyKnown_A	610967533	610843402	0	0
gen_passthru_fifo.paramCheckPass	2932	2932	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610967533	48884	0	0
T4	880922	1	0	0
T5	261894	8	0	0
T6	268510	3	0	0
T15	348510	3	0	0
T16	119109	27	0	0
T41	268135	56	0	0
T64	155389	6	0	0
T65	147327	3	0	0
T96	96467	1	0	0
T97	214515	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610967533	610843402	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610967533	610843402	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610967533	610843402	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2932	2932	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T41	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T96	1	1	0	0
T97	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	610967533	52593	0	0
DepthKnown_A	610967533	610843402	0	0
RvalidKnown_A	610967533	610843402	0	0
WreadyKnown_A	610967533	610843402	0	0
gen_passthru_fifo.paramCheckPass	2932	2932	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610967533	52593	0	0
T4	880922	1	0	0
T5	261894	8	0	0
T6	268510	3	0	0
T15	348510	3	0	0
T16	119109	27	0	0
T41	268135	56	0	0
T64	155389	6	0	0
T65	147327	3	0	0
T96	96467	1	0	0
T97	214515	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610967533	610843402	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610967533	610843402	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610967533	610843402	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2932	2932	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T41	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T96	1	1	0	0
T97	1	1	0	0