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Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_regwen_0.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_dbus_regwen_0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_regwen_1.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_dbus_regwen_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_addr_en_0.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_dbus_addr_en_0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_addr_en_1.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_dbus_addr_en_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_addr_matching_0.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_dbus_addr_matching_0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_addr_matching_1.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_dbus_addr_matching_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_remap_addr_0.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_dbus_remap_addr_0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_remap_addr_1.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_dbus_remap_addr_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_nmi_enable_alert_en.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_nmi_enable_alert_en


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_nmi_enable_wdog_en.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_nmi_enable_wdog_en


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_nmi_state_alert.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_nmi_state_alert


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_nmi_state_wdog.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_nmi_state_wdog


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_err_status_reg_intg_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.00 100.00 90.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.00 100.00 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_err_status_reg_intg_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_regwen_0.wr_en_data_arb
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_regwen_1.wr_en_data_arb
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_addr_en_0.wr_en_data_arb
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_addr_en_1.wr_en_data_arb
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_addr_matching_0.wr_en_data_arb
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_addr_matching_1.wr_en_data_arb
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_remap_addr_0.wr_en_data_arb
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_remap_addr_1.wr_en_data_arb
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_nmi_enable_alert_en.wr_en_data_arb
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_nmi_enable_wdog_en.wr_en_data_arb
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_nmi_state_alert.wr_en_data_arb
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_nmi_state_wdog.wr_en_data_arb
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_err_status_reg_intg_err.wr_en_data_arb
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_regwen_0.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
113 1 1
135 1 1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_regwen_0.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT550,T572,T153 

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT153,T387,T390
10CoveredT550,T572,T153
11CoveredT4,T5,T6 

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1Unreachable 

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT550,T572,T153
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_regwen_1.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
113 1 1
135 1 1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_regwen_1.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT82,T135,T153 

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT153,T154,T387
10CoveredT82,T135,T153
11CoveredT4,T5,T6 

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1Unreachable 

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT82,T135,T153
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_addr_en_0.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_addr_en_0.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT180,T183,T306 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT180,T183,T306 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT180,T183,T306
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_addr_en_0.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T180,T183,T306
0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_addr_en_1.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_addr_en_1.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT180,T183,T306 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT180,T183,T306 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT180,T183,T306
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_addr_en_1.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T180,T183,T306
0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_addr_matching_0.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_addr_matching_0.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT180,T183,T306 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT180,T183,T306 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT180,T183,T306
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_addr_matching_0.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T180,T183,T306
0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_addr_matching_1.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_addr_matching_1.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT180,T183,T306 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT180,T183,T306 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT180,T183,T306
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_addr_matching_1.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T180,T183,T306
0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_remap_addr_0.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_remap_addr_0.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT180,T183,T306 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT180,T183,T306 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT180,T183,T306
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_remap_addr_0.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T180,T183,T306
0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_remap_addr_1.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_remap_addr_1.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT180,T183,T306 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT180,T183,T306 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT180,T183,T306
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_dbus_remap_addr_1.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T180,T183,T306
0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_nmi_enable_alert_en.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN8211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
82 1 1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_nmi_enable_alert_en.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       60
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT5,T16,T41 

 LINE       82
 EXPRESSION ((de ? d : q) | (we ? wd : '0))
             ------1-----   -------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT5,T41,T200
10CoveredT5,T41,T200 

 LINE       82
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1Unreachable 

 LINE       82
 SUB-EXPRESSION (we ? wd : '0)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T16,T41
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_nmi_enable_wdog_en.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN8211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
82 1 1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_nmi_enable_wdog_en.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       60
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T6
01Unreachable
10CoveredT5,T16,T41 

 LINE       82
 EXPRESSION ((de ? d : q) | (we ? wd : '0))
             ------1-----   -------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT5,T16,T41
10CoveredT5,T16,T41 

 LINE       82
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1Unreachable 

 LINE       82
 SUB-EXPRESSION (we ? wd : '0)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T16,T41
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_nmi_state_alert.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN11011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
88 1 1
110 1 1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_nmi_state_alert.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT5,T41,T65
10CoveredT101,T157,T259 

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT101,T547,T768
11CoveredT5,T41,T65 

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T41,T65 

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT101,T157,T259
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_nmi_state_wdog.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN11011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
88 1 1
110 1 1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_nmi_state_wdog.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT262,T68,T263
10CoveredT101,T157,T259 

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT101,T157,T259
11CoveredT262,T68,T263 

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT262,T68,T263 

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT101,T157,T259
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_err_status_reg_intg_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN11011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
88 1 1
110 1 1

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_err_status_reg_intg_err.wr_en_data_arb
TotalCoveredPercent
Conditions10990.00
Logical10990.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT200,T253,T254
10CoveredT523,T153,T465 

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT4,T5,T6
10Not Covered
11CoveredT200,T253,T254 

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT200,T253,T254 

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT523,T153,T465
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%