Module Definition
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Module : pattgen
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_pattgen_0.1/rtl/pattgen.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_pattgen 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_pattgen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : pattgen
TotalCoveredPercent
Totals 35 35 100.00
Total Bits 300 300 100.00
Total Bits 0->1 150 150 100.00
Total Bits 1->0 150 150 100.00

Ports 35 35 100.00
Port Bits 300 300 100.00
Port Bits 0->1 150 150 100.00
Port Bits 1->0 150 150 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T5,T16,T64 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T221,T222,T356 Yes T221,T222,T356 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T221,T222,T356 Yes T221,T222,T356 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[5:0] Yes Yes *T81,*T82,*T83 Yes T81,T82,T83 INPUT
tl_i.a_address[16:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[19:17] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:20] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T84,*T85,*T86 Yes T84,T85,T86 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T60,T87,T88 Yes T60,T87,T88 INPUT
tl_i.a_valid Yes Yes T221,T222,T61 Yes T221,T222,T61 INPUT
tl_o.a_ready Yes Yes T221,T222,T61 Yes T221,T222,T61 OUTPUT
tl_o.d_error Yes Yes T82,T83,T133 Yes T82,T83,T133 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T221,T222,T356 Yes T221,T222,T356 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T221,T222,T356 Yes T221,T222,T61 OUTPUT
tl_o.d_data[31:0] Yes Yes T221,T222,T356 Yes T221,T222,T61 OUTPUT
tl_o.d_sink Yes Yes T81,T82,T83 Yes T81,T82,T83 OUTPUT
tl_o.d_source[5:0] Yes Yes *T60,T82,T83 Yes T60,T81,T82 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T81,T82,T83 Yes T81,T82,T83 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T221,*T222,*T356 Yes T221,T222,T356 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T221,T222,T61 Yes T221,T222,T61 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T89,T110,T92 Yes T89,T110,T92 INPUT
alert_rx_i[0].ping_n Yes Yes T89,T92,T94 Yes T89,T92,T94 INPUT
alert_rx_i[0].ping_p Yes Yes T89,T92,T94 Yes T89,T92,T94 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T89,T110,T92 Yes T89,T110,T92 OUTPUT
cio_pda0_tx_o Yes Yes T222,T60,T153 Yes T222,T60,T153 OUTPUT
cio_pcl0_tx_o Yes Yes T222,T60,T153 Yes T222,T60,T153 OUTPUT
cio_pda1_tx_o Yes Yes T221,T222,T356 Yes T221,T222,T356 OUTPUT
cio_pcl1_tx_o Yes Yes T221,T222,T356 Yes T221,T222,T356 OUTPUT
cio_pda0_tx_en_o Unreachable Unreachable Unreachable OUTPUT
cio_pcl0_tx_en_o Unreachable Unreachable Unreachable OUTPUT
cio_pda1_tx_en_o Unreachable Unreachable Unreachable OUTPUT
cio_pcl1_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_done_ch0_o Yes Yes T222,T161,T162 Yes T222,T161,T162 OUTPUT
intr_done_ch1_o Yes Yes T221,T222,T356 Yes T221,T222,T356 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%