Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : usbdev
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.12 94.12

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_usbdev 94.12 94.12


Module Instance : tb.dut.top_earlgrey.u_usbdev

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.12 94.12


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.12 94.12


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : usbdev
TotalCoveredPercent
Totals 77 71 92.21
Total Bits 408 384 94.12
Total Bits 0->1 204 192 94.12
Total Bits 1->0 204 192 94.12

Ports 77 71 92.21
Port Bits 408 384 94.12
Port Bits 0->1 204 192 94.12
Port Bits 1->0 204 192 94.12

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T5,T16,T64 Yes T4,T5,T6 INPUT
clk_aon_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_aon_ni Yes Yes T5,T16,T64 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T6,T201,T3 Yes T6,T201,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T6,T201,T3 Yes T6,T201,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T6,T201,T3 Yes T6,T201,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T6,T201,T3 Yes T6,T201,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T6,T201,T3 Yes T6,T201,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T6,T201,T3 Yes T6,T201,T3 INPUT
tl_i.a_address[11:0] Yes Yes *T81,*T82,*T83 Yes T81,T82,T83 INPUT
tl_i.a_address[16:12] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17] Yes Yes *T6,*T201,*T3 Yes T6,T201,T3 INPUT
tl_i.a_address[19:18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[21:20] Yes Yes T6,T201,T3 Yes T6,T201,T3 INPUT
tl_i.a_address[29:22] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T6,*T201,*T3 Yes T6,T201,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T60,*T88,*T152 Yes T60,T88,T152 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
tl_i.a_valid Yes Yes T6,T201,T3 Yes T6,T201,T3 INPUT
tl_o.a_ready Yes Yes T6,T201,T3 Yes T6,T201,T3 OUTPUT
tl_o.d_error Yes Yes T82,T133,T134 Yes T82,T83,T133 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T6,T201,T27 Yes T6,T201,T27 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T6,T201,T27 Yes T6,T201,T27 OUTPUT
tl_o.d_data[31:0] Yes Yes T6,T201,T3 Yes T6,T201,T3 OUTPUT
tl_o.d_sink Yes Yes T81,T82,T83 Yes T81,T82,T83 OUTPUT
tl_o.d_source[5:0] Yes Yes *T60,*T88,*T152 Yes T60,T88,T152 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T81,T82,T83 Yes T81,T82,T83 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T6,*T201,*T3 Yes T6,T201,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T6,T201,T3 Yes T6,T201,T3 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T89,T92,T94 Yes T89,T92,T94 INPUT
alert_rx_i[0].ping_n Yes Yes T89,T92,T94 Yes T89,T92,T94 INPUT
alert_rx_i[0].ping_p Yes Yes T89,T92,T94 Yes T89,T92,T94 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T89,T92,T94 Yes T89,T92,T94 OUTPUT
cio_usb_dp_i Yes Yes T27,T20,T31 Yes T27,T20,T31 INPUT
cio_usb_dn_i Yes Yes T27,T31,T78 Yes T27,T19,T20 INPUT
usb_rx_d_i Yes Yes T27,T31,T78 Yes T27,T31,T78 INPUT
cio_usb_dp_o Yes Yes T3,T7,T27 Yes T3,T7,T27 OUTPUT
cio_usb_dp_en_o Yes Yes T27,T31,T32 Yes T27,T31,T32 OUTPUT
cio_usb_dn_o Yes Yes T27,T31,T32 Yes T27,T31,T78 OUTPUT
cio_usb_dn_en_o Yes Yes T27,T31,T32 Yes T27,T31,T32 OUTPUT
usb_tx_se0_o Yes Yes T27,T31,T32 Yes T27,T31,T32 OUTPUT
usb_tx_d_o Yes Yes T3,T7,T27 Yes T3,T7,T27 OUTPUT
cio_sense_i Yes Yes T80,T399,T400 Yes T27,T401,T31 INPUT
usb_dp_pullup_o Yes Yes T3,T7,T10 Yes T3,T7,T27 OUTPUT
usb_dn_pullup_o Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
usb_rx_enable_o Yes Yes T80,T140,T147 Yes T27,T31,T78 OUTPUT
usb_tx_use_d_se0_o Yes Yes T152,T153,T154 Yes T152,T153,T154 OUTPUT
usb_aon_suspend_req_o Yes Yes T3,T7,T10 Yes T3,T7,T10 OUTPUT
usb_aon_wake_ack_o Yes Yes T3,T7,T60 Yes T3,T7,T60 OUTPUT
usb_aon_bus_reset_i Yes Yes T79 Yes T79 INPUT
usb_aon_sense_lost_i Yes Yes T3,T7,T10 Yes T3,T7,T10 INPUT
usb_aon_bus_not_idle_i Yes Yes T3,T7,T10 Yes T3,T7,T10 INPUT
usb_aon_wake_detect_active_i Yes Yes T3,T7,T10 Yes T3,T7,T10 INPUT
usb_ref_val_o Yes Yes T31,T32,T155 Yes T27,T31,T32 OUTPUT
usb_ref_pulse_o Yes Yes T27,T31,T32 Yes T27,T31,T32 OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.rf_cfg.test No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.test No No No INPUT
intr_pkt_received_o Yes Yes T6,T329,T328 Yes T6,T329,T328 OUTPUT
intr_pkt_sent_o Yes Yes T6,T329,T328 Yes T6,T329,T328 OUTPUT
intr_powered_o Yes Yes T6,T329,T328 Yes T6,T329,T328 OUTPUT
intr_disconnected_o Yes Yes T6,T329,T328 Yes T6,T329,T328 OUTPUT
intr_host_lost_o Yes Yes T6,T329,T328 Yes T6,T329,T328 OUTPUT
intr_link_reset_o Yes Yes T6,T329,T328 Yes T6,T329,T328 OUTPUT
intr_link_suspend_o Yes Yes T6,T329,T328 Yes T6,T329,T328 OUTPUT
intr_link_resume_o Yes Yes T6,T329,T328 Yes T6,T329,T328 OUTPUT
intr_av_out_empty_o Yes Yes T6,T329,T328 Yes T6,T329,T328 OUTPUT
intr_rx_full_o Yes Yes T6,T329,T328 Yes T6,T329,T328 OUTPUT
intr_av_overflow_o Yes Yes T6,T329,T328 Yes T6,T329,T328 OUTPUT
intr_link_in_err_o Yes Yes T6,T329,T328 Yes T6,T329,T328 OUTPUT
intr_link_out_err_o Yes Yes T6,T329,T328 Yes T6,T329,T328 OUTPUT
intr_rx_crc_err_o Yes Yes T6,T329,T328 Yes T6,T329,T328 OUTPUT
intr_rx_pid_err_o Yes Yes T6,T329,T328 Yes T6,T329,T328 OUTPUT
intr_rx_bitstuff_err_o Yes Yes T6,T329,T328 Yes T6,T329,T328 OUTPUT
intr_frame_o Yes Yes T6,T329,T328 Yes T6,T329,T328 OUTPUT
intr_av_setup_empty_o Yes Yes T6,T329,T328 Yes T6,T329,T328 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%