Toggle Coverage for Module :
uart
| Total | Covered | Percent |
Totals |
40 |
40 |
100.00 |
Total Bits |
308 |
308 |
100.00 |
Total Bits 0->1 |
154 |
154 |
100.00 |
Total Bits 1->0 |
154 |
154 |
100.00 |
| | | |
Ports |
40 |
40 |
100.00 |
Port Bits |
308 |
308 |
100.00 |
Port Bits 0->1 |
154 |
154 |
100.00 |
Port Bits 1->0 |
154 |
154 |
100.00 |
Port Details
| | | | | | |
clk_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
rst_ni |
Yes |
Yes |
T5,T16,T64 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T6,T16,T97 |
Yes |
T6,T16,T97 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T6,T16,T97 |
Yes |
T6,T16,T97 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[5:0] |
Yes |
Yes |
*T81,*T82,*T83 |
Yes |
T81,T82,T83 |
INPUT |
tl_i.a_address[15:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[17:16] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[29:18] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[30] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_source[5:0] |
Yes |
Yes |
*T84,*T85,*T86 |
Yes |
T84,T85,T86 |
INPUT |
tl_i.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T81,T82,T83 |
Yes |
T81,T82,T83 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T60,T87,T88 |
Yes |
T60,T87,T88 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T6,T16,T97 |
Yes |
T6,T16,T97 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T6,T16,T97 |
Yes |
T6,T16,T97 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T81,T82,T83 |
Yes |
T81,T82,T83 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T6,T16,T97 |
Yes |
T6,T16,T97 |
OUTPUT |
tl_o.d_user.rsp_intg[6:0] |
Yes |
Yes |
T6,T16,T97 |
Yes |
T6,T16,T97 |
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T6,T16,T97 |
Yes |
T6,T16,T97 |
OUTPUT |
tl_o.d_sink |
Yes |
Yes |
T81,T82,T83 |
Yes |
T81,T82,T83 |
OUTPUT |
tl_o.d_source[5:0] |
Yes |
Yes |
*T60,*T88,*T266 |
Yes |
T60,T88,T266 |
OUTPUT |
tl_o.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T81,T82,T83 |
Yes |
T81,T82,T83 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T6,*T16,*T97 |
Yes |
T6,T16,T97 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T6,T16,T97 |
Yes |
T6,T16,T97 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T89,T92,T249 |
Yes |
T89,T92,T249 |
INPUT |
alert_rx_i[0].ping_n |
Yes |
Yes |
T89,T92,T94 |
Yes |
T89,T92,T94 |
INPUT |
alert_rx_i[0].ping_p |
Yes |
Yes |
T89,T92,T94 |
Yes |
T89,T92,T94 |
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T89,T92,T249 |
Yes |
T89,T92,T249 |
OUTPUT |
cio_rx_i |
Yes |
Yes |
T5,T16,T97 |
Yes |
T4,T5,T6 |
INPUT |
cio_tx_o |
Yes |
Yes |
T16,T97,T225 |
Yes |
T16,T97,T225 |
OUTPUT |
cio_tx_en_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
intr_tx_watermark_o |
Yes |
Yes |
T6,T97,T225 |
Yes |
T6,T97,T225 |
OUTPUT |
intr_tx_empty_o |
Yes |
Yes |
T6,T97,T225 |
Yes |
T6,T97,T225 |
OUTPUT |
intr_rx_watermark_o |
Yes |
Yes |
T6,T97,T225 |
Yes |
T6,T97,T225 |
OUTPUT |
intr_tx_done_o |
Yes |
Yes |
T6,T97,T225 |
Yes |
T6,T97,T225 |
OUTPUT |
intr_rx_overflow_o |
Yes |
Yes |
T6,T97,T225 |
Yes |
T6,T97,T225 |
OUTPUT |
intr_rx_frame_err_o |
Yes |
Yes |
T6,T329,T328 |
Yes |
T6,T329,T328 |
OUTPUT |
intr_rx_break_err_o |
Yes |
Yes |
T6,T329,T328 |
Yes |
T6,T329,T328 |
OUTPUT |
intr_rx_timeout_o |
Yes |
Yes |
T6,T329,T328 |
Yes |
T6,T329,T328 |
OUTPUT |
intr_rx_parity_err_o |
Yes |
Yes |
T6,T329,T328 |
Yes |
T6,T329,T328 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0
| Total | Covered | Percent |
Totals |
40 |
40 |
100.00 |
Total Bits |
304 |
304 |
100.00 |
Total Bits 0->1 |
152 |
152 |
100.00 |
Total Bits 1->0 |
152 |
152 |
100.00 |
| | | |
Ports |
40 |
40 |
100.00 |
Port Bits |
304 |
304 |
100.00 |
Port Bits 0->1 |
152 |
152 |
100.00 |
Port Bits 1->0 |
152 |
152 |
100.00 |
Port Details
| | | | | | |
clk_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
rst_ni |
Yes |
Yes |
T5,T16,T64 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T6,T16,T225 |
Yes |
T6,T16,T225 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T6,T16,T225 |
Yes |
T6,T16,T225 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[5:0] |
Yes |
Yes |
*T81,*T82,*T83 |
Yes |
T81,T82,T83 |
INPUT |
tl_i.a_address[29:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[30] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_source[5:0] |
Yes |
Yes |
*T84,*T85,*T86 |
Yes |
T84,T85,T86 |
INPUT |
tl_i.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T81,T82,T83 |
Yes |
T81,T82,T83 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T60,T87,T88 |
Yes |
T60,T87,T88 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T6,T16,T225 |
Yes |
T6,T16,T225 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T6,T16,T225 |
Yes |
T6,T16,T225 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T81,T82,T83 |
Yes |
T81,T82,T83 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T6,T16,T225 |
Yes |
T6,T16,T225 |
OUTPUT |
tl_o.d_user.rsp_intg[6:0] |
Yes |
Yes |
T6,T16,T225 |
Yes |
T6,T16,T225 |
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T6,T16,T225 |
Yes |
T6,T16,T225 |
OUTPUT |
tl_o.d_sink |
Yes |
Yes |
T81,T82,T83 |
Yes |
T81,T82,T83 |
OUTPUT |
tl_o.d_source[5:0] |
Yes |
Yes |
*T60,*T88,*T266 |
Yes |
T60,T88,T266 |
OUTPUT |
tl_o.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T81,T82,T83 |
Yes |
T81,T82,T83 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T6,*T16,*T225 |
Yes |
T6,T16,T225 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T6,T16,T225 |
Yes |
T6,T16,T225 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T89,T92,T249 |
Yes |
T89,T92,T249 |
INPUT |
alert_rx_i[0].ping_n |
Yes |
Yes |
T89,T92,T94 |
Yes |
T89,T92,T94 |
INPUT |
alert_rx_i[0].ping_p |
Yes |
Yes |
T89,T92,T94 |
Yes |
T89,T92,T94 |
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T89,T92,T249 |
Yes |
T89,T92,T249 |
OUTPUT |
cio_rx_i |
Yes |
Yes |
T5,T16,T41 |
Yes |
T4,T5,T6 |
INPUT |
cio_tx_o |
Yes |
Yes |
T16,T225,T53 |
Yes |
T16,T225,T53 |
OUTPUT |
cio_tx_en_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
intr_tx_watermark_o |
Yes |
Yes |
T6,T225,T226 |
Yes |
T6,T225,T226 |
OUTPUT |
intr_tx_empty_o |
Yes |
Yes |
T6,T225,T226 |
Yes |
T6,T225,T226 |
OUTPUT |
intr_rx_watermark_o |
Yes |
Yes |
T6,T225,T226 |
Yes |
T6,T225,T226 |
OUTPUT |
intr_tx_done_o |
Yes |
Yes |
T6,T225,T340 |
Yes |
T6,T225,T340 |
OUTPUT |
intr_rx_overflow_o |
Yes |
Yes |
T6,T225,T340 |
Yes |
T6,T225,T340 |
OUTPUT |
intr_rx_frame_err_o |
Yes |
Yes |
T6,T329,T328 |
Yes |
T6,T329,T328 |
OUTPUT |
intr_rx_break_err_o |
Yes |
Yes |
T6,T329,T328 |
Yes |
T6,T329,T328 |
OUTPUT |
intr_rx_timeout_o |
Yes |
Yes |
T6,T329,T328 |
Yes |
T6,T329,T328 |
OUTPUT |
intr_rx_parity_err_o |
Yes |
Yes |
T6,T329,T328 |
Yes |
T6,T329,T328 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1
| Total | Covered | Percent |
Totals |
40 |
40 |
100.00 |
Total Bits |
306 |
306 |
100.00 |
Total Bits 0->1 |
153 |
153 |
100.00 |
Total Bits 1->0 |
153 |
153 |
100.00 |
| | | |
Ports |
40 |
40 |
100.00 |
Port Bits |
306 |
306 |
100.00 |
Port Bits 0->1 |
153 |
153 |
100.00 |
Port Bits 1->0 |
153 |
153 |
100.00 |
Port Details
| | | | | | |
clk_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
rst_ni |
Yes |
Yes |
T5,T16,T64 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T6,T108,T220 |
Yes |
T6,T108,T220 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T6,T108,T220 |
Yes |
T6,T108,T220 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[5:0] |
Yes |
Yes |
*T81,*T82,*T83 |
Yes |
T81,T82,T83 |
INPUT |
tl_i.a_address[15:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[16] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[29:17] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[30] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_source[5:0] |
Yes |
Yes |
*T84,*T85,*T86 |
Yes |
T84,T85,T86 |
INPUT |
tl_i.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T81,T82,T83 |
Yes |
T81,T82,T83 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T60,T87,T88 |
Yes |
T60,T87,T88 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T6,T108,T249 |
Yes |
T6,T108,T249 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T6,T108,T249 |
Yes |
T6,T108,T249 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T82,T83,T133 |
Yes |
T82,T133,T134 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T6,T108,T220 |
Yes |
T6,T108,T220 |
OUTPUT |
tl_o.d_user.rsp_intg[6:0] |
Yes |
Yes |
T6,T108,T249 |
Yes |
T6,T108,T249 |
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T6,T108,T249 |
Yes |
T6,T108,T249 |
OUTPUT |
tl_o.d_sink |
Yes |
Yes |
T81,T82,T83 |
Yes |
T81,T82,T83 |
OUTPUT |
tl_o.d_source[5:0] |
Yes |
Yes |
*T60,*T88,*T152 |
Yes |
T60,T88,T152 |
OUTPUT |
tl_o.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T82,T83,T133 |
Yes |
T81,T82,T83 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T6,*T108,*T220 |
Yes |
T6,T108,T220 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T6,T108,T249 |
Yes |
T6,T108,T249 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T89,T92,T249 |
Yes |
T89,T92,T249 |
INPUT |
alert_rx_i[0].ping_n |
Yes |
Yes |
T89,T92,T94 |
Yes |
T89,T92,T94 |
INPUT |
alert_rx_i[0].ping_p |
Yes |
Yes |
T89,T92,T94 |
Yes |
T89,T92,T94 |
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T89,T92,T249 |
Yes |
T89,T92,T249 |
OUTPUT |
cio_rx_i |
Yes |
Yes |
T43,T108,T220 |
Yes |
T43,T108,T220 |
INPUT |
cio_tx_o |
Yes |
Yes |
T108,T220,T207 |
Yes |
T108,T220,T207 |
OUTPUT |
cio_tx_en_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
intr_tx_watermark_o |
Yes |
Yes |
T6,T108,T220 |
Yes |
T6,T108,T220 |
OUTPUT |
intr_tx_empty_o |
Yes |
Yes |
T6,T108,T220 |
Yes |
T6,T108,T220 |
OUTPUT |
intr_rx_watermark_o |
Yes |
Yes |
T6,T108,T220 |
Yes |
T6,T108,T220 |
OUTPUT |
intr_tx_done_o |
Yes |
Yes |
T6,T108,T220 |
Yes |
T6,T108,T220 |
OUTPUT |
intr_rx_overflow_o |
Yes |
Yes |
T6,T108,T220 |
Yes |
T6,T108,T220 |
OUTPUT |
intr_rx_frame_err_o |
Yes |
Yes |
T6,T329,T328 |
Yes |
T6,T329,T328 |
OUTPUT |
intr_rx_break_err_o |
Yes |
Yes |
T6,T329,T328 |
Yes |
T6,T329,T328 |
OUTPUT |
intr_rx_timeout_o |
Yes |
Yes |
T6,T329,T328 |
Yes |
T6,T329,T328 |
OUTPUT |
intr_rx_parity_err_o |
Yes |
Yes |
T6,T329,T328 |
Yes |
T6,T329,T328 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2
| Total | Covered | Percent |
Totals |
40 |
40 |
100.00 |
Total Bits |
306 |
306 |
100.00 |
Total Bits 0->1 |
153 |
153 |
100.00 |
Total Bits 1->0 |
153 |
153 |
100.00 |
| | | |
Ports |
40 |
40 |
100.00 |
Port Bits |
306 |
306 |
100.00 |
Port Bits 0->1 |
153 |
153 |
100.00 |
Port Bits 1->0 |
153 |
153 |
100.00 |
Port Details
| | | | | | |
clk_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
rst_ni |
Yes |
Yes |
T5,T16,T64 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T6,T97,T156 |
Yes |
T6,T97,T156 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T6,T97,T156 |
Yes |
T6,T97,T156 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[5:0] |
Yes |
Yes |
*T81,*T82,*T83 |
Yes |
T81,T82,T83 |
INPUT |
tl_i.a_address[16:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[17] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[29:18] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[30] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_source[5:0] |
Yes |
Yes |
*T84,*T85,*T86 |
Yes |
T84,T85,T86 |
INPUT |
tl_i.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T81,T82,T83 |
Yes |
T81,T82,T83 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T60,T87,T88 |
Yes |
T60,T87,T88 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T6,T97,T156 |
Yes |
T6,T97,T156 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T6,T97,T156 |
Yes |
T6,T97,T156 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T82,T83,T134 |
Yes |
T82,T83,T134 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T6,T97,T156 |
Yes |
T6,T97,T156 |
OUTPUT |
tl_o.d_user.rsp_intg[6:0] |
Yes |
Yes |
T6,T97,T156 |
Yes |
T6,T97,T156 |
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T6,T97,T156 |
Yes |
T6,T97,T156 |
OUTPUT |
tl_o.d_sink |
Yes |
Yes |
T81,T82,T83 |
Yes |
T81,T82,T83 |
OUTPUT |
tl_o.d_source[5:0] |
Yes |
Yes |
*T60,*T88,*T152 |
Yes |
T60,T88,T152 |
OUTPUT |
tl_o.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T81,T82,T133 |
Yes |
T82,T133,T134 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T6,*T97,*T156 |
Yes |
T6,T97,T156 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T6,T97,T156 |
Yes |
T6,T97,T156 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T89,T92,T249 |
Yes |
T89,T92,T249 |
INPUT |
alert_rx_i[0].ping_n |
Yes |
Yes |
T89,T92,T94 |
Yes |
T89,T92,T94 |
INPUT |
alert_rx_i[0].ping_p |
Yes |
Yes |
T89,T92,T94 |
Yes |
T89,T92,T94 |
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T89,T92,T249 |
Yes |
T89,T92,T249 |
OUTPUT |
cio_rx_i |
Yes |
Yes |
T97,T156,T126 |
Yes |
T97,T156,T126 |
INPUT |
cio_tx_o |
Yes |
Yes |
T97,T156,T126 |
Yes |
T97,T156,T126 |
OUTPUT |
cio_tx_en_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
intr_tx_watermark_o |
Yes |
Yes |
T6,T97,T156 |
Yes |
T6,T97,T156 |
OUTPUT |
intr_tx_empty_o |
Yes |
Yes |
T6,T97,T156 |
Yes |
T6,T97,T156 |
OUTPUT |
intr_rx_watermark_o |
Yes |
Yes |
T6,T97,T156 |
Yes |
T6,T97,T156 |
OUTPUT |
intr_tx_done_o |
Yes |
Yes |
T6,T97,T156 |
Yes |
T6,T97,T156 |
OUTPUT |
intr_rx_overflow_o |
Yes |
Yes |
T6,T97,T156 |
Yes |
T6,T97,T156 |
OUTPUT |
intr_rx_frame_err_o |
Yes |
Yes |
T6,T329,T328 |
Yes |
T6,T329,T328 |
OUTPUT |
intr_rx_break_err_o |
Yes |
Yes |
T6,T329,T328 |
Yes |
T6,T329,T328 |
OUTPUT |
intr_rx_timeout_o |
Yes |
Yes |
T6,T329,T328 |
Yes |
T6,T329,T328 |
OUTPUT |
intr_rx_parity_err_o |
Yes |
Yes |
T6,T329,T328 |
Yes |
T6,T329,T328 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3
| Total | Covered | Percent |
Totals |
40 |
40 |
100.00 |
Total Bits |
308 |
308 |
100.00 |
Total Bits 0->1 |
154 |
154 |
100.00 |
Total Bits 1->0 |
154 |
154 |
100.00 |
| | | |
Ports |
40 |
40 |
100.00 |
Port Bits |
308 |
308 |
100.00 |
Port Bits 0->1 |
154 |
154 |
100.00 |
Port Bits 1->0 |
154 |
154 |
100.00 |
Port Details
| | | | | | |
clk_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
rst_ni |
Yes |
Yes |
T5,T16,T64 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T6,T25,T26 |
Yes |
T6,T25,T26 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T6,T25,T26 |
Yes |
T6,T25,T26 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[5:0] |
Yes |
Yes |
*T81,*T82,*T83 |
Yes |
T81,T82,T83 |
INPUT |
tl_i.a_address[15:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[17:16] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[29:18] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[30] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_source[5:0] |
Yes |
Yes |
*T84,*T85,*T86 |
Yes |
T84,T85,T86 |
INPUT |
tl_i.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T81,T82,T83 |
Yes |
T81,T82,T83 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T60,T87,T88 |
Yes |
T60,T87,T88 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T6,T25,T26 |
Yes |
T6,T25,T26 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T6,T25,T26 |
Yes |
T6,T25,T26 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T81,T82,T83 |
Yes |
T81,T82,T83 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T6,T25,T26 |
Yes |
T6,T25,T26 |
OUTPUT |
tl_o.d_user.rsp_intg[6:0] |
Yes |
Yes |
T6,T25,T26 |
Yes |
T6,T25,T26 |
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T6,T25,T26 |
Yes |
T6,T25,T26 |
OUTPUT |
tl_o.d_sink |
Yes |
Yes |
T81,T82,T83 |
Yes |
T81,T82,T83 |
OUTPUT |
tl_o.d_source[5:0] |
Yes |
Yes |
*T60,*T88,*T152 |
Yes |
T60,T88,T152 |
OUTPUT |
tl_o.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T81,T82,T83 |
Yes |
T81,T82,T83 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T6,*T25,*T26 |
Yes |
T6,T25,T26 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T6,T25,T26 |
Yes |
T6,T25,T26 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T89,T92,T249 |
Yes |
T89,T92,T249 |
INPUT |
alert_rx_i[0].ping_n |
Yes |
Yes |
T89,T92,T94 |
Yes |
T89,T92,T94 |
INPUT |
alert_rx_i[0].ping_p |
Yes |
Yes |
T89,T92,T94 |
Yes |
T89,T92,T94 |
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T89,T92,T249 |
Yes |
T89,T92,T249 |
OUTPUT |
cio_rx_i |
Yes |
Yes |
T25,T26,T353 |
Yes |
T25,T26,T353 |
INPUT |
cio_tx_o |
Yes |
Yes |
T25,T26,T353 |
Yes |
T25,T26,T353 |
OUTPUT |
cio_tx_en_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
intr_tx_watermark_o |
Yes |
Yes |
T6,T25,T26 |
Yes |
T6,T25,T26 |
OUTPUT |
intr_tx_empty_o |
Yes |
Yes |
T6,T25,T26 |
Yes |
T6,T25,T26 |
OUTPUT |
intr_rx_watermark_o |
Yes |
Yes |
T6,T25,T26 |
Yes |
T6,T25,T26 |
OUTPUT |
intr_tx_done_o |
Yes |
Yes |
T6,T25,T26 |
Yes |
T6,T25,T26 |
OUTPUT |
intr_rx_overflow_o |
Yes |
Yes |
T6,T25,T26 |
Yes |
T6,T25,T26 |
OUTPUT |
intr_rx_frame_err_o |
Yes |
Yes |
T6,T329,T328 |
Yes |
T6,T329,T328 |
OUTPUT |
intr_rx_break_err_o |
Yes |
Yes |
T6,T329,T328 |
Yes |
T6,T329,T328 |
OUTPUT |
intr_rx_timeout_o |
Yes |
Yes |
T6,T329,T328 |
Yes |
T6,T329,T328 |
OUTPUT |
intr_rx_parity_err_o |
Yes |
Yes |
T6,T329,T328 |
Yes |
T6,T329,T328 |
OUTPUT |
*Tests covering at least one bit in the range