Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_fixed_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_usb_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host0_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host1_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_main_ni	Yes	Yes	T5,T16,T64	Yes	T4,T5,T6	INPUT
rst_fixed_ni	Yes	Yes	T5,T16,T64	Yes	T4,T5,T6	INPUT
rst_usb_ni	Yes	Yes	T5,T16,T64	Yes	T4,T5,T6	INPUT
rst_spi_host0_ni	Yes	Yes	T5,T16,T64	Yes	T4,T5,T6	INPUT
rst_spi_host1_ni	Yes	Yes	T5,T16,T64	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T81,T82,T134	Yes	T81,T82,T83	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T83,T255,T256	Yes	T83,T255,T256	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T41,T228,T91	Yes	T41,T228,T91	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T41,T228,T91	Yes	T41,T228,T91	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T60,T87,T88	Yes	T60,T87,T88	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T83,T257,T255	Yes	T83,T257,T255	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T41,T68,T200	Yes	T41,T68,T200	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T5,T16,T64	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T72,T74,T199	Yes	T72,T74,T199	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T16,T64	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T5,T16,T64	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T72,T74,T199	Yes	T72,T74,T199	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T5,T16,T64	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T72,T74,T199	Yes	T72,T74,T199	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T5,T16,T64	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T72,T74,T199	Yes	T72,T74,T199	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T72,T74,T199	Yes	T72,T74,T199	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T72,T74,T199	Yes	T72,T74,T199	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T72,*T74,*T199	Yes	T72,T74,T199	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T72,T74,T199	Yes	T72,T74,T199	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T5,T16,T64	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T81,T82,T134	Yes	T81,T82,T83	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	T82,*T83,*T134	Yes	T81,T82,T83	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T81,*T82,*T83	Yes	T81,T82,T83	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T5,T16,T64	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T84,T264,T265	Yes	T84,T264,T265	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T84,T264,T265	Yes	T84,T264,T265	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T84,T264,T265	Yes	T84,T264,T265	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T84,T264,T265	Yes	T84,T264,T265	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T84,T264,T265	Yes	T84,T264,T265	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T84,*T264,*T265	Yes	T84,T264,T265	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T84,T264,T265	Yes	T84,T264,T265	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T16,T64	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T84,T264,T265	Yes	T84,T264,T265	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T84,T264,T265	Yes	T84,T264,T265	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T5,T16,T64	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T84,*T264,*T265	Yes	T84,T264,T265	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T5,T16,T64	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T84,T264,T265	Yes	T84,T264,T265	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T16,T58,T53	Yes	T16,T58,T53	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T16,T53,T17	Yes	T16,T53,T17	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T81,*T82,*T83	Yes	T81,T82,T83	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T5,T16,T64	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T280,T61,T413	Yes	T280,T61,T413	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T280,T61,T413	Yes	T280,T61,T413	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T280,T61,T413	Yes	T280,T61,T413	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T81,*T82,*T83	Yes	T81,T82,T83	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T280,T61,T413	Yes	T280,T61,T413	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T280,T61,T413	Yes	T280,T61,T413	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T280,T413,T414	Yes	T280,T413,T414	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T81,T82,T83	Yes	T61,T62,T63	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T280,T413,T414	Yes	T280,T61,T413	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T82,*T134,*T135	Yes	T81,T82,T83	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T133	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T280,*T415,*T416	Yes	T280,T413,T414	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T280,T61,T413	Yes	T280,T61,T413	INPUT
tl_peri_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T60,T87,T88	Yes	T60,T87,T88	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_error	Yes	Yes	T200,T228,T91	Yes	T200,T228,T91	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T201,T249,T61	Yes	T201,T249,T61	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T201,T249,T61	Yes	T201,T249,T61	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T201,T249,T61	Yes	T201,T249,T61	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T201,T249,T61	Yes	T201,T249,T61	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T201,T249,T61	Yes	T201,T249,T61	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T201,T249,T61	Yes	T201,T249,T61	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T81,*T82,*T133	Yes	T81,T82,T133	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T22,T24,T204	Yes	T22,T24,T204	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T201,T249,T61	Yes	T201,T249,T61	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T201,T249,T61	Yes	T201,T249,T61	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T201,T391,T161	Yes	T201,T391,T161	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T201,T249,T391	Yes	T201,T249,T61	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T201,T391,T161	Yes	T201,T391,T161	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T82,T83,T133	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T82,*T134,*T135	Yes	T81,T82,T133	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T82,T83,T133	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T201,*T391,*T405	Yes	T201,T391,T405	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T201,T249,T61	Yes	T201,T249,T61	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T201,T43,T61	Yes	T201,T43,T61	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T201,T43,T61	Yes	T201,T43,T61	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T201,T43,T61	Yes	T201,T43,T61	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T201,T43,T61	Yes	T201,T43,T61	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T201,T43,T61	Yes	T201,T43,T61	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T201,T43,T61	Yes	T201,T43,T61	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T81,*T82,*T83	Yes	T81,T82,T83	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T82,T83,T133	Yes	T82,T83,T133	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T201,T43,T61	Yes	T201,T43,T61	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T201,T43,T61	Yes	T201,T43,T61	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T82,T83,T133	Yes	T82,T83,T133	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T201,T43,T391	Yes	T201,T43,T391	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T201,T43,T391	Yes	T201,T43,T61	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T201,T43,T391	Yes	T201,T43,T391	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T82,T83,T133	Yes	T81,T82,T83	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T82,*T83,*T133	Yes	T81,T82,T83	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T201,*T43,*T391	Yes	T201,T43,T391	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T201,T43,T61	Yes	T201,T43,T61	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T6,T201,T3	Yes	T6,T201,T3	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T6,T201,T3	Yes	T6,T201,T3	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T6,T201,T3	Yes	T6,T201,T3	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T6,T201,T3	Yes	T6,T201,T3	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T6,T201,T3	Yes	T6,T201,T3	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T6,T201,T3	Yes	T6,T201,T3	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T60,*T88,*T152	Yes	T60,T88,T152	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T6,T201,T3	Yes	T6,T201,T3	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T6,T201,T3	Yes	T6,T201,T3	INPUT
tl_usbdev_i.d_error	Yes	Yes	T82,T133,T134	Yes	T82,T83,T133	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T6,T201,T27	Yes	T6,T201,T27	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T201,T27	Yes	T6,T201,T27	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T6,T201,T3	Yes	T6,T201,T3	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T60,*T88,*T152	Yes	T60,T88,T152	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T6,*T201,*T3	Yes	T6,T201,T3	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T6,T201,T3	Yes	T6,T201,T3	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T88,*T81,*T82	Yes	T88,T81,T82	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T16,T64	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T5,T16,T64	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T88,*T82,*T134	Yes	T88,T81,T82	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T5,T16,T64	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T88,T81,T82	Yes	T88,T81,T82	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T88,T81,T82	Yes	T88,T81,T82	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T88,T81,T82	Yes	T88,T81,T82	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T88,T81,T82	Yes	T88,T81,T82	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T88,T81,T82	Yes	T88,T81,T82	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T88,T81,T82	Yes	T88,T81,T82	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T88,T81,T82	Yes	T88,T81,T82	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T88,T81,T82	Yes	T88,T81,T82	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T88,T81,T82	Yes	T88,T81,T82	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T88,T81,T82	Yes	T88,T81,T82	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T88,T81,T82	Yes	T88,T81,T82	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T88,T82,T83	Yes	T88,T81,T82	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T88,*T81,*T82	Yes	T88,T81,T82	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T88,T81,T82	Yes	T88,T81,T82	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T16,T64	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T81,*T82,*T83	Yes	T81,T82,T83	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_hmac_o.d_ready	Yes	Yes	T5,T16,T64	Yes	T4,T5,T6	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T16,T262,T53	Yes	T16,T262,T53	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T16,T262,T53	Yes	T16,T262,T53	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T16,T42,T262	Yes	T16,T42,T262	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T16,T262,T53	Yes	T16,T262,T53	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T16,T42,T262	Yes	T16,T42,T262	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T88,*T82,*T83	Yes	T88,T82,T83	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T114,T326,T313	Yes	T114,T326,T313	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T16,T42,T262	Yes	T16,T42,T262	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T16,T42,T262	Yes	T16,T42,T262	INPUT
tl_hmac_i.d_error	Yes	Yes	T82,T83,T133	Yes	T82,T83,T133	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T16,T42,T262	Yes	T16,T42,T262	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T16,T42,T262	Yes	T16,T42,T262	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T16,T262,T53	Yes	T16,T262,T53	INPUT
tl_hmac_i.d_sink	Yes	Yes	T82,T83,T133	Yes	T82,T83,T133	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T88,*T82,*T83	Yes	T88,T82,T83	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T82,T83,T133	Yes	T82,T83,T133	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T16,*T262,*T53	Yes	T16,T262,T53	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T16,T42,T262	Yes	T16,T42,T262	INPUT
tl_kmac_o.d_ready	Yes	Yes	T5,T16,T64	Yes	T4,T5,T6	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T454,T132,T229	Yes	T454,T132,T229	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T42,T454,T132	Yes	T42,T454,T132	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T42,T454,T132	Yes	T42,T454,T132	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T454,T132,T229	Yes	T454,T132,T229	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T42,T454,T132	Yes	T42,T454,T132	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T60,*T88,*T81	Yes	T60,T88,T81	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T454,T229,T105	Yes	T454,T229,T105	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T42,T454,T132	Yes	T42,T454,T132	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T42,T454,T132	Yes	T42,T454,T132	INPUT
tl_kmac_i.d_error	Yes	Yes	T81,T82,T83	Yes	T81,T82,T133	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T454,T132,T18	Yes	T454,T132,T18	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T454,T132,T18	Yes	T454,T132,T18	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T454,T132,T18	Yes	T454,T18,T229	INPUT
tl_kmac_i.d_sink	Yes	Yes	T81,T82,T134	Yes	T81,T82,T133	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T60,*T88,*T82	Yes	T60,T88,T81	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T133	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T454,*T132,*T18	Yes	T454,T18,T229	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T454,T132,T18	Yes	T454,T132,T18	INPUT
tl_aes_o.d_ready	Yes	Yes	T4,T5,T96	Yes	T4,T5,T6	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T4,T96,T122	Yes	T4,T96,T122	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T96,T122	Yes	T4,T96,T122	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T4,T96,T42	Yes	T4,T96,T42	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T4,T96,T122	Yes	T4,T96,T122	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T4,T96,T42	Yes	T4,T96,T42	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T81,*T82,*T83	Yes	T81,T82,T83	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T4,T96,T42	Yes	T4,T96,T42	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T4,T96,T42	Yes	T4,T96,T42	INPUT
tl_aes_i.d_error	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T4,T96,T42	Yes	T4,T96,T42	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T96,T122	Yes	T4,T96,T122	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T4,T96,T42	Yes	T4,T96,T42	INPUT
tl_aes_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T81,*T82,*T83	Yes	T81,T82,T83	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T4,*T96,*T42	Yes	T4,T96,T42	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T4,T96,T42	Yes	T4,T96,T42	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T88,*T81,*T82	Yes	T88,T81,T82	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T81,T82,T134	Yes	T81,T82,T134	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T4,T262,T132	Yes	T4,T262,T132	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T16	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T5,T16,T64	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T81,T82,T133	Yes	T81,T82,T83	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T88,*T82,*T83	Yes	T88,T81,T82	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T4,*T262,*T132	Yes	T4,T262,T53	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T4,T262,T132	Yes	T4,T262,T132	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T88,*T81,*T82	Yes	T88,T81,T82	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_error	Yes	Yes	T81,T82,T83	Yes	T81,T82,T133	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T4,T262,T132	Yes	T4,T262,T132	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T16	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T5,T16,T64	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_sink	Yes	Yes	T81,T82,T133	Yes	T81,T82,T83	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T88,*T81,*T82	Yes	T88,T81,T82	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T81,T82,T133	Yes	T81,T82,T83	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T4,*T262,*T132	Yes	T4,T262,T132	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T4,T262,T132	Yes	T4,T262,T132	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T4,T262,T132	Yes	T4,T262,T132	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T88,*T81,*T82	Yes	T88,T81,T82	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_error	Yes	Yes	T82,T134,T135	Yes	T81,T82,T134	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T4,T262,T132	Yes	T4,T262,T132	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T16	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T4,T5,T16	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_sink	Yes	Yes	T81,T82,T133	Yes	T81,T82,T133	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T88,*T82,*T134	Yes	T88,T81,T82	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T81,T82,T133	Yes	T81,T82,T83	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T4,*T262,*T132	Yes	T4,T262,T132	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn1_o.d_ready	Yes	Yes	T4,T5,T16	Yes	T4,T5,T6	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T4,T262,T132	Yes	T4,T262,T132	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T262,T132	Yes	T4,T262,T132	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T262,T132	Yes	T4,T262,T132	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T4,T262,T132	Yes	T4,T262,T132	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T4,T262,T132	Yes	T4,T262,T132	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T88,*T81,*T82	Yes	T88,T81,T82	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T82,T83,T133	Yes	T82,T83,T133	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T4,T262,T132	Yes	T4,T262,T132	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T4,T262,T132	Yes	T4,T262,T132	INPUT
tl_edn1_i.d_error	Yes	Yes	T81,T82,T83	Yes	T82,T83,T133	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T4,T262,T132	Yes	T4,T262,T132	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T262,T132	Yes	T4,T262,T132	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T4,T262,T132	Yes	T4,T262,T132	INPUT
tl_edn1_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T88,*T81,*T82	Yes	T88,T81,T82	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T4,*T262,*T132	Yes	T4,T262,T132	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T4,T262,T132	Yes	T4,T262,T132	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T5,T6,T16	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T15	Yes	T5,T6,T15	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T15	Yes	T5,T6,T15	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T15	Yes	T5,T6,T15	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T5,T6,T15	Yes	T5,T6,T15	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T5,T6,T15	Yes	T5,T6,T15	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T81,*T82,*T83	Yes	T81,T82,T83	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T5,T6,T15	Yes	T5,T6,T15	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T5,T6,T15	Yes	T5,T6,T15	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T15	Yes	T5,T6,T15	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T15	Yes	T5,T6,T15	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T5,T6,T15	Yes	T5,T6,T15	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T81,*T82,*T83	Yes	T81,T82,T83	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T15	Yes	T5,T6,T15	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T5,T6,T15	Yes	T5,T6,T15	INPUT
tl_otbn_o.d_ready	Yes	Yes	T5,T16,T64	Yes	T4,T5,T6	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T16,T53,T17	Yes	T16,T53,T17	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T16,T42,T53	Yes	T16,T42,T53	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T16,T42,T53	Yes	T16,T42,T53	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T16,T53,T17	Yes	T16,T53,T17	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T16,T42,T53	Yes	T16,T42,T53	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T60,*T87,*T205	Yes	T60,T87,T205	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T82,T83,T133	Yes	T82,T83,T133	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T16,T42,T53	Yes	T16,T42,T53	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T16,T42,T53	Yes	T16,T42,T53	INPUT
tl_otbn_i.d_error	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T16,T53,T17	Yes	T16,T53,T17	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T16,T42,T53	Yes	T16,T42,T53	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T16,T42,T53	Yes	T16,T42,T53	INPUT
tl_otbn_i.d_sink	Yes	Yes	T82,T83,T133	Yes	T81,T82,T133	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T60,*T87,*T205	Yes	T60,T87,T205	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T82,T83,T133	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T16,*T53,*T17	Yes	T16,T53,T17	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T16,T42,T53	Yes	T16,T42,T53	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T5,T16,T64	Yes	T4,T5,T6	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T53,T132,T18	Yes	T53,T132,T18	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T53,T132,T18	Yes	T53,T132,T18	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T53,T132,T18	Yes	T53,T132,T18	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T53,T132,T18	Yes	T53,T132,T18	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T53,T132,T18	Yes	T53,T132,T18	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T88,*T81,*T82	Yes	T88,T81,T82	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T53,T132,T18	Yes	T53,T132,T18	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T53,T132,T18	Yes	T53,T132,T18	INPUT
tl_keymgr_i.d_error	Yes	Yes	T81,T82,T133	Yes	T81,T82,T83	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T132,T18,T54	Yes	T132,T18,T54	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T53,T132,T18	Yes	T53,T132,T18	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T53,T132,T18	Yes	T53,T132,T18	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T88,*T81,*T82	Yes	T88,T81,T82	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T53,*T132,*T18	Yes	T53,T132,T18	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T53,T132,T18	Yes	T53,T132,T18	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T266,*T81,*T82	Yes	T266,T81,T82	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T5,T6,T16	Yes	T5,T6,T16	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T82,*T83,*T134	Yes	T266,T81,T82	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T5,T16,T64	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T16,T53,T17	Yes	T16,T53,T17	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T16,T53,T17	Yes	T16,T53,T17	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T16,T53,T17	Yes	T16,T53,T17	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T16,T53,T17	Yes	T16,T53,T17	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T16,T53,T17	Yes	T16,T53,T17	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T449,*T81,*T82	Yes	T449,T81,T82	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T16,T53,T17	Yes	T16,T53,T17	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T16,T53,T17	Yes	T16,T53,T17	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T182,T315,T316	Yes	T182,T315,T316	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T16,T17,T52	Yes	T16,T53,T17	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T16,T17,T52	Yes	T16,T53,T17	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T82,*T83,*T134	Yes	T449,T81,T82	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T82,T83,T133	Yes	T81,T82,T83	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T177,*T178,*T182	Yes	T450,T250,T177	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T16,T53,T17	Yes	T16,T53,T17	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T16,T64	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range