Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_peri_ni	Yes	Yes	T5,T16,T64	Yes	T4,T5,T6	INPUT
tl_main_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T60,T87,T88	Yes	T60,T87,T88	INPUT
tl_main_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_error	Yes	Yes	T200,T228,T91	Yes	T200,T228,T91	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T6,T16,T225	Yes	T6,T16,T225	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T6,T16,T225	Yes	T6,T16,T225	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T60,T87,T88	Yes	T60,T87,T88	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T6,T16,T225	Yes	T6,T16,T225	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T6,T16,T225	Yes	T6,T16,T225	INPUT
tl_uart0_i.d_error	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T6,T16,T225	Yes	T6,T16,T225	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T16,T225	Yes	T6,T16,T225	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T6,T16,T225	Yes	T6,T16,T225	INPUT
tl_uart0_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T60,*T88,*T266	Yes	T60,T88,T266	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T6,*T16,*T225	Yes	T6,T16,T225	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T6,T16,T225	Yes	T6,T16,T225	INPUT
tl_uart1_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T6,T108,T220	Yes	T6,T108,T220	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T6,T108,T220	Yes	T6,T108,T220	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T60,T87,T88	Yes	T60,T87,T88	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T6,T108,T249	Yes	T6,T108,T249	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T6,T108,T249	Yes	T6,T108,T249	INPUT
tl_uart1_i.d_error	Yes	Yes	T82,T83,T133	Yes	T82,T133,T134	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T6,T108,T220	Yes	T6,T108,T220	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T108,T249	Yes	T6,T108,T249	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T6,T108,T249	Yes	T6,T108,T249	INPUT
tl_uart1_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T60,*T88,*T152	Yes	T60,T88,T152	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T82,T83,T133	Yes	T81,T82,T83	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T6,*T108,*T220	Yes	T6,T108,T220	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T6,T108,T249	Yes	T6,T108,T249	INPUT
tl_uart2_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T6,T97,T156	Yes	T6,T97,T156	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T6,T97,T156	Yes	T6,T97,T156	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T60,T87,T88	Yes	T60,T87,T88	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T6,T97,T156	Yes	T6,T97,T156	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T6,T97,T156	Yes	T6,T97,T156	INPUT
tl_uart2_i.d_error	Yes	Yes	T82,T83,T134	Yes	T82,T83,T134	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T6,T97,T156	Yes	T6,T97,T156	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T97,T156	Yes	T6,T97,T156	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T6,T97,T156	Yes	T6,T97,T156	INPUT
tl_uart2_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T60,*T88,*T152	Yes	T60,T88,T152	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T81,T82,T133	Yes	T82,T133,T134	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T6,*T97,*T156	Yes	T6,T97,T156	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T6,T97,T156	Yes	T6,T97,T156	INPUT
tl_uart3_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T6,T25,T26	Yes	T6,T25,T26	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T6,T25,T26	Yes	T6,T25,T26	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T60,T87,T88	Yes	T60,T87,T88	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T6,T25,T26	Yes	T6,T25,T26	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T6,T25,T26	Yes	T6,T25,T26	INPUT
tl_uart3_i.d_error	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T6,T25,T26	Yes	T6,T25,T26	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T25,T26	Yes	T6,T25,T26	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T6,T25,T26	Yes	T6,T25,T26	INPUT
tl_uart3_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T60,*T88,*T152	Yes	T60,T88,T152	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T6,*T25,*T26	Yes	T6,T25,T26	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T6,T25,T26	Yes	T6,T25,T26	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T201,T262,T391	Yes	T201,T262,T391	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T201,T262,T391	Yes	T201,T262,T391	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T60,T87,T88	Yes	T60,T87,T88	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T201,T262,T249	Yes	T201,T262,T249	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T201,T262,T249	Yes	T201,T262,T249	INPUT
tl_i2c0_i.d_error	Yes	Yes	T82,T83,T133	Yes	T82,T83,T133	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T262,T330,T219	Yes	T262,T330,T219	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T201,T262,T249	Yes	T201,T262,T249	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T201,T262,T249	Yes	T201,T262,T249	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T82,T83,T133	Yes	T82,T83,T133	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T88,*T82,*T83	Yes	T88,T82,T83	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T82,T83,T133	Yes	T82,T83,T133	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T201,*T262,*T391	Yes	T201,T262,T391	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T201,T262,T249	Yes	T201,T262,T249	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T201,T262,T223	Yes	T201,T262,T223	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T201,T262,T223	Yes	T201,T262,T223	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T60,T87,T88	Yes	T60,T87,T88	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T201,T262,T249	Yes	T201,T262,T249	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T201,T262,T249	Yes	T201,T262,T249	INPUT
tl_i2c1_i.d_error	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T262,T223,T342	Yes	T262,T223,T342	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T201,T262,T249	Yes	T201,T262,T249	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T201,T262,T249	Yes	T201,T262,T249	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T88,*T82,*T83	Yes	T88,T81,T82	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T201,*T262,*T223	Yes	T201,T262,T223	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T201,T262,T249	Yes	T201,T262,T249	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T15,T201,T262	Yes	T15,T201,T262	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T15,T201,T262	Yes	T15,T201,T262	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T60,T87,T88	Yes	T60,T87,T88	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T15,T201,T262	Yes	T15,T201,T262	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T15,T201,T262	Yes	T15,T201,T262	INPUT
tl_i2c2_i.d_error	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T15,T262,T224	Yes	T15,T262,T224	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T15,T201,T262	Yes	T15,T201,T262	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T15,T201,T262	Yes	T15,T201,T262	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T88,*T81,*T82	Yes	T88,T81,T82	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T15,*T201,*T262	Yes	T15,T201,T262	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T15,T201,T262	Yes	T15,T201,T262	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T221,T222,T356	Yes	T221,T222,T356	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T221,T222,T356	Yes	T221,T222,T356	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T60,T87,T88	Yes	T60,T87,T88	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T221,T222,T61	Yes	T221,T222,T61	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T221,T222,T61	Yes	T221,T222,T61	INPUT
tl_pattgen_i.d_error	Yes	Yes	T82,T83,T133	Yes	T82,T83,T133	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T221,T222,T356	Yes	T221,T222,T356	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T221,T222,T356	Yes	T221,T222,T61	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T221,T222,T356	Yes	T221,T222,T61	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	*T60,T82,T83	Yes	T60,T81,T82	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T221,*T222,*T356	Yes	T221,T222,T356	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T221,T222,T61	Yes	T221,T222,T61	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T157,T259,T764	Yes	T157,T259,T764	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T157,T259,T764	Yes	T157,T259,T764	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T60,T87,T88	Yes	T60,T87,T88	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T61,T157,T259	Yes	T61,T157,T259	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T61,T157,T259	Yes	T61,T157,T259	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T81,T82,T133	Yes	T81,T82,T133	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T157,T259,T764	Yes	T157,T259,T764	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T157,T259,T764	Yes	T61,T157,T259	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T157,T259,T764	Yes	T61,T157,T259	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	*T82,*T83,*T134	Yes	T81,T82,T83	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T157,*T259,*T764	Yes	T157,T259,T764	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T61,T157,T259	Yes	T61,T157,T259	INPUT
tl_gpio_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T60,T87,T88	Yes	T60,T87,T88	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_gpio_i.d_error	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T262,T33,T330	Yes	T262,T33,T330	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T262,T33,T330	Yes	T262,T1,T33	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T262,T33,T330	Yes	T262,T1,T33	INPUT
tl_gpio_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T88,*T81,*T82	Yes	T88,T81,T82	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T5,*T16,*T64	Yes	T4,T5,T6	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T201,T49,T95	Yes	T201,T49,T95	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T201,T49,T95	Yes	T201,T49,T95	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T60,T87,T88	Yes	T60,T87,T88	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T201,T49,T95	Yes	T201,T49,T95	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T201,T49,T95	Yes	T201,T49,T95	INPUT
tl_spi_device_i.d_error	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T201,T49,T95	Yes	T201,T49,T95	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T201,T49,T95	Yes	T201,T49,T95	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T201,T49,T95	Yes	T201,T49,T95	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T82,T83,T133	Yes	T82,T83,T133	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T82,*T83,*T134	Yes	T81,T82,T83	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T82,T83,T133	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T201,*T49,*T95	Yes	T201,T49,T95	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T201,T49,T95	Yes	T201,T49,T95	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T260,T104,T261	Yes	T260,T104,T261	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T260,T104,T261	Yes	T260,T104,T261	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T60,T87,T88	Yes	T60,T87,T88	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T260,T104,T61	Yes	T260,T104,T61	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T260,T104,T61	Yes	T260,T104,T61	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T260,T104,T261	Yes	T260,T104,T261	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T260,T104,T261	Yes	T260,T104,T61	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T260,T104,T261	Yes	T260,T104,T61	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T82,*T83,*T134	Yes	T81,T82,T83	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T260,*T104,*T261	Yes	T260,T104,T261	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T260,T104,T61	Yes	T260,T104,T61	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T16,T64,T65	Yes	T16,T64,T65	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T16,T64,T65	Yes	T16,T64,T65	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T60,T87,T88	Yes	T60,T87,T88	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T16,T64,T65	Yes	T16,T64,T65	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T16,T64,T65	Yes	T16,T64,T65	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T16,T64,T65	Yes	T16,T64,T65	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T16,T64,T65	Yes	T16,T64,T65	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T16,T64,T65	Yes	T16,T64,T65	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T82,*T83,*T133	Yes	T81,T82,T83	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T16,*T64,*T65	Yes	T16,T64,T65	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T16,T64,T65	Yes	T16,T64,T65	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T60,T87,T88	Yes	T60,T87,T88	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T82,T83,T133	Yes	T82,T83,T133	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T16,T64	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T5,T16,T64	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T82,*T83,*T134	Yes	T81,T82,T83	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T97,T57,T42	Yes	T97,T57,T42	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T97,T57,T42	Yes	T97,T57,T42	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T60,T87,T88	Yes	T60,T87,T88	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T97,T57,T225	Yes	T97,T57,T225	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T16,T97	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T5,T16,T97	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T82,T83,T133	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T82,*T83,*T134	Yes	T85,T86,T770	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T97,*T57,*T42	Yes	T97,T57,T42	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T60,T87,T88	Yes	T60,T87,T88	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T60,*T82,*T83	Yes	T60,T81,T82	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T60,T87,T88	Yes	T60,T87,T88	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T85,*T86,*T60	Yes	T85,T86,T60	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T5,*T160,*T132	Yes	T5,T160,T132	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T60,T81,T82	Yes	T60,T81,T82	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T60,T81,T82	Yes	T60,T81,T82	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T60,T87,T88	Yes	T60,T87,T88	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T60,T81,T82	Yes	T60,T81,T82	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T16,T64	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T60,T82,T83	Yes	T60,T81,T82	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T60,T81,T82	Yes	T60,T81,T82	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T5,T16,T64	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T60,T82,T134	Yes	T60,T81,T82	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T81,T82,T133	Yes	T81,T82,T83	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T5,T16,T64	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T60,T81,T82	Yes	T60,T81,T82	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T16,T53,T17	Yes	T16,T53,T17	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T16,T53,T17	Yes	T16,T53,T17	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T60,T87,T88	Yes	T60,T87,T88	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T16,T53,T17	Yes	T16,T53,T17	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T16,T53,T17	Yes	T16,T53,T17	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T81,T82,T133	Yes	T81,T82,T133	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T16,T53,T17	Yes	T16,T53,T17	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T55,T56,T66	Yes	T55,T56,T66	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T16,T53,T17	Yes	T16,T53,T17	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T84,*T60,*T317	Yes	T84,T60,T317	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T133	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T53,T17	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T16,T53,T17	Yes	T16,T53,T17	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T60,T87,T88	Yes	T60,T87,T88	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T82,T83,T133	Yes	T82,T83,T133	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T64,T52,T278	Yes	T64,T52,T278	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T64,T52,T278	Yes	T64,T52,T278	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T5,T64,T41	Yes	T4,T5,T6	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T133	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T82,*T83,*T134	Yes	T81,T82,T83	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T82,T83,T133	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T5,*T64,*T41	Yes	T4,T5,T6	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T5,T16,T41	Yes	T5,T16,T41	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T5,T16,T41	Yes	T5,T16,T41	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T60,T87,T88	Yes	T60,T87,T88	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T5,T16,T41	Yes	T5,T16,T41	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T5,T16,T41	Yes	T5,T16,T41	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T81,T82,T133	Yes	T81,T82,T83	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T5,T41,T65	Yes	T5,T41,T65	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T16,T41	Yes	T5,T16,T41	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T5,T16,T41	Yes	T5,T16,T41	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T82,T83,T133	Yes	T81,T82,T83	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T82,*T83,*T134	Yes	T81,T82,T83	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T5,*T41,*T65	Yes	T5,T41,T65	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T5,T16,T41	Yes	T5,T16,T41	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T16,T53,T17	Yes	T16,T53,T17	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T16,T53,T17	Yes	T16,T53,T17	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T60,T87,T88	Yes	T60,T87,T88	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T16,T53,T17	Yes	T16,T53,T17	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T16,T53,T17	Yes	T16,T53,T17	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T177,T178,T179	Yes	T177,T178,T179	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T16,T17,T52	Yes	T16,T53,T17	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T16,T17,T52	Yes	T16,T53,T17	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T81,*T82,*T133	Yes	T81,T82,T83	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T177,*T178,*T179	Yes	T450,T177,T178	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T16,T53,T17	Yes	T16,T53,T17	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T5,T16,T64	Yes	T5,T16,T64	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T60,T87,T88	Yes	T60,T87,T88	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T16,T41	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T5,T64,T41	Yes	T5,T64,T41	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T16,T64	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T5,T64,T41	Yes	T5,T64,T41	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T87,*T266,*T205	Yes	T87,T266,T205	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T82,T83,T133	Yes	T82,T83,T133	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T5,T16,T41	Yes	T5,T16,T41	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T5,T16,T41	Yes	T5,T16,T41	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T60,T87,T88	Yes	T60,T87,T88	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T5,T16,T41	Yes	T5,T16,T41	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T5,T16,T41	Yes	T5,T16,T41	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T82,T83,T134	Yes	T81,T82,T83	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T5,T41,T65	Yes	T5,T41,T65	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T16,T41	Yes	T5,T16,T41	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T5,T16,T41	Yes	T5,T16,T41	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T82,*T83,*T134	Yes	T264,T266,T449	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T5,*T16,*T41	Yes	T5,T16,T41	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T5,T16,T41	Yes	T5,T16,T41	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T6,T68,T28	Yes	T6,T68,T28	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T6,T68,T28	Yes	T6,T68,T28	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T60,T87,T88	Yes	T60,T87,T88	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T6,T68,T28	Yes	T6,T68,T28	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T6,T68,T28	Yes	T6,T68,T28	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T82,T83,T133	Yes	T82,T83,T133	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T6,T68,T28	Yes	T6,T68,T28	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T68,T28	Yes	T6,T68,T28	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T68,T28,T103	Yes	T6,T68,T28	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T82,T83,T133	Yes	T82,T83,T133	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T60,*T88,*T152	Yes	T60,T88,T152	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T82,T133,T134	Yes	T82,T83,T133	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T6,*T68,*T28	Yes	T6,T68,T28	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T6,T68,T28	Yes	T6,T68,T28	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T262,T116,T117	Yes	T262,T116,T117	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T262,T116,T117	Yes	T262,T116,T117	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T60,T87,T88	Yes	T60,T87,T88	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T262,T116,T117	Yes	T262,T116,T117	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T262,T116,T117	Yes	T262,T116,T117	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T82,T83,T133	Yes	T81,T82,T83	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T262,T116,T117	Yes	T262,T116,T117	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T262,T116,T117	Yes	T262,T116,T117	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T116,T117,T8	Yes	T262,T116,T117	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T82,T83,T133	Yes	T81,T82,T83	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T82,*T83,*T133	Yes	T82,T83,T133	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T82,T83,T133	Yes	T82,T83,T133	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T262,*T116,*T117	Yes	T262,T116,T117	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T262,T116,T117	Yes	T262,T116,T117	INPUT
tl_ast_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T60,T87,T88	Yes	T60,T87,T88	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_ast_i.d_error	Yes	Yes	T82,T133,T134	Yes	T82,T83,T133	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T81,T82,T134	Yes	T81,T82,T83	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T16,T64	Yes	T4,T5,T6	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T5,T16,T64	Yes	T4,T5,T6	INPUT
tl_ast_i.d_sink	Yes	Yes	T81,T82,T133	Yes	T81,T82,T133	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	*T82,*T134,*T135	Yes	T82,T83,T134	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T82,T83,T134	Yes	T82,T134,T135	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T81,*T82,*T83	Yes	T81,T82,T134	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range