Unified Coverage Report :: Module :: prim_sync_reqack_data

Module : prim_sync_reqack_data

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data	100.00	100.00					100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.03	92.94	89.29	99.75		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	84.62			100.00	100.00	u_edn_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

Line Coverage for Module : prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Module : prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	1045780592	4427	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	1045780592	4427	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045780592	4427	0	0
T4	880922	1	0	0
T5	261894	4	0	0
T6	268510	2	0	0
T15	348510	2	0	0
T16	119109	14	0	0
T41	268135	4	0	0
T64	155389	4	0	0
T65	147327	2	0	0
T96	96467	1	0	0
T97	214515	1	0	0
T149	84827	0	0	0
T173	51213	0	0	0
T180	83868	8	0	0
T181	0	10	0	0
T183	0	8	0	0
T305	0	8	0	0
T306	0	8	0	0
T307	0	4	0	0
T308	253811	0	0	0
T309	88538	0	0	0
T310	93870	0	0	0
T311	420709	0	0	0
T312	116231	0	0	0
T313	103838	0	0	0
T314	273016	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045780592	4427	0	0
T4	880922	1	0	0
T5	261894	4	0	0
T6	268510	2	0	0
T15	348510	2	0	0
T16	119109	14	0	0
T41	268135	4	0	0
T64	155389	4	0	0
T65	147327	2	0	0
T96	96467	1	0	0
T97	214515	1	0	0
T149	84827	0	0	0
T173	51213	0	0	0
T180	83868	8	0	0
T181	0	10	0	0
T183	0	8	0	0
T305	0	8	0	0
T306	0	8	0	0
T307	0	4	0	0
T308	253811	0	0	0
T309	88538	0	0	0
T310	93870	0	0	0
T311	420709	0	0	0
T312	116231	0	0	0
T313	103838	0	0	0
T314	273016	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	522890296	46	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	522890296	46	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	46	0	0
T149	84827	0	0	0
T173	51213	0	0	0
T180	83868	8	0	0
T181	0	10	0	0
T183	0	8	0	0
T305	0	8	0	0
T306	0	8	0	0
T307	0	4	0	0
T308	253811	0	0	0
T309	88538	0	0	0
T310	93870	0	0	0
T311	420709	0	0	0
T312	116231	0	0	0
T313	103838	0	0	0
T314	273016	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	46	0	0
T149	84827	0	0	0
T173	51213	0	0	0
T180	83868	8	0	0
T181	0	10	0	0
T183	0	8	0	0
T305	0	8	0	0
T306	0	8	0	0
T307	0	4	0	0
T308	253811	0	0	0
T309	88538	0	0	0
T310	93870	0	0	0
T311	420709	0	0	0
T312	116231	0	0	0
T313	103838	0	0	0
T314	273016	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	522890296	4381	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	522890296	4381	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	4381	0	0
T4	880922	1	0	0
T5	261894	4	0	0
T6	268510	2	0	0
T15	348510	2	0	0
T16	119109	14	0	0
T41	268135	4	0	0
T64	155389	4	0	0
T65	147327	2	0	0
T96	96467	1	0	0
T97	214515	1	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	4381	0	0
T4	880922	1	0	0
T5	261894	4	0	0
T6	268510	2	0	0
T15	348510	2	0	0
T16	119109	14	0	0
T41	268135	4	0	0
T64	155389	4	0	0
T65	147327	2	0	0
T96	96467	1	0	0
T97	214515	1	0	0