Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_plic_target
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_plic_component_0.1/rtl/rv_plic_target.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target 100.00 100.00 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.49 89.34 76.61 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.26 99.65 66.67 100.00 100.00 90.00 u_rv_plic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_max_tree 91.46 89.27 76.58 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rv_plic_target
Line No.TotalCoveredPercent
TOTAL99100.00
CONT_ASSIGN5811100.00
CONT_ASSIGN5911100.00
ALWAYS6255100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_plic_component_0.1/rtl/rv_plic_target.sv' or '../src/lowrisc_ip_rv_plic_component_0.1/rtl/rv_plic_target.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
59 1 1
62 1 1
63 1 1
64 1 1
66 1 1
67 1 1
71 1 1
72 1 1


Cond Coverage for Module : rv_plic_target
TotalCoveredPercent
Conditions44100.00
Logical44100.00
Non-Logical00
Event00

 LINE       58
 EXPRESSION ((max_value > threshold_i) ? max_valid : 1'b0)
             ------------1------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T15

 LINE       59
 EXPRESSION (max_valid ? max_idx : '0)
             ----1----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T15

Branch Coverage for Module : rv_plic_target
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 58 2 2 100.00
TERNARY 59 2 2 100.00
IF 62 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_plic_component_0.1/rtl/rv_plic_target.sv' or '../src/lowrisc_ip_rv_plic_component_0.1/rtl/rv_plic_target.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 58 ((max_value > threshold_i)) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T15
0 Covered T4,T5,T6


LineNo. Expression -1-: 59 (max_valid) ?

Branches:
-1-StatusTests
1 Covered T5,T6,T15
0 Covered T4,T5,T6


LineNo. Expression -1-: 62 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%