Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rom_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.19 97.19

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rom_ctrl_0.1/rtl/rom_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rom_ctrl 99.89 99.89



Module Instance : tb.dut.top_earlgrey.u_rom_ctrl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.89 99.89


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.89 99.89


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : rom_ctrl
TotalCoveredPercent
Totals 66 60 90.91
Total Bits 2810 2731 97.19
Total Bits 0->1 1405 1366 97.22
Total Bits 1->0 1405 1365 97.15

Ports 66 60 90.91
Port Bits 2810 2731 97.19
Port Bits 0->1 1405 1366 97.22
Port Bits 1->0 1405 1365 97.15

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T5,T16,T64 Yes T4,T5,T6 INPUT
rom_cfg_i.cfg[3:0] No No No INPUT
rom_cfg_i.cfg_en No No No INPUT
rom_cfg_i.test No No No INPUT
rom_tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rom_tl_i.a_user.data_intg[6:0] Yes Yes T16,T58,T53 Yes T16,T58,T53 INPUT
rom_tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rom_tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rom_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
rom_tl_i.a_data[31:0] Yes Yes T16,T53,T17 Yes T16,T53,T17 INPUT
rom_tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rom_tl_i.a_address[15:0] Yes Yes *T81,*T82,*T83 Yes T81,T82,T83 INPUT
rom_tl_i.a_address[31:16] Unreachable Unreachable Unreachable INPUT
rom_tl_i.a_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
rom_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
rom_tl_i.a_size[1:0] Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
rom_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
rom_tl_i.a_opcode[2:0] Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
rom_tl_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rom_tl_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
rom_tl_o.d_error Yes Yes T81,T82,T83 Yes T81,T82,T83 OUTPUT
rom_tl_o.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
rom_tl_o.d_user.rsp_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
rom_tl_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
rom_tl_o.d_sink Yes Yes T81,T82,T83 Yes T81,T82,T83 OUTPUT
rom_tl_o.d_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
rom_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
rom_tl_o.d_size[1:0] Yes Yes T81,T82,T83 Yes T81,T82,T83 OUTPUT
rom_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
rom_tl_o.d_opcode[0] Yes Yes *T81,*T82,*T83 Yes T81,T82,T83 OUTPUT
rom_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
rom_tl_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
regs_tl_i.d_ready Yes Yes T5,T16,T64 Yes T4,T5,T6 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T61,T62,T63 Yes T61,T62,T63 INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T280,T61,T413 Yes T280,T61,T413 INPUT
regs_tl_i.a_user.instr_type[3:0] Yes Yes T280,T61,T413 Yes T280,T61,T413 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T61,T62,T63 Yes T61,T62,T63 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T280,T61,T413 Yes T280,T61,T413 INPUT
regs_tl_i.a_address[6:0] Yes Yes *T82,*T83,*T133 Yes T82,T83,T133 INPUT
regs_tl_i.a_address[16:7] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20:17] Yes Yes T280,T61,T413 Yes T280,T61,T413 INPUT
regs_tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[24] Yes Yes *T280,*T61,*T413 Yes T280,T61,T413 INPUT
regs_tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T280,*T61,*T413 Yes T280,T61,T413 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[5:0] Yes Yes *T81,*T82,*T83 Yes T81,T82,T83 INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[1:0] Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[2:0] Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
regs_tl_i.a_valid Yes Yes T280,T61,T413 Yes T280,T61,T413 INPUT
regs_tl_o.a_ready Yes Yes T280,T61,T413 Yes T280,T61,T413 OUTPUT
regs_tl_o.d_error Yes Yes T81,T82,T83 Yes T81,T82,T83 OUTPUT
regs_tl_o.d_user.data_intg[6:0] Yes Yes T280,T413,T414 Yes T280,T413,T414 OUTPUT
regs_tl_o.d_user.rsp_intg[6:0] Yes Yes T81,T82,T83 Yes T61,T62,T63 OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T280,T413,T414 Yes T280,T61,T413 OUTPUT
regs_tl_o.d_sink Yes Yes T81,T82,T83 Yes T81,T82,T83 OUTPUT
regs_tl_o.d_source[5:0] Yes Yes *T82,*T134,*T135 Yes T81,T82,T83 OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[1:0] Yes Yes T81,T82,T83 Yes T81,T82,T133 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T280,*T415,*T416 Yes T280,T413,T414 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T280,T61,T413 Yes T280,T61,T413 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T65,T89,T92 Yes T65,T89,T92 INPUT
alert_rx_i[0].ping_n Yes Yes T65,T89,T92 Yes T65,T89,T92 INPUT
alert_rx_i[0].ping_p Yes Yes T65,T89,T92 Yes T65,T89,T92 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T65,T89,T92 Yes T65,T89,T92 OUTPUT
pwrmgr_data_o.good[3:0] Yes Yes T4,T5,T6 Yes T5,T16,T64 OUTPUT
pwrmgr_data_o.done[3:0] Yes Yes T4,T5,T6 Yes T5,T16,T64 OUTPUT
keymgr_data_o.valid Yes Yes T5,T16,T64 Yes T4,T5,T6 OUTPUT
keymgr_data_o.data[255:0] Yes Yes T5,T16,T64 Yes T4,T5,T6 OUTPUT
kmac_data_i.error No No Yes T173,T174,T175 INPUT
kmac_data_i.digest_share1[383:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
kmac_data_i.digest_share0[383:0] Yes Yes T55,T56,T168 Yes T55,T56,T168 INPUT
kmac_data_i.done Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
kmac_data_i.ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
kmac_data_o.last Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
kmac_data_o.strb[7:0] No No No OUTPUT
kmac_data_o.data[38:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
kmac_data_o.data[63:39] No No No OUTPUT
kmac_data_o.valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rom_ctrl
TotalCoveredPercent
Totals 63 61 96.83
Total Bits 2734 2731 99.89
Total Bits 0->1 1367 1366 99.93
Total Bits 1->0 1367 1365 99.85

Ports 63 61 96.83
Port Bits 2734 2731 99.89
Port Bits 0->1 1367 1366 99.93
Port Bits 1->0 1367 1365 99.85

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T5,T16,T64 Yes T4,T5,T6 INPUT
rom_cfg_i.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
rom_cfg_i.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
rom_cfg_i.test No No No INPUT
rom_tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rom_tl_i.a_user.data_intg[6:0] Yes Yes T16,T58,T53 Yes T16,T58,T53 INPUT
rom_tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rom_tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rom_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
rom_tl_i.a_data[31:0] Yes Yes T16,T53,T17 Yes T16,T53,T17 INPUT
rom_tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rom_tl_i.a_address[15:0] Yes Yes *T81,*T82,*T83 Yes T81,T82,T83 INPUT
rom_tl_i.a_address[31:16] Unreachable Unreachable Unreachable INPUT
rom_tl_i.a_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
rom_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
rom_tl_i.a_size[1:0] Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
rom_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
rom_tl_i.a_opcode[2:0] Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
rom_tl_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rom_tl_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
rom_tl_o.d_error Yes Yes T81,T82,T83 Yes T81,T82,T83 OUTPUT
rom_tl_o.d_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
rom_tl_o.d_user.rsp_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
rom_tl_o.d_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
rom_tl_o.d_sink Yes Yes T81,T82,T83 Yes T81,T82,T83 OUTPUT
rom_tl_o.d_source[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
rom_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
rom_tl_o.d_size[1:0] Yes Yes T81,T82,T83 Yes T81,T82,T83 OUTPUT
rom_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
rom_tl_o.d_opcode[0] Yes Yes *T81,*T82,*T83 Yes T81,T82,T83 OUTPUT
rom_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
rom_tl_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
regs_tl_i.d_ready Yes Yes T5,T16,T64 Yes T4,T5,T6 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T61,T62,T63 Yes T61,T62,T63 INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T280,T61,T413 Yes T280,T61,T413 INPUT
regs_tl_i.a_user.instr_type[3:0] Yes Yes T280,T61,T413 Yes T280,T61,T413 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T61,T62,T63 Yes T61,T62,T63 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T280,T61,T413 Yes T280,T61,T413 INPUT
regs_tl_i.a_address[6:0] Yes Yes *T82,*T83,*T133 Yes T82,T83,T133 INPUT
regs_tl_i.a_address[16:7] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20:17] Yes Yes T280,T61,T413 Yes T280,T61,T413 INPUT
regs_tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[24] Yes Yes *T280,*T61,*T413 Yes T280,T61,T413 INPUT
regs_tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T280,*T61,*T413 Yes T280,T61,T413 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[5:0] Yes Yes *T81,*T82,*T83 Yes T81,T82,T83 INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[1:0] Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[2:0] Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
regs_tl_i.a_valid Yes Yes T280,T61,T413 Yes T280,T61,T413 INPUT
regs_tl_o.a_ready Yes Yes T280,T61,T413 Yes T280,T61,T413 OUTPUT
regs_tl_o.d_error Yes Yes T81,T82,T83 Yes T81,T82,T83 OUTPUT
regs_tl_o.d_user.data_intg[6:0] Yes Yes T280,T413,T414 Yes T280,T413,T414 OUTPUT
regs_tl_o.d_user.rsp_intg[6:0] Yes Yes T81,T82,T83 Yes T61,T62,T63 OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T280,T413,T414 Yes T280,T61,T413 OUTPUT
regs_tl_o.d_sink Yes Yes T81,T82,T83 Yes T81,T82,T83 OUTPUT
regs_tl_o.d_source[5:0] Yes Yes *T82,*T134,*T135 Yes T81,T82,T83 OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[1:0] Yes Yes T81,T82,T83 Yes T81,T82,T133 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T280,*T415,*T416 Yes T280,T413,T414 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T280,T61,T413 Yes T280,T61,T413 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T65,T89,T92 Yes T65,T89,T92 INPUT
alert_rx_i[0].ping_n Yes Yes T65,T89,T92 Yes T65,T89,T92 INPUT
alert_rx_i[0].ping_p Yes Yes T65,T89,T92 Yes T65,T89,T92 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T65,T89,T92 Yes T65,T89,T92 OUTPUT
pwrmgr_data_o.good[3:0] Yes Yes T4,T5,T6 Yes T5,T16,T64 OUTPUT
pwrmgr_data_o.done[3:0] Yes Yes T4,T5,T6 Yes T5,T16,T64 OUTPUT
keymgr_data_o.valid Yes Yes T5,T16,T64 Yes T4,T5,T6 OUTPUT
keymgr_data_o.data[255:0] Yes Yes T5,T16,T64 Yes T4,T5,T6 OUTPUT
kmac_data_i.error No No Yes T173,T174,T175 INPUT
kmac_data_i.digest_share1[383:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
kmac_data_i.digest_share0[383:0] Yes Yes T55,T56,T168 Yes T55,T56,T168 INPUT
kmac_data_i.done Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
kmac_data_i.ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
kmac_data_o.last Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
kmac_data_o.strb[7:0] Excluded Excluded Excluded OUTPUT [UNR] rom_ctrl -> KMAC app intf: Tied off data and strobe bits.
kmac_data_o.data[38:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
kmac_data_o.data[63:39] Excluded Excluded Excluded OUTPUT [UNR] rom_ctrl -> KMAC app intf: Tied off data and strobe bits.
kmac_data_o.valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%