Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T180,T183,T306
0	1	Covered	T180,T183,T306
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T180,T183,T306
1	Covered	T180,T183,T306

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T180,T183,T306
1	Covered	T180,T183,T306

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T180,T183,T306
1	1	Covered	T180,T183,T306

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T180,T183,T306
1	0	Covered	T180,T183,T306
1	1	Covered	T180,T183,T306

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T180,T183,T306

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T180,T183,T306
0	Covered	T180,T183,T306

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T180,T183,T306
0	Covered	T180,T183,T306

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1045780592	1031390786	0	0
CheckNGreaterZero_A	2044	2044	0	0
GntImpliesReady_A	1045780592	8382	0	0
GntImpliesValid_A	1045780592	8382	0	0
GrantKnown_A	1045780592	1031390786	0	0
IdxKnown_A	1045780592	1031390786	0	0
IndexIsCorrect_A	1045780592	8382	0	0
NoReadyValidNoGrant_A	1045780592	0	0	0
Priority_A	1045780592	8382	0	0
ReadyAndValidImplyGrant_A	1045780592	8382	0	0
ReqAndReadyImplyGrant_A	1045780592	8382	0	0
ReqImpliesValid_A	1045780592	8382	0	0
ValidKnown_A	1045780592	1031390786	0	0
gen_data_port_assertion.DataFlow_A	1045780592	8382	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045780592	1031390786	0	0
T4	1761844	1761720	0	0
T5	523788	523584	0	0
T6	537020	536910	0	0
T15	697020	696910	0	0
T16	238218	238208	0	0
T41	536270	536044	0	0
T64	310778	310568	0	0
T65	294654	294530	0	0
T96	192934	192832	0	0
T97	429030	428928	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2044	2044	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T15	2	2	0	0
T16	2	2	0	0
T41	2	2	0	0
T64	2	2	0	0
T65	2	2	0	0
T96	2	2	0	0
T97	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045780592	8382	0	0
T149	169654	0	0	0
T173	102426	0	0	0
T180	167736	2795	0	0
T183	0	2794	0	0
T306	0	2793	0	0
T308	507622	0	0	0
T309	177076	0	0	0
T310	187740	0	0	0
T311	841418	0	0	0
T312	232462	0	0	0
T313	207676	0	0	0
T314	546032	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045780592	8382	0	0
T149	169654	0	0	0
T173	102426	0	0	0
T180	167736	2795	0	0
T183	0	2794	0	0
T306	0	2793	0	0
T308	507622	0	0	0
T309	177076	0	0	0
T310	187740	0	0	0
T311	841418	0	0	0
T312	232462	0	0	0
T313	207676	0	0	0
T314	546032	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045780592	1031390786	0	0
T4	1761844	1761720	0	0
T5	523788	523584	0	0
T6	537020	536910	0	0
T15	697020	696910	0	0
T16	238218	238208	0	0
T41	536270	536044	0	0
T64	310778	310568	0	0
T65	294654	294530	0	0
T96	192934	192832	0	0
T97	429030	428928	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045780592	1031390786	0	0
T4	1761844	1761720	0	0
T5	523788	523584	0	0
T6	537020	536910	0	0
T15	697020	696910	0	0
T16	238218	238208	0	0
T41	536270	536044	0	0
T64	310778	310568	0	0
T65	294654	294530	0	0
T96	192934	192832	0	0
T97	429030	428928	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045780592	8382	0	0
T149	169654	0	0	0
T173	102426	0	0	0
T180	167736	2795	0	0
T183	0	2794	0	0
T306	0	2793	0	0
T308	507622	0	0	0
T309	177076	0	0	0
T310	187740	0	0	0
T311	841418	0	0	0
T312	232462	0	0	0
T313	207676	0	0	0
T314	546032	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045780592	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045780592	8382	0	0
T149	169654	0	0	0
T173	102426	0	0	0
T180	167736	2795	0	0
T183	0	2794	0	0
T306	0	2793	0	0
T308	507622	0	0	0
T309	177076	0	0	0
T310	187740	0	0	0
T311	841418	0	0	0
T312	232462	0	0	0
T313	207676	0	0	0
T314	546032	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045780592	8382	0	0
T149	169654	0	0	0
T173	102426	0	0	0
T180	167736	2795	0	0
T183	0	2794	0	0
T306	0	2793	0	0
T308	507622	0	0	0
T309	177076	0	0	0
T310	187740	0	0	0
T311	841418	0	0	0
T312	232462	0	0	0
T313	207676	0	0	0
T314	546032	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045780592	8382	0	0
T149	169654	0	0	0
T173	102426	0	0	0
T180	167736	2795	0	0
T183	0	2794	0	0
T306	0	2793	0	0
T308	507622	0	0	0
T309	177076	0	0	0
T310	187740	0	0	0
T311	841418	0	0	0
T312	232462	0	0	0
T313	207676	0	0	0
T314	546032	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045780592	8382	0	0
T149	169654	0	0	0
T173	102426	0	0	0
T180	167736	2795	0	0
T183	0	2794	0	0
T306	0	2793	0	0
T308	507622	0	0	0
T309	177076	0	0	0
T310	187740	0	0	0
T311	841418	0	0	0
T312	232462	0	0	0
T313	207676	0	0	0
T314	546032	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045780592	1031390786	0	0
T4	1761844	1761720	0	0
T5	523788	523584	0	0
T6	537020	536910	0	0
T15	697020	696910	0	0
T16	238218	238208	0	0
T41	536270	536044	0	0
T64	310778	310568	0	0
T65	294654	294530	0	0
T96	192934	192832	0	0
T97	429030	428928	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1045780592	8382	0	0
T149	169654	0	0	0
T173	102426	0	0	0
T180	167736	2795	0	0
T183	0	2794	0	0
T306	0	2793	0	0
T308	507622	0	0	0
T309	177076	0	0	0
T310	187740	0	0	0
T311	841418	0	0	0
T312	232462	0	0	0
T313	207676	0	0	0
T314	546032	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T180,T183,T306
0	1	Covered	T180,T183,T306
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T180,T183,T306
1	Covered	T180,T183,T306

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T180,T183,T306
1	Covered	T180,T183,T306

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T180,T183,T306
1	1	Covered	T180,T183,T306

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T180,T183,T306
1	0	Covered	T180,T183,T306
1	1	Covered	T180,T183,T306

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T180,T183,T306

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T180,T183,T306
0	Covered	T180,T183,T306

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T180,T183,T306
0	Covered	T180,T183,T306

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	522890296	515695393	0	0
CheckNGreaterZero_A	1022	1022	0	0
GntImpliesReady_A	522890296	5194	0	0
GntImpliesValid_A	522890296	5194	0	0
GrantKnown_A	522890296	515695393	0	0
IdxKnown_A	522890296	515695393	0	0
IndexIsCorrect_A	522890296	5194	0	0
NoReadyValidNoGrant_A	522890296	0	0	0
Priority_A	522890296	5194	0	0
ReadyAndValidImplyGrant_A	522890296	5194	0	0
ReqAndReadyImplyGrant_A	522890296	5194	0	0
ReqImpliesValid_A	522890296	5194	0	0
ValidKnown_A	522890296	515695393	0	0
gen_data_port_assertion.DataFlow_A	522890296	5194	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	515695393	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T41	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T96	1	1	0	0
T97	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	5194	0	0
T149	84827	0	0	0
T173	51213	0	0	0
T180	83868	1732	0	0
T183	0	1732	0	0
T306	0	1730	0	0
T308	253811	0	0	0
T309	88538	0	0	0
T310	93870	0	0	0
T311	420709	0	0	0
T312	116231	0	0	0
T313	103838	0	0	0
T314	273016	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	5194	0	0
T149	84827	0	0	0
T173	51213	0	0	0
T180	83868	1732	0	0
T183	0	1732	0	0
T306	0	1730	0	0
T308	253811	0	0	0
T309	88538	0	0	0
T310	93870	0	0	0
T311	420709	0	0	0
T312	116231	0	0	0
T313	103838	0	0	0
T314	273016	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	515695393	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	515695393	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	5194	0	0
T149	84827	0	0	0
T173	51213	0	0	0
T180	83868	1732	0	0
T183	0	1732	0	0
T306	0	1730	0	0
T308	253811	0	0	0
T309	88538	0	0	0
T310	93870	0	0	0
T311	420709	0	0	0
T312	116231	0	0	0
T313	103838	0	0	0
T314	273016	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	5194	0	0
T149	84827	0	0	0
T173	51213	0	0	0
T180	83868	1732	0	0
T183	0	1732	0	0
T306	0	1730	0	0
T308	253811	0	0	0
T309	88538	0	0	0
T310	93870	0	0	0
T311	420709	0	0	0
T312	116231	0	0	0
T313	103838	0	0	0
T314	273016	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	5194	0	0
T149	84827	0	0	0
T173	51213	0	0	0
T180	83868	1732	0	0
T183	0	1732	0	0
T306	0	1730	0	0
T308	253811	0	0	0
T309	88538	0	0	0
T310	93870	0	0	0
T311	420709	0	0	0
T312	116231	0	0	0
T313	103838	0	0	0
T314	273016	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	5194	0	0
T149	84827	0	0	0
T173	51213	0	0	0
T180	83868	1732	0	0
T183	0	1732	0	0
T306	0	1730	0	0
T308	253811	0	0	0
T309	88538	0	0	0
T310	93870	0	0	0
T311	420709	0	0	0
T312	116231	0	0	0
T313	103838	0	0	0
T314	273016	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	5194	0	0
T149	84827	0	0	0
T173	51213	0	0	0
T180	83868	1732	0	0
T183	0	1732	0	0
T306	0	1730	0	0
T308	253811	0	0	0
T309	88538	0	0	0
T310	93870	0	0	0
T311	420709	0	0	0
T312	116231	0	0	0
T313	103838	0	0	0
T314	273016	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	515695393	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	5194	0	0
T149	84827	0	0	0
T173	51213	0	0	0
T180	83868	1732	0	0
T183	0	1732	0	0
T306	0	1730	0	0
T308	253811	0	0	0
T309	88538	0	0	0
T310	93870	0	0	0
T311	420709	0	0	0
T312	116231	0	0	0
T313	103838	0	0	0
T314	273016	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T180,T183,T306
0	1	Covered	T180,T183,T306
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T180,T183,T306
1	Covered	T180,T183,T306

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T180,T183,T306
1	Covered	T180,T183,T306

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T180,T183,T306
1	1	Covered	T180,T183,T306

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T180,T183,T306
1	0	Covered	T180,T183,T306
1	1	Covered	T180,T183,T306

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T180,T183,T306

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T180,T183,T306
0	Covered	T180,T183,T306

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T180,T183,T306
0	Covered	T180,T183,T306

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	522890296	515695393	0	0
CheckNGreaterZero_A	1022	1022	0	0
GntImpliesReady_A	522890296	3188	0	0
GntImpliesValid_A	522890296	3188	0	0
GrantKnown_A	522890296	515695393	0	0
IdxKnown_A	522890296	515695393	0	0
IndexIsCorrect_A	522890296	3188	0	0
NoReadyValidNoGrant_A	522890296	0	0	0
Priority_A	522890296	3188	0	0
ReadyAndValidImplyGrant_A	522890296	3188	0	0
ReqAndReadyImplyGrant_A	522890296	3188	0	0
ReqImpliesValid_A	522890296	3188	0	0
ValidKnown_A	522890296	515695393	0	0
gen_data_port_assertion.DataFlow_A	522890296	3188	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	515695393	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T41	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T96	1	1	0	0
T97	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	3188	0	0
T149	84827	0	0	0
T173	51213	0	0	0
T180	83868	1063	0	0
T183	0	1062	0	0
T306	0	1063	0	0
T308	253811	0	0	0
T309	88538	0	0	0
T310	93870	0	0	0
T311	420709	0	0	0
T312	116231	0	0	0
T313	103838	0	0	0
T314	273016	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	3188	0	0
T149	84827	0	0	0
T173	51213	0	0	0
T180	83868	1063	0	0
T183	0	1062	0	0
T306	0	1063	0	0
T308	253811	0	0	0
T309	88538	0	0	0
T310	93870	0	0	0
T311	420709	0	0	0
T312	116231	0	0	0
T313	103838	0	0	0
T314	273016	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	515695393	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	515695393	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	3188	0	0
T149	84827	0	0	0
T173	51213	0	0	0
T180	83868	1063	0	0
T183	0	1062	0	0
T306	0	1063	0	0
T308	253811	0	0	0
T309	88538	0	0	0
T310	93870	0	0	0
T311	420709	0	0	0
T312	116231	0	0	0
T313	103838	0	0	0
T314	273016	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	3188	0	0
T149	84827	0	0	0
T173	51213	0	0	0
T180	83868	1063	0	0
T183	0	1062	0	0
T306	0	1063	0	0
T308	253811	0	0	0
T309	88538	0	0	0
T310	93870	0	0	0
T311	420709	0	0	0
T312	116231	0	0	0
T313	103838	0	0	0
T314	273016	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	3188	0	0
T149	84827	0	0	0
T173	51213	0	0	0
T180	83868	1063	0	0
T183	0	1062	0	0
T306	0	1063	0	0
T308	253811	0	0	0
T309	88538	0	0	0
T310	93870	0	0	0
T311	420709	0	0	0
T312	116231	0	0	0
T313	103838	0	0	0
T314	273016	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	3188	0	0
T149	84827	0	0	0
T173	51213	0	0	0
T180	83868	1063	0	0
T183	0	1062	0	0
T306	0	1063	0	0
T308	253811	0	0	0
T309	88538	0	0	0
T310	93870	0	0	0
T311	420709	0	0	0
T312	116231	0	0	0
T313	103838	0	0	0
T314	273016	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	3188	0	0
T149	84827	0	0	0
T173	51213	0	0	0
T180	83868	1063	0	0
T183	0	1062	0	0
T306	0	1063	0	0
T308	253811	0	0	0
T309	88538	0	0	0
T310	93870	0	0	0
T311	420709	0	0	0
T312	116231	0	0	0
T313	103838	0	0	0
T314	273016	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	515695393	0	0
T4	880922	880860	0	0
T5	261894	261792	0	0
T6	268510	268455	0	0
T15	348510	348455	0	0
T16	119109	119104	0	0
T41	268135	268022	0	0
T64	155389	155284	0	0
T65	147327	147265	0	0
T96	96467	96416	0	0
T97	214515	214464	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522890296	3188	0	0
T149	84827	0	0	0
T173	51213	0	0	0
T180	83868	1063	0	0
T183	0	1062	0	0
T306	0	1063	0	0
T308	253811	0	0	0
T309	88538	0	0	0
T310	93870	0	0	0
T311	420709	0	0	0
T312	116231	0	0	0
T313	103838	0	0	0
T314	273016	0	0	0