Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : edn
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.34 99.34

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_edn1 99.02 99.02
tb.dut.top_earlgrey.u_edn0 99.25 99.25


Module Instance : tb.dut.top_earlgrey.u_edn1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.02 99.02


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.02 99.02


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_edn0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.25 99.25


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.25 99.25


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : edn
TotalCoveredPercent
Totals 78 75 96.15
Total Bits 1210 1202 99.34
Total Bits 0->1 605 602 99.50
Total Bits 1->0 605 600 99.17

Ports 78 75 96.15
Port Bits 1210 1202 99.34
Port Bits 0->1 605 602 99.50
Port Bits 1->0 605 600 99.17

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T5,T16,T64 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T4,T262,T132 Yes T4,T262,T132 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T4,T262,T132 Yes T4,T262,T132 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[6:0] Yes Yes *T82,*T83,*T133 Yes T82,T83,T133 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:16] Yes Yes T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T88,*T81,*T82 Yes T88,T81,T82 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
tl_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_error Yes Yes T81,T82,T83 Yes T81,T82,T83 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T4,T262,T132 Yes T4,T262,T132 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T4,T5,T16 Yes T4,T5,T6 OUTPUT
tl_o.d_data[31:0] Yes Yes T4,T5,T16 Yes T4,T5,T6 OUTPUT
tl_o.d_sink Yes Yes T81,T82,T83 Yes T81,T82,T83 OUTPUT
tl_o.d_source[5:0] Yes Yes *T88,*T81,*T82 Yes T88,T81,T82 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T81,T82,T83 Yes T81,T82,T83 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T4,*T262,*T132 Yes T4,T262,T132 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_i[0].edn_req Yes Yes T132,T18,T54 Yes T132,T18,T54 INPUT
edn_i[1].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i[2].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i[3].edn_req Yes Yes T122,T455,T456 Yes T122,T455,T456 INPUT
edn_i[4].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i[5].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i[6].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i[7].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T132,T18,T54 Yes T132,T18,T54 OUTPUT
edn_o[0].edn_fips Yes Yes T115,T129,T130 Yes T132,T122,T229 OUTPUT
edn_o[0].edn_ack Yes Yes T132,T18,T54 Yes T132,T18,T54 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[1].edn_fips No No Yes T158,T123,T159 OUTPUT
edn_o[1].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T4,T96,T16 Yes T4,T6,T96 OUTPUT
edn_o[2].edn_fips Yes Yes T119,T120,T121 Yes T122,T123,T119 OUTPUT
edn_o[2].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T122,T455,T456 Yes T122,T455,T456 OUTPUT
edn_o[3].edn_fips No No Yes T122,T455,T457 OUTPUT
edn_o[3].edn_ack Yes Yes T122,T455,T456 Yes T122,T455,T456 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T4,T5,T16 Yes T4,T5,T96 OUTPUT
edn_o[4].edn_fips Yes Yes T728 Yes T115,T119,T729 OUTPUT
edn_o[4].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[5].edn_fips Yes Yes T115,T119,T727 Yes T4,T122,T115 OUTPUT
edn_o[5].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[6].edn_fips Yes Yes T115,T129,T130 Yes T122,T230,T115 OUTPUT
edn_o[6].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T16,T41,T42 Yes T6,T16,T97 OUTPUT
edn_o[7].edn_fips Yes Yes T115,T129,T130 Yes T122,T115,T129 OUTPUT
edn_o[7].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T4,T5,T16 Yes T4,T5,T6 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
csrng_cmd_i.genbits_fips Yes Yes T129,T130,T120 Yes T4,T132,T122 INPUT
csrng_cmd_i.genbits_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T115,T119,T725 Yes T115,T119,T725 INPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T89,T92,T94 Yes T89,T92,T94 INPUT
alert_rx_i[0].ping_n Yes Yes T89,T92,T94 Yes T89,T92,T94 INPUT
alert_rx_i[0].ping_p Yes Yes T89,T92,T94 Yes T89,T92,T94 INPUT
alert_rx_i[1].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[1].ack_p Yes Yes T89,T92,T94 Yes T89,T92,T94 INPUT
alert_rx_i[1].ping_n Yes Yes T89,T92,T94 Yes T89,T92,T94 INPUT
alert_rx_i[1].ping_p Yes Yes T89,T92,T94 Yes T89,T92,T94 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T89,T92,T94 Yes T89,T92,T94 OUTPUT
alert_tx_o[1].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[1].alert_p Yes Yes T89,T92,T94 Yes T89,T92,T94 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T262,T330,T334 Yes T262,T330,T334 OUTPUT
intr_edn_fatal_err_o Yes Yes T262,T330,T331 Yes T262,T330,T331 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn1
TotalCoveredPercent
Totals 50 48 96.00
Total Bits 714 707 99.02
Total Bits 0->1 357 354 99.16
Total Bits 1->0 357 353 98.88

Ports 50 48 96.00
Port Bits 714 707 99.02
Port Bits 0->1 357 354 99.16
Port Bits 1->0 357 353 98.88

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T5,T16,T64 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T16 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T4,T262,T132 Yes T4,T262,T132 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T262,T132 Yes T4,T262,T132 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T262,T132 Yes T4,T262,T132 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T4,T262,T132 Yes T4,T262,T132 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T262,T132 Yes T4,T262,T132 INPUT
tl_i.a_address[6:0] Yes Yes *T82,*T83,*T133 Yes T82,T83,T133 INPUT
tl_i.a_address[18:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:19] Yes Yes T4,T262,T132 Yes T4,T262,T132 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T4,*T262,*T132 Yes T4,T262,T132 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T262,*T132 Yes T4,T262,T132 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T88,*T81,*T82 Yes T88,T81,T82 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T82,T83,T133 Yes T82,T83,T133 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
tl_i.a_valid Yes Yes T4,T262,T132 Yes T4,T262,T132 INPUT
tl_o.a_ready Yes Yes T4,T262,T132 Yes T4,T262,T132 OUTPUT
tl_o.d_error Yes Yes T81,T82,T83 Yes T82,T83,T133 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T4,T262,T132 Yes T4,T262,T132 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T4,T262,T132 Yes T4,T262,T132 OUTPUT
tl_o.d_data[31:0] Yes Yes T4,T262,T132 Yes T4,T262,T132 OUTPUT
tl_o.d_sink Yes Yes T81,T82,T83 Yes T81,T82,T83 OUTPUT
tl_o.d_source[5:0] Yes Yes *T88,*T81,*T82 Yes T88,T81,T82 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T81,T82,T83 Yes T81,T82,T83 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T4,*T262,*T132 Yes T4,T262,T132 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T4,T262,T132 Yes T4,T262,T132 OUTPUT
edn_i[0].edn_req Yes Yes T122,T115,T158 Yes T122,T115,T158 INPUT
edn_i[1].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[2].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[3].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[4].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[5].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[6].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[7].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_o[0].edn_bus[31:0] Yes Yes T122,T115,T158 Yes T122,T115,T158 OUTPUT
edn_o[0].edn_fips Yes Yes T115,T129,T130 Yes T122,T115,T158 OUTPUT
edn_o[0].edn_ack Yes Yes T122,T115,T158 Yes T122,T115,T158 OUTPUT
edn_o[1].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
csrng_cmd_o.genbits_ready Yes Yes T4,T132,T122 Yes T4,T132,T122 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T122,T115,T158 Yes T4,T132,T122 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T4,T132,T122 Yes T4,T132,T122 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T132,T122,T229 Yes T122,T230,T115 INPUT
csrng_cmd_i.genbits_fips No No Yes T129,T130,T726 INPUT
csrng_cmd_i.genbits_valid Yes Yes T4,T132,T122 Yes T4,T132,T122 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T4,T132,T122 Yes T4,T132,T122 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T115,T119,T727 Yes T115,T119,T727 INPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T89,T92,T94 Yes T89,T92,T94 INPUT
alert_rx_i[0].ping_n Yes Yes T89,T92,T94 Yes T89,T92,T94 INPUT
alert_rx_i[0].ping_p Yes Yes T89,T92,T94 Yes T89,T92,T94 INPUT
alert_rx_i[1].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[1].ack_p Yes Yes T89,T92,T94 Yes T89,T92,T94 INPUT
alert_rx_i[1].ping_n Yes Yes T89,T92,T94 Yes T89,T92,T94 INPUT
alert_rx_i[1].ping_p Yes Yes T89,T92,T94 Yes T89,T92,T94 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T89,T92,T94 Yes T89,T92,T94 OUTPUT
alert_tx_o[1].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[1].alert_p Yes Yes T89,T92,T94 Yes T89,T92,T94 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T262,T330,T334 Yes T262,T330,T334 OUTPUT
intr_edn_fatal_err_o Yes Yes T262,T330,T331 Yes T262,T330,T331 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn0
TotalCoveredPercent
Totals 78 74 94.87
Total Bits 1208 1199 99.25
Total Bits 0->1 604 601 99.50
Total Bits 1->0 604 598 99.01

Ports 78 74 94.87
Port Bits 1208 1199 99.25
Port Bits 0->1 604 601 99.50
Port Bits 1->0 604 598 99.01

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T5,T16,T64 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T4,T262,T132 Yes T4,T262,T132 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T4,T262,T132 Yes T4,T262,T132 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[6:0] Yes Yes *T82,*T83,*T133 Yes T82,T83,T133 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18:16] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T88,*T81,*T82 Yes T88,T81,T82 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T81,T82,T83 Yes T81,T82,T83 INPUT
tl_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_error Yes Yes T82,T134,T135 Yes T81,T82,T134 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T4,T262,T132 Yes T4,T262,T132 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T4,T5,T16 Yes T4,T5,T6 OUTPUT
tl_o.d_data[31:0] Yes Yes T4,T5,T16 Yes T4,T5,T6 OUTPUT
tl_o.d_sink Yes Yes T81,T82,T133 Yes T81,T82,T133 OUTPUT
tl_o.d_source[5:0] Yes Yes *T88,*T82,*T134 Yes T88,T81,T82 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T81,T82,T133 Yes T81,T82,T83 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T4,*T262,*T132 Yes T4,T262,T132 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_i[0].edn_req Yes Yes T132,T18,T54 Yes T132,T18,T54 INPUT
edn_i[1].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i[2].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i[3].edn_req Yes Yes T122,T455,T456 Yes T122,T455,T456 INPUT
edn_i[4].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i[5].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i[6].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_i[7].edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T132,T18,T54 Yes T132,T18,T54 OUTPUT
edn_o[0].edn_fips No No Yes T132,T122,T229 OUTPUT
edn_o[0].edn_ack Yes Yes T132,T18,T54 Yes T132,T18,T54 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[1].edn_fips No No Yes T158,T123,T159 OUTPUT
edn_o[1].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T4,T96,T16 Yes T4,T6,T96 OUTPUT
edn_o[2].edn_fips Yes Yes T119,T120,T121 Yes T122,T123,T119 OUTPUT
edn_o[2].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T122,T455,T456 Yes T122,T455,T456 OUTPUT
edn_o[3].edn_fips No No Yes T122,T455,T457 OUTPUT
edn_o[3].edn_ack Yes Yes T122,T455,T456 Yes T122,T455,T456 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T4,T5,T16 Yes T4,T5,T96 OUTPUT
edn_o[4].edn_fips Yes Yes T728 Yes T115,T119,T729 OUTPUT
edn_o[4].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[5].edn_fips Yes Yes T115,T119,T727 Yes T4,T122,T115 OUTPUT
edn_o[5].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[6].edn_fips Yes Yes T115,T129,T130 Yes T122,T230,T115 OUTPUT
edn_o[6].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T16,T41,T42 Yes T6,T16,T97 OUTPUT
edn_o[7].edn_fips Yes Yes T115,T129,T130 Yes T122,T115,T129 OUTPUT
edn_o[7].edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T4,T5,T16 Yes T4,T5,T6 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
csrng_cmd_i.genbits_fips Yes Yes T129,T130,T120 Yes T4,T132,T122 INPUT
csrng_cmd_i.genbits_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T115,T119,T725 Yes T115,T119,T725 INPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T89,T92,T94 Yes T89,T92,T94 INPUT
alert_rx_i[0].ping_n Yes Yes T89,T92,T94 Yes T89,T92,T94 INPUT
alert_rx_i[0].ping_p Yes Yes T89,T92,T94 Yes T89,T92,T94 INPUT
alert_rx_i[1].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[1].ack_p Yes Yes T89,T92,T94 Yes T89,T92,T94 INPUT
alert_rx_i[1].ping_n Yes Yes T89,T92,T94 Yes T89,T92,T94 INPUT
alert_rx_i[1].ping_p Yes Yes T89,T92,T94 Yes T89,T92,T94 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T89,T92,T94 Yes T89,T92,T94 OUTPUT
alert_tx_o[1].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[1].alert_p Yes Yes T89,T92,T94 Yes T89,T92,T94 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T262,T330,T334 Yes T262,T330,T334 OUTPUT
intr_edn_fatal_err_o Yes Yes T262,T330,T331 Yes T262,T330,T331 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%