Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : chip_earlgrey_asic
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.90 80.00 100.00 95.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 92.83 80.00 100.00 98.48



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.83 80.00 100.00 98.48


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.25 95.29 93.64 95.33 94.46 97.53


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
top_earlgrey 94.99 95.22 93.14 95.33 94.24 97.02
u_ast 93.28 93.28
u_padring 99.04 99.21 99.81 96.57 99.60 100.00
u_prim_usb_diff_rx 96.30 100.00 88.89 100.00

Line Coverage for Module : chip_earlgrey_asic
Line No.TotalCoveredPercent
TOTAL252080.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28311100.00
CONT_ASSIGN857100.00
CONT_ASSIGN870100.00
CONT_ASSIGN899100.00
CONT_ASSIGN907100.00
CONT_ASSIGN91411100.00
CONT_ASSIGN91711100.00
CONT_ASSIGN92311100.00
CONT_ASSIGN92511100.00
CONT_ASSIGN929100.00
CONT_ASSIGN93211100.00
CONT_ASSIGN109711100.00
CONT_ASSIGN109811100.00
CONT_ASSIGN109911100.00
CONT_ASSIGN110011100.00
CONT_ASSIGN110711100.00
CONT_ASSIGN112411100.00
CONT_ASSIGN112511100.00
CONT_ASSIGN112611100.00
CONT_ASSIGN112711100.00
CONT_ASSIGN113111100.00
CONT_ASSIGN113211100.00
CONT_ASSIGN113311100.00
CONT_ASSIGN113411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' or '../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
282 1 1
283 1 1
857 0 1
870 0 1
899 0 1
907 0 1
914 1 1
917 1 1
923 1 1
925 1 1
929 0 1
932 1 1
1097 1 1
1098 1 1
1099 1 1
1100 1 1
1107 1 1
1124 1 1
1125 1 1
1126 1 1
1127 1 1
1131 1 1
1132 1 1
1133 1 1
1134 1 1


Cond Coverage for Module : chip_earlgrey_asic
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       79
 EXPRESSION (tb.dut.top_earlgrey.u_pwrmgr_aon.pwr_rst_o.reset_cause == LowPwrEntry)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT64,T65,T339

Toggle Coverage for Module : chip_earlgrey_asic
TotalCoveredPercent
Totals 70 64 91.43
Total Bits 140 134 95.71
Total Bits 0->1 70 70 100.00
Total Bits 1->0 70 64 91.43

Ports 70 64 91.43
Port Bits 140 134 95.71
Port Bits 0->1 70 70 100.00
Port Bits 1->0 70 64 91.43

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
POR_N Yes Yes T16,T17,T18 Yes T4,T5,T6 INOUT
USB_P Yes Yes T27,T20,T31 Yes T27,T20,T31 INOUT
USB_N Yes Yes T27,T31,T78 Yes T27,T19,T20 INOUT
CC1 No No Yes T19,T20,T21 INOUT
CC2 No No Yes T19,T20,T21 INOUT
FLASH_TEST_VOLT No No Yes T19,T20,T21 INOUT
FLASH_TEST_MODE0 No No Yes T19,T20,T21 INOUT
FLASH_TEST_MODE1 No No Yes T19,T20,T21 INOUT
OTP_EXT_VOLT No No Yes T19,T20,T21 INOUT
SPI_HOST_D0 Yes Yes T22,T23,T24 Yes T22,T20,T23 INOUT
SPI_HOST_D1 Yes Yes T22,T23,T24 Yes T22,T23,T24 INOUT
SPI_HOST_D2 Yes Yes T22,T24,T202 Yes T22,T24,T202 INOUT
SPI_HOST_D3 Yes Yes T22,T24,T202 Yes T22,T20,T24 INOUT
SPI_HOST_CLK Yes Yes T22,T23,T24 Yes T19,T22,T23 INOUT
SPI_HOST_CS_L Yes Yes T22,T23,T24 Yes T19,T22,T20 INOUT
SPI_DEV_D0 Yes Yes T49,T95,T50 Yes T49,T95,T50 INOUT
SPI_DEV_D1 Yes Yes T49,T95,T50 Yes T49,T95,T50 INOUT
SPI_DEV_D2 Yes Yes T22,T24,T202 Yes T22,T24,T202 INOUT
SPI_DEV_D3 Yes Yes T22,T24,T202 Yes T22,T24,T202 INOUT
SPI_DEV_CLK Yes Yes T49,T95,T50 Yes T49,T95,T50 INOUT
SPI_DEV_CS_L Yes Yes T2,T95,T19 Yes T95,T19,T207 INOUT
IOR8 Yes Yes T28,T29,T210 Yes T28,T2,T29 INOUT
IOR9 Yes Yes T28,T29,T210 Yes T28,T2,T29 INOUT
IOA0 Yes Yes T25,T1,T26 Yes T25,T1,T26 INOUT
IOA1 Yes Yes T25,T1,T26 Yes T25,T1,T26 INOUT
IOA2 Yes Yes T1,T33,T157 Yes T1,T33,T19 INOUT
IOA3 Yes Yes T1,T33,T34 Yes T1,T33,T19 INOUT
IOA4 Yes Yes T97,T156,T126 Yes T97,T156,T126 INOUT
IOA5 Yes Yes T97,T156,T126 Yes T97,T156,T126 INOUT
IOA6 Yes Yes T1,T33,T34 Yes T1,T33,T19 INOUT
IOA7 Yes Yes T1,T49,T33 Yes T1,T49,T33 INOUT
IOA8 Yes Yes T1,T33,T219 Yes T1,T33,T219 INOUT
IOB0 Yes Yes T43,T44,T37 Yes T43,T44,T37 INOUT
IOB1 Yes Yes T43,T44,T37 Yes T43,T44,T37 INOUT
IOB2 Yes Yes T37,T38,T39 Yes T21,T37,T38 INOUT
IOB3 Yes Yes T43,T28,T29 Yes T43,T210,T211 INOUT
IOB4 Yes Yes T43,T108,T220 Yes T43,T108,T220 INOUT
IOB5 Yes Yes T108,T220,T19 Yes T108,T220,T19 INOUT
IOB6 Yes Yes T28,T29,T210 Yes T2,T210,T211 INOUT
IOB7 Yes Yes T3,T33,T7 Yes T28,T29,T3 INOUT
IOB8 Yes Yes T210,T211,T212 Yes T210,T211,T212 INOUT
IOB9 Yes Yes T28,T29,T33 Yes T28,T29,T33 INOUT
IOB10 Yes Yes T33,T222,T223 Yes T33,T222,T223 INOUT
IOB11 Yes Yes T15,T221,T224 Yes T15,T221,T224 INOUT
IOB12 Yes Yes T15,T221,T224 Yes T15,T221,T224 INOUT
IOC0 Yes Yes T16,T53,T17 Yes T95,T19,T371 INOUT
IOC1 Yes Yes T95,T207,T208 Yes T95,T19,T20 INOUT
IOC2 Yes Yes T95,T207,T208 Yes T95,T19,T20 INOUT
IOC3 Yes Yes T225,T226,T227 Yes T225,T226,T227 INOUT
IOC4 Yes Yes T16,T225,T53 Yes T16,T225,T53 INOUT
IOC5 Yes Yes T58,T72,T74 Yes T58,T72,T169 INOUT
IOC6 Yes Yes T57,T126,T55 Yes T57,T126,T55 INOUT
IOC7 Yes Yes T210,T211,T212 Yes T28,T29,T210 INOUT
IOC8 Yes Yes T58,T72,T169 Yes T58,T72,T169 INOUT
IOC9 Yes Yes T33,T30,T46 Yes T28,T29,T33 INOUT
IOC10 Yes Yes T33,T157,T34 Yes T33,T157,T34 INOUT
IOC11 Yes Yes T33,T157,T34 Yes T33,T157,T34 INOUT
IOC12 Yes Yes T33,T157,T34 Yes T33,T19,T157 INOUT
IOR0 Yes Yes T58,T59,T54 Yes T58,T59,T54 INOUT
IOR1 Yes Yes T58,T59,T54 Yes T58,T59,T54 INOUT
IOR2 Yes Yes T58,T59,T54 Yes T58,T59,T54 INOUT
IOR3 Yes Yes T58,T59,T54 Yes T58,T59,T54 INOUT
IOR4 Yes Yes T55,T56,T73 Yes T57,T58,T59 INOUT
IOR5 Yes Yes T28,T29,T33 Yes T28,T29,T33 INOUT
IOR6 Yes Yes T33,T30,T34 Yes T28,T29,T33 INOUT
IOR7 Yes Yes T33,T34,T35 Yes T33,T19,T34 INOUT
IOR10 Yes Yes T33,T34,T35 Yes T33,T19,T34 INOUT
IOR11 Yes Yes T33,T34,T35 Yes T33,T19,T34 INOUT
IOR12 Yes Yes T33,T34,T35 Yes T33,T34,T35 INOUT
IOR13 Yes Yes T103,T210,T3 Yes T103,T210,T3 INOUT

Line Coverage for Instance : tb.dut
Line No.TotalCoveredPercent
TOTAL252080.00
CONT_ASSIGN28211100.00
CONT_ASSIGN28311100.00
CONT_ASSIGN857100.00
CONT_ASSIGN870100.00
CONT_ASSIGN899100.00
CONT_ASSIGN907100.00
CONT_ASSIGN91411100.00
CONT_ASSIGN91711100.00
CONT_ASSIGN92311100.00
CONT_ASSIGN92511100.00
CONT_ASSIGN929100.00
CONT_ASSIGN93211100.00
CONT_ASSIGN109711100.00
CONT_ASSIGN109811100.00
CONT_ASSIGN109911100.00
CONT_ASSIGN110011100.00
CONT_ASSIGN110711100.00
CONT_ASSIGN112411100.00
CONT_ASSIGN112511100.00
CONT_ASSIGN112611100.00
CONT_ASSIGN112711100.00
CONT_ASSIGN113111100.00
CONT_ASSIGN113211100.00
CONT_ASSIGN113311100.00
CONT_ASSIGN113411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' or '../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
282 1 1
283 1 1
857 0 1
870 0 1
899 0 1
907 0 1
914 1 1
917 1 1
923 1 1
925 1 1
929 0 1
932 1 1
1097 1 1
1098 1 1
1099 1 1
1100 1 1
1107 1 1
1124 1 1
1125 1 1
1126 1 1
1127 1 1
1131 1 1
1132 1 1
1133 1 1
1134 1 1


Cond Coverage for Instance : tb.dut
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       79
 EXPRESSION (tb.dut.top_earlgrey.u_pwrmgr_aon.pwr_rst_o.reset_cause == LowPwrEntry)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT64,T65,T339

Toggle Coverage for Instance : tb.dut
TotalCoveredPercent
Totals 66 64 96.97
Total Bits 132 130 98.48
Total Bits 0->1 66 66 100.00
Total Bits 1->0 66 64 96.97

Ports 66 64 96.97
Port Bits 132 130 98.48
Port Bits 0->1 66 66 100.00
Port Bits 1->0 66 64 96.97

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
POR_N Yes Yes T16,T17,T18 Yes T4,T5,T6 INOUT
USB_P Yes Yes T27,T20,T31 Yes T27,T20,T31 INOUT
USB_N Yes Yes T27,T31,T78 Yes T27,T19,T20 INOUT
CC1 No No Yes T19,T20,T21 INOUT
CC2 No No Yes T19,T20,T21 INOUT
FLASH_TEST_VOLT[0:0] Excluded Excluded Excluded INOUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
FLASH_TEST_MODE0[0:0] Excluded Excluded Excluded INOUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
FLASH_TEST_MODE1[0:0] Excluded Excluded Excluded INOUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
OTP_EXT_VOLT[0:0] Excluded Excluded Excluded INOUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and OTP. Must be covered in vendor closed source DV.
SPI_HOST_D0 Yes Yes T22,T23,T24 Yes T22,T20,T23 INOUT
SPI_HOST_D1 Yes Yes T22,T23,T24 Yes T22,T23,T24 INOUT
SPI_HOST_D2 Yes Yes T22,T24,T202 Yes T22,T24,T202 INOUT
SPI_HOST_D3 Yes Yes T22,T24,T202 Yes T22,T20,T24 INOUT
SPI_HOST_CLK Yes Yes T22,T23,T24 Yes T19,T22,T23 INOUT
SPI_HOST_CS_L Yes Yes T22,T23,T24 Yes T19,T22,T20 INOUT
SPI_DEV_D0 Yes Yes T49,T95,T50 Yes T49,T95,T50 INOUT
SPI_DEV_D1 Yes Yes T49,T95,T50 Yes T49,T95,T50 INOUT
SPI_DEV_D2 Yes Yes T22,T24,T202 Yes T22,T24,T202 INOUT
SPI_DEV_D3 Yes Yes T22,T24,T202 Yes T22,T24,T202 INOUT
SPI_DEV_CLK Yes Yes T49,T95,T50 Yes T49,T95,T50 INOUT
SPI_DEV_CS_L Yes Yes T2,T95,T19 Yes T95,T19,T207 INOUT
IOR8 Yes Yes T28,T29,T210 Yes T28,T2,T29 INOUT
IOR9 Yes Yes T28,T29,T210 Yes T28,T2,T29 INOUT
IOA0 Yes Yes T25,T1,T26 Yes T25,T1,T26 INOUT
IOA1 Yes Yes T25,T1,T26 Yes T25,T1,T26 INOUT
IOA2 Yes Yes T1,T33,T157 Yes T1,T33,T19 INOUT
IOA3 Yes Yes T1,T33,T34 Yes T1,T33,T19 INOUT
IOA4 Yes Yes T97,T156,T126 Yes T97,T156,T126 INOUT
IOA5 Yes Yes T97,T156,T126 Yes T97,T156,T126 INOUT
IOA6 Yes Yes T1,T33,T34 Yes T1,T33,T19 INOUT
IOA7 Yes Yes T1,T49,T33 Yes T1,T49,T33 INOUT
IOA8 Yes Yes T1,T33,T219 Yes T1,T33,T219 INOUT
IOB0 Yes Yes T43,T44,T37 Yes T43,T44,T37 INOUT
IOB1 Yes Yes T43,T44,T37 Yes T43,T44,T37 INOUT
IOB2 Yes Yes T37,T38,T39 Yes T21,T37,T38 INOUT
IOB3 Yes Yes T43,T28,T29 Yes T43,T210,T211 INOUT
IOB4 Yes Yes T43,T108,T220 Yes T43,T108,T220 INOUT
IOB5 Yes Yes T108,T220,T19 Yes T108,T220,T19 INOUT
IOB6 Yes Yes T28,T29,T210 Yes T2,T210,T211 INOUT
IOB7 Yes Yes T3,T33,T7 Yes T28,T29,T3 INOUT
IOB8 Yes Yes T210,T211,T212 Yes T210,T211,T212 INOUT
IOB9 Yes Yes T28,T29,T33 Yes T28,T29,T33 INOUT
IOB10 Yes Yes T33,T222,T223 Yes T33,T222,T223 INOUT
IOB11 Yes Yes T15,T221,T224 Yes T15,T221,T224 INOUT
IOB12 Yes Yes T15,T221,T224 Yes T15,T221,T224 INOUT
IOC0 Yes Yes T16,T53,T17 Yes T95,T19,T371 INOUT
IOC1 Yes Yes T95,T207,T208 Yes T95,T19,T20 INOUT
IOC2 Yes Yes T95,T207,T208 Yes T95,T19,T20 INOUT
IOC3 Yes Yes T225,T226,T227 Yes T225,T226,T227 INOUT
IOC4 Yes Yes T16,T225,T53 Yes T16,T225,T53 INOUT
IOC5 Yes Yes T58,T72,T74 Yes T58,T72,T169 INOUT
IOC6 Yes Yes T57,T126,T55 Yes T57,T126,T55 INOUT
IOC7 Yes Yes T210,T211,T212 Yes T28,T29,T210 INOUT
IOC8 Yes Yes T58,T72,T169 Yes T58,T72,T169 INOUT
IOC9 Yes Yes T33,T30,T46 Yes T28,T29,T33 INOUT
IOC10 Yes Yes T33,T157,T34 Yes T33,T157,T34 INOUT
IOC11 Yes Yes T33,T157,T34 Yes T33,T157,T34 INOUT
IOC12 Yes Yes T33,T157,T34 Yes T33,T19,T157 INOUT
IOR0 Yes Yes T58,T59,T54 Yes T58,T59,T54 INOUT
IOR1 Yes Yes T58,T59,T54 Yes T58,T59,T54 INOUT
IOR2 Yes Yes T58,T59,T54 Yes T58,T59,T54 INOUT
IOR3 Yes Yes T58,T59,T54 Yes T58,T59,T54 INOUT
IOR4 Yes Yes T55,T56,T73 Yes T57,T58,T59 INOUT
IOR5 Yes Yes T28,T29,T33 Yes T28,T29,T33 INOUT
IOR6 Yes Yes T33,T30,T34 Yes T28,T29,T33 INOUT
IOR7 Yes Yes T33,T34,T35 Yes T33,T19,T34 INOUT
IOR10 Yes Yes T33,T34,T35 Yes T33,T19,T34 INOUT
IOR11 Yes Yes T33,T34,T35 Yes T33,T19,T34 INOUT
IOR12 Yes Yes T33,T34,T35 Yes T33,T34,T35 INOUT
IOR13 Yes Yes T103,T210,T3 Yes T103,T210,T3 INOUT

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