974aaab627| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_example_tests | chip_sw_example_flash | 3.679m | 2.218ms | 3 | 3 | 100.00 |
| chip_sw_example_rom | 2.392m | 2.540ms | 3 | 3 | 100.00 | ||
| chip_sw_example_manufacturer | 4.798m | 3.503ms | 3 | 3 | 100.00 | ||
| chip_sw_example_concurrency | 5.786m | 3.207ms | 3 | 3 | 100.00 | ||
| V1 | csr_hw_reset | chip_csr_hw_reset | 7.045m | 6.113ms | 5 | 5 | 100.00 |
| V1 | csr_rw | chip_csr_rw | 11.654m | 6.397ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | chip_csr_bit_bash | 1.610h | 47.459ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | chip_csr_aliasing | 2.880h | 57.636ms | 4 | 5 | 80.00 |
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 17.003m | 11.153ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 2.880h | 57.636ms | 4 | 5 | 80.00 |
| chip_csr_rw | 11.654m | 6.397ms | 20 | 20 | 100.00 | ||
| V1 | xbar_smoke | xbar_smoke | 11.030s | 238.860us | 100 | 100 | 100.00 |
| V1 | chip_sw_gpio_out | chip_sw_gpio | 9.268m | 3.728ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 9.268m | 3.728ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 9.268m | 3.728ms | 3 | 3 | 100.00 |
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 12.231m | 4.826ms | 5 | 5 | 100.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 12.231m | 4.826ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_idx1 | 13.707m | 4.186ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx2 | 12.448m | 3.631ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx3 | 11.804m | 5.020ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_uart_baud_rate | chip_sw_uart_rand_baudrate | 39.413m | 12.621ms | 20 | 20 | 100.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 24.394m | 8.838ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 34.156m | 13.642ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 219 | 220 | 99.55 | |||
| V2 | chip_pin_mux | chip_padctrl_attributes | 6.248m | 5.470ms | 10 | 10 | 100.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 6.248m | 5.470ms | 10 | 10 | 100.00 |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 6.048m | 3.222ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 8.354m | 5.354ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 6.708m | 3.928ms | 3 | 3 | 100.00 |
| V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev | 25.146m | 14.616ms | 5 | 5 | 100.00 |
| chip_tap_straps_testunlock0 | 10.234m | 5.637ms | 3 | 5 | 60.00 | ||
| chip_tap_straps_rma | 1.704h | 60.000ms | 4 | 5 | 80.00 | ||
| chip_tap_straps_prod | 22.898m | 12.842ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_pattgen_ios | chip_sw_pattgen_ios | 4.280m | 3.042ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | 28.704m | 10.003ms | 3 | 3 | 100.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 13.303m | 5.086ms | 6 | 6 | 100.00 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 13.303m | 5.086ms | 6 | 6 | 100.00 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 16.752m | 6.755ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 1.071h | 27.397ms | 2 | 3 | 66.67 |
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_flash_ctrl_ops_jitter_en | 12.190m | 3.764ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.052m | 6.126ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.255h | 18.830ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 5.460m | 3.051ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 22.539m | 6.579ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 4.313m | 2.624ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 41.174m | 13.114ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.154m | 3.123ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 10.742m | 4.208ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 4.585m | 2.827ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_ast_usb_clk_calib | chip_sw_usb_ast_clk_calib | 5.724m | 3.106ms | 1 | 1 | 100.00 |
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_sensor_ctrl_alert | 18.039m | 7.508ms | 5 | 5 | 100.00 |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 8.154m | 5.418ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 4.791m | 2.664ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 8.154m | 5.418ms | 3 | 3 | 100.00 |
| V2 | chip_sw_smoketest | chip_sw_flash_scrambling_smoketest | 4.461m | 3.580ms | 3 | 3 | 100.00 |
| chip_sw_aes_smoketest | 5.323m | 3.537ms | 3 | 3 | 100.00 | ||
| chip_sw_aon_timer_smoketest | 6.354m | 3.560ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 5.126m | 3.612ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 4.983m | 3.115ms | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_smoketest | 8.738m | 4.098ms | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 5.686m | 2.550ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 6.056m | 3.417ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 6.246m | 2.700ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 36.446m | 8.753ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 8.325m | 6.428ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_usbdev_smoketest | 9.617m | 6.519ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 5.130m | 3.001ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 4.984m | 2.957ms | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 4.607m | 2.881ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 4.852m | 3.083ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 4.773m | 2.797ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_smoketest | chip_sw_otp_ctrl_smoketest | 4.568m | 2.788ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 12.000m | 4.956ms | 3 | 3 | 100.00 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 3.931h | 76.939ms | 3 | 3 | 100.00 |
| V2 | chip_sw_secure_boot | rom_e2e_smoke | 1.134h | 14.949ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_raw_unlock | rom_raw_unlock | 5.564m | 6.852ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_idle_load | chip_sw_power_idle_load | 14.731m | 4.695ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_sleep_load | chip_sw_power_sleep_load | 6.364m | 4.705ms | 3 | 3 | 100.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 3.171h | 60.190ms | 3 | 3 | 100.00 |
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 3.452h | 65.604ms | 3 | 3 | 100.00 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 12.290m | 6.060ms | 30 | 30 | 100.00 |
| V2 | tl_d_illegal_access | chip_tl_errors | 12.290m | 6.060ms | 30 | 30 | 100.00 |
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 2.880h | 57.636ms | 4 | 5 | 80.00 |
| chip_same_csr_outstanding | 1.479h | 30.918ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 7.045m | 6.113ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 11.654m | 6.397ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | chip_csr_aliasing | 2.880h | 57.636ms | 4 | 5 | 80.00 |
| chip_same_csr_outstanding | 1.479h | 30.918ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 7.045m | 6.113ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 11.654m | 6.397ms | 20 | 20 | 100.00 | ||
| V2 | xbar_base_random_sequence | xbar_random | 1.559m | 2.458ms | 100 | 100 | 100.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 7.500s | 55.213us | 100 | 100 | 100.00 |
| xbar_smoke_large_delays | 2.094m | 11.196ms | 100 | 100 | 100.00 | ||
| xbar_smoke_slow_rsp | 2.142m | 6.797ms | 100 | 100 | 100.00 | ||
| xbar_random_zero_delays | 58.000s | 613.912us | 100 | 100 | 100.00 | ||
| xbar_random_large_delays | 22.316m | 105.442ms | 100 | 100 | 100.00 | ||
| xbar_random_slow_rsp | 21.606m | 68.449ms | 100 | 100 | 100.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 1.049m | 1.487ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 59.760s | 1.279ms | 100 | 100 | 100.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 1.611m | 2.673ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 59.760s | 1.279ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 2.698m | 3.657ms | 100 | 100 | 100.00 |
| xbar_access_same_device_slow_rsp | 54.700m | 168.664ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 1.405m | 2.697ms | 100 | 100 | 100.00 |
| V2 | xbar_stress_all | xbar_stress_all | 14.228m | 19.831ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_error | 14.685m | 25.493ms | 100 | 100 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 22.183m | 12.981ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_reset_error | 12.678m | 14.840ms | 100 | 100 | 100.00 | ||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 1.134h | 14.949ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 1.014h | 25.127ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 1.069h | 14.773ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 56.142m | 11.930ms | 1 | 1 | 100.00 |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 1.105h | 15.487ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 1.028h | 15.939ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 1.406h | 15.018ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 1.038h | 14.694ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 49.206m | 11.268ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 1.003h | 15.521ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 58.160m | 15.443ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 1.134h | 15.020ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 1.074h | 14.610ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 1.250h | 18.613ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 1.909h | 24.271ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 1.497h | 24.185ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 1.788h | 24.868ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 2.086h | 23.520ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 1.245h | 17.207ms | 1 | 1 | 100.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 1.948h | 23.568ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 1.570h | 22.951ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 1.738h | 23.799ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 1.637h | 23.064ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 1.016h | 11.371ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 1.156h | 14.347ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 56.935m | 14.771ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 1.357h | 14.635ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 54.364m | 13.770ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 53.005m | 11.077ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 1.036h | 14.270ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 59.038m | 15.083ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 53.213m | 14.797ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 57.117m | 13.757ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 54.804m | 11.604ms | 3 | 3 | 100.00 |
| rom_e2e_asm_init_dev | 1.336h | 15.442ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod | 1.174h | 15.625ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod_end | 1.095h | 15.009ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_rma | 1.118h | 15.126ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 1.137h | 15.433ms | 3 | 3 | 100.00 |
| rom_e2e_keymgr_init_rom_ext_no_meas | 1.037h | 15.219ms | 3 | 3 | 100.00 | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 1.107h | 15.361ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 1.364h | 16.779ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 7.123m | 3.116ms | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 5.460m | 3.051ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_aes_multi_block | chip_sw_aes_multi_block | 0 | 0 | -- | ||
| V2 | chip_sw_aes_interrupt_encryption | chip_sw_aes_interrupt_encryption | 0 | 0 | -- | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 4.600m | 2.614ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_prng_reseed | chip_sw_aes_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_force_prng_reseed | chip_sw_aes_force_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 5.191m | 2.086ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 27.269m | 8.644ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_debug_cable_irq | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 11.180m | 18.488ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 11.180m | 18.488ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 6.968m | 3.896ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 8.325m | 6.428ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 6.968m | 3.896ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 15.966m | 7.412ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 15.966m | 7.412ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 10.189m | 8.075ms | 5 | 5 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 12.173m | 6.370ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 16.181m | 6.155ms | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 5.191m | 2.086ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 5.012m | 2.762ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 4.386m | 2.977ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 9.954m | 4.818ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_off_hmac_trans | 11.154m | 5.340ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 10.876m | 4.731ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 10.970m | 5.490ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 23.742m | 10.325ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 11.155m | 3.919ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 9.504m | 4.864ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 11.139m | 4.510ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 13.251m | 4.962ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 12.620m | 3.873ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 12.345m | 4.843ms | 3 | 3 | 100.00 | ||
| chip_sw_ast_clk_outputs | 16.752m | 6.755ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | 9.518m | 6.683ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 11.139m | 4.510ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 13.251m | 4.962ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_flash_ctrl_ops_jitter_en | 12.190m | 3.764ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.052m | 6.126ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.255h | 18.830ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 5.460m | 3.051ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 22.539m | 6.579ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 4.313m | 2.624ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 41.174m | 13.114ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.154m | 3.123ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 10.742m | 4.208ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 4.585m | 2.827ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 3.577m | 3.315ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 11.568m | 4.891ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 20.302m | 6.775ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 1.144h | 24.752ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 4.853m | 3.161ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 4.520m | 3.554ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 28.266m | 10.546ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 5.407m | 2.927ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 11.724m | 5.404ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_init_reduced_freq | 40.960m | 26.683ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 2.759h | 68.797ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 16.752m | 6.755ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 13.383m | 4.891ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 7.703m | 3.227ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 13.917m | 6.758ms | 97 | 100 | 97.00 |
| V2 | chip_sw_clkmgr_alert_handler_clock_enables | chip_sw_alert_handler_lpg_clkoff | 29.568m | 7.396ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 22.375m | 6.292ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 8.777m | 4.232ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_lc_hw_debug_en | chip_sw_csrng_lc_hw_debug_en_test | 15.565m | 7.346ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 5.403m | 2.971ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 26.445m | 9.688ms | 3 | 3 | 100.00 |
| chip_sw_sysrst_ctrl_reset | 30.495m | 21.551ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | 6.275m | 3.455ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_outputs | chip_sw_sysrst_ctrl_outputs | 7.530m | 3.981ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_in_irq | chip_sw_sysrst_ctrl_in_irq | 10.969m | 4.711ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | 30.495m | 21.551ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | 30.495m | 21.551ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ec_rst_l | chip_sw_sysrst_ctrl_ec_rst_l | 1.141h | 20.519ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_flash_wp_l | chip_sw_sysrst_ctrl_ec_rst_l | 1.141h | 20.519ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | chip_sw_sysrst_ctrl_ulp_z3_wakeup | 8.773m | 5.565ms | 3 | 3 | 100.00 |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 11.180m | 18.488ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 1.735h | 25.447ms | 10 | 10 | 100.00 |
| chip_sw_entropy_src_ast_rng_req | 4.821m | 2.668ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs | 25.461m | 6.281ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rng_req | 4.821m | 2.668ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 22.375m | 6.292ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fuse_en_fw_read | chip_sw_entropy_src_fuse_en_fw_read_test | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | 4.818m | 2.182ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fw_observe_many_contiguous | chip_sw_entropy_src_fw_observe_many_contiguous | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_fw_extract_and_insert | chip_sw_entropy_src_fw_extract_and_insert | 0 | 0 | -- | ||
| V2 | chip_sw_flash_init | chip_sw_flash_init | 45.703m | 20.296ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access | 18.457m | 5.963ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.052m | 6.126ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops | 12.047m | 3.760ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en | 12.190m | 3.764ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | 1.683h | 43.584ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_scramble | chip_sw_flash_init | 45.703m | 20.296ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | 7.808m | 3.947ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_keymgr_seeds | chip_sw_keymgr_key_derivation | 37.532m | 11.709ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 9.820m | 5.357ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | 1.683h | 43.584ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 9.820m | 5.357ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 9.820m | 5.357ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | 9.820m | 5.357ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 9.820m | 5.357ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_escalate_en | chip_sw_all_escalation_resets | 13.917m | 6.758ms | 97 | 100 | 97.00 |
| V2 | chip_sw_flash_prim_tl_access | chip_prim_tl_access | 11.743m | 13.042ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | 20.438m | 5.934ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_escalation_reset | chip_sw_flash_crash_alert | 13.241m | 5.895ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_write_clear | chip_sw_flash_crash_alert | 13.241m | 5.895ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 5.675m | 3.293ms | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 4.313m | 2.624ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 5.012m | 2.762ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_all_configurations | chip_sw_hmac_oneshot | 6.542m | 3.649ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_multistream_mode | chip_sw_hmac_multistream | 26.980m | 8.486ms | 3 | 3 | 100.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 17.253m | 4.801ms | 3 | 3 | 100.00 |
| chip_sw_i2c_host_tx_rx_idx1 | 13.990m | 4.890ms | 3 | 3 | 100.00 | ||
| chip_sw_i2c_host_tx_rx_idx2 | 17.819m | 5.314ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 10.631m | 3.823ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation | 37.532m | 11.709ms | 3 | 3 | 100.00 |
| chip_sw_keymgr_key_derivation_jitter_en | 41.174m | 13.114ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 48.088m | 11.453ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 27.269m | 8.644ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_otbn | chip_sw_keymgr_sideload_otbn | 1.181h | 13.347ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 3.978m | 3.459ms | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 5.717m | 3.090ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.154m | 3.123ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_key_derivation | 37.532m | 11.709ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 18.630m | 8.807ms | 15 | 15 | 100.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 4.366m | 3.031ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 5.313m | 2.966ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 4.386m | 2.977ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 9.702m | 5.545ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev | 25.146m | 14.616ms | 5 | 5 | 100.00 |
| chip_tap_straps_rma | 1.704h | 60.000ms | 4 | 5 | 80.00 | ||
| chip_tap_straps_prod | 22.898m | 12.842ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_otp_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 5.746m | 2.969ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 18.630m | 8.807ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 18.630m | 8.807ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 18.630m | 8.807ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_key_derivation_prod | 41.917m | 12.218ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_flash_ctrl_lc_rw_en | 9.820m | 5.357ms | 3 | 3 | 100.00 |
| chip_sw_flash_rma_unlocked | 1.683h | 43.584ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 13.793m | 4.058ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 24.749m | 9.129ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 21.332m | 7.296ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 22.592m | 8.808ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 18.630m | 8.807ms | 15 | 15 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 37.532m | 11.709ms | 3 | 3 | 100.00 | ||
| chip_sw_rom_ctrl_integrity_check | 11.088m | 9.592ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 16.968m | 7.910ms | 3 | 3 | 100.00 | ||
| chip_prim_tl_access | 11.743m | 13.042ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_lc | 9.518m | 6.683ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 11.155m | 3.919ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 9.504m | 4.864ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 11.139m | 4.510ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 13.251m | 4.962ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 12.620m | 3.873ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 12.345m | 4.843ms | 3 | 3 | 100.00 | ||
| chip_tap_straps_dev | 25.146m | 14.616ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 1.704h | 60.000ms | 4 | 5 | 80.00 | ||
| chip_tap_straps_prod | 22.898m | 12.842ms | 5 | 5 | 100.00 | ||
| chip_rv_dm_lc_disabled | 17.624m | 21.466ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 2.696m | 3.800ms | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 2.608m | 3.166ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 2.201m | 3.213ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 5.838m | 3.342ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 35.757m | 32.582ms | 3 | 3 | 100.00 |
| chip_rv_dm_lc_disabled | 17.624m | 21.466ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 1.692h | 48.058ms | 3 | 3 | 100.00 |
| chip_sw_lc_walkthrough_prod | 1.650h | 50.195ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_prodend | 19.603m | 11.514ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_rma | 1.689h | 49.329ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 35.757m | 32.582ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 2.137m | 2.558ms | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 1.938m | 2.308ms | 3 | 3 | 100.00 | ||
| rom_volatile_raw_unlock | 2.044m | 3.091ms | 3 | 3 | 100.00 | ||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 18.630m | 8.807ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_flash_init | 45.703m | 20.296ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 11.040m | 3.780ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 37.532m | 11.709ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 10.694m | 5.273ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 4.936m | 2.510ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_flash_init | 45.703m | 20.296ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 11.040m | 3.780ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 37.532m | 11.709ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 10.694m | 5.273ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 4.936m | 2.510ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 18.630m | 8.807ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 9.872m | 4.908ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 5.746m | 2.969ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 13.793m | 4.058ms | 3 | 3 | 100.00 |
| chip_sw_otp_ctrl_lc_signals_dev | 24.749m | 9.129ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 21.332m | 7.296ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 22.592m | 8.808ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 18.630m | 8.807ms | 15 | 15 | 100.00 | ||
| chip_prim_tl_access | 11.743m | 13.042ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 11.743m | 13.042ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_dai_lock | chip_sw_otp_ctrl_dai_lock | 1.498h | 27.912ms | 1 | 1 | 100.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 9.635m | 9.395ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 27.334m | 21.156ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 6.991m | 7.396ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_por_reset | chip_sw_pwrmgr_deep_sleep_por_reset | 14.894m | 8.280ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_por_reset | chip_sw_pwrmgr_normal_sleep_por_reset | 14.324m | 7.408ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 33.364m | 26.484ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 29.674m | 18.410ms | 3 | 3 | 100.00 |
| chip_sw_aon_timer_wdog_bite_reset | 15.966m | 7.412ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 30.062m | 13.456ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 10.416m | 4.459ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 9.635m | 9.395ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 9.909m | 4.991ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 1.043h | 29.684ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 9.457m | 7.368ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 9.054m | 4.747ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 45.971m | 28.590ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 26.445m | 9.688ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_all_reset_reqs | 32.005m | 9.548ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | 53.124m | 27.971ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 5.331m | 3.409ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 13.917m | 6.758ms | 97 | 100 | 97.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 11.088m | 9.592ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 11.088m | 9.592ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_all_reset_reqs | 32.005m | 9.548ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 45.971m | 28.590ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_wdog_reset | 10.416m | 4.459ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 8.325m | 6.428ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 8.519m | 4.961ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 13.446m | 6.723ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 7.476m | 4.369ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 36.024m | 11.571ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 4.694m | 3.015ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 13.917m | 6.758ms | 97 | 100 | 97.00 |
| V2 | chip_sw_rstmgr_alert_handler_reset_enables | chip_sw_alert_handler_lpg_reset_toggle | 28.361m | 7.929ms | 3 | 3 | 100.00 |
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs_0 | 20.678m | 5.409ms | 3 | 3 | 100.00 |
| chip_plic_all_irqs_10 | 11.083m | 4.154ms | 3 | 3 | 100.00 | ||
| chip_plic_all_irqs_20 | 16.141m | 5.543ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 6.383m | 3.473ms | 3 | 3 | 100.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 5.862m | 3.499ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_flash_mode | rom_e2e_smoke | 1.134h | 14.949ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 12.444m | 6.826ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 11.107m | 4.505ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 6.163m | 3.821ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 6.846m | 2.996ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 10.694m | 5.273ms | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 10.742m | 4.208ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents_no_scramble | 15.535m | 8.423ms | 3 | 3 | 100.00 |
| chip_sw_sleep_sram_ret_contents_scramble | 14.521m | 8.121ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 16.968m | 7.910ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 13.917m | 6.758ms | 97 | 100 | 97.00 |
| chip_sw_data_integrity_escalation | 13.303m | 5.086ms | 6 | 6 | 100.00 | ||
| V2 | chip_sw_usbdev_mem | chip_sw_usbdev_mem | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_vbus | chip_sw_usbdev_vbus | 3.877m | 3.008ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pullup | chip_sw_usbdev_pullup | 6.478m | 3.499ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_aon_pullup | chip_sw_usbdev_aon_pullup | 6.108m | 3.953ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_sof | chip_sw_usbdev_sof | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_setup_rx | chip_sw_usbdev_setuprx | 11.125m | 4.167ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_config_host | chip_sw_usbdev_config_host | 26.971m | 8.481ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pincfg | chip_sw_usbdev_pincfg | 2.020h | 31.872ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_tx_rx | chip_sw_usbdev_dpi | 44.511m | 11.953ms | 1 | 1 | 100.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 6.685m | 2.700ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 9.702m | 5.545ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalation_nmi_reset | chip_sw_alert_handler_escalation_nmi_reset | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_escalation_methods | chip_sw_alert_handler_escalation_methods | 0 | 0 | -- | ||
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 13.917m | 6.758ms | 97 | 100 | 97.00 |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 6.379m | 3.419ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 36.024m | 11.571ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 8.405m | 5.557ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 9.977m | 3.721ms | 90 | 90 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 19.580m | 10.315ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 29.568m | 7.396ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 28.361m | 7.929ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_ok | chip_sw_alert_handler_ping_ok | 24.276m | 8.087ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3.494h | 255.306ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 24.549m | 11.671ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 28.131m | 13.808ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 8.519m | 4.961ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 9.389m | 4.060ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 10.861m | 7.279ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_jtag_tap_sel | chip_tap_straps_rma | 1.704h | 60.000ms | 4 | 5 | 80.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 17.624m | 21.466ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_jtag | chip_rv_dm_jtag | 0 | 0 | -- | ||
| V2 | chip_rv_dm_dtm | chip_rv_dm_dtm | 0 | 0 | -- | ||
| V2 | chip_rv_dm_control_status | chip_rv_dm_control_status | 0 | 0 | -- | ||
| V2 | TOTAL | 2637 | 2644 | 99.74 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 5.683m | 2.705ms | 3 | 3 | 100.00 |
| V2S | TOTAL | 3 | 3 | 100.00 | |||
| V3 | chip_sw_usb_suspend | chip_sw_usb_suspend | 0 | 0 | -- | ||
| V3 | chip_sw_coremark | chip_sw_coremark | 4.061h | 71.281ms | 1 | 1 | 100.00 |
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 0 | 3 | 0.00 | ||
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 31.991m | 10.728ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 39.011m | 11.998ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 41.379m | 11.032ms | 1 | 1 | 100.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 26.293m | 24.514ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_inject_dev | 57.303m | 25.043ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_inject_rma | 48.850m | 34.757ms | 1 | 1 | 100.00 | ||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
| V3 | rom_e2e_self_hash | rom_e2e_self_hash | 1.669h | 25.960ms | 3 | 3 | 100.00 |
| V3 | manuf_cp_unlock_raw | manuf_cp_unlock_raw | 0 | 0 | -- | ||
| V3 | manuf_scrap | manuf_scrap | 0 | 0 | -- | ||
| V3 | manuf_cp_yield_test | manuf_cp_yield_test | 0 | 0 | -- | ||
| V3 | manuf_cp_ast_test_execution | manuf_cp_ast_test_execution | 0 | 0 | -- | ||
| V3 | manuf_cp_device_info_flash_wr | manuf_cp_device_info_flash_wr | 0 | 0 | -- | ||
| V3 | manuf_cp_test_lock | manuf_cp_test_lock | 0 | 0 | -- | ||
| V3 | manuf_ft_exit_token | manuf_ft_exit_token | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization_preop | manuf_ft_sku_individualization_preop | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization | manuf_ft_sku_individualization | 0 | 0 | -- | ||
| V3 | manuf_ft_provision_rma_token_and_personalization | manuf_ft_provision_rma_token_and_personalization | 0 | 0 | -- | ||
| V3 | manuf_ft_load_transport_image | manuf_ft_load_transport_image | 0 | 0 | -- | ||
| V3 | manuf_ft_load_certificates | manuf_ft_load_certificates | 0 | 0 | -- | ||
| V3 | manuf_ft_eom | manuf_ft_eom | 0 | 0 | -- | ||
| V3 | manuf_rma_entry | manuf_rma_entry | 0 | 0 | -- | ||
| V3 | manuf_sram_program_crc_functest | manuf_sram_program_crc_functest | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_normal | chip_sw_adc_ctrl_normal | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_oneshot | chip_sw_adc_ctrl_oneshot | 0 | 0 | -- | ||
| V3 | chip_sw_clkmgr_jitter_cycle_measurements | chip_sw_clkmgr_jitter_frequency | 9.044m | 3.451ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_boot_mode | chip_sw_edn_boot_mode | 11.806m | 3.560ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_auto_mode | chip_sw_edn_auto_mode | 26.666m | 5.879ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_sw_mode | chip_sw_edn_sw_mode | 48.207m | 10.700ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_kat | chip_sw_edn_kat | 11.463m | 3.437ms | 3 | 3 | 100.00 |
| V3 | chip_sw_entropy_src_bypass_mode_health_tests | chip_sw_entropy_src_bypass_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_fips_mode_health_tests | chip_sw_entropy_src_fips_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_validation | chip_sw_entropy_src_validation | 0 | 0 | -- | ||
| V3 | chip_sw_flash_memory_protection | chip_sw_flash_ctrl_mem_protection | 19.384m | 5.212ms | 3 | 3 | 100.00 |
| V3 | chip_sw_hmac_sha2_stress | chip_sw_hmac_sha2_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_stress | chip_sw_hmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_endianness | chip_sw_hmac_endianness | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_secure_wipe | chip_sw_hmac_secure_wipe | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_error_conditions | chip_sw_hmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_speed | chip_sw_i2c_speed | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_override | chip_sw_i2c_override | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_clockstretching | chip_sw_i2c_clockstretching | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_nack | chip_sw_i2c_nack | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_repeatedstart | chip_sw_i2c_repeatedstart | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_attestation | chip_sw_keymgr_derive_attestation | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_sealing | chip_sw_keymgr_derive_sealing | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_sha3_stress | chip_sw_kmac_sha3_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_shake_stress | chip_sw_kmac_shake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_cshake_stress | chip_sw_kmac_cshake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_stress | chip_sw_kmac_kmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_key_sideload | chip_sw_kmac_kmac_key_sideload | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_endianess | chip_sw_kmac_endianess | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_entropy_stress | chip_sw_kmac_entropy_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_error_conditions | chip_sw_kmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_debug_access | chip_sw_lc_ctrl_debug_access | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 3.406m | 2.369ms | 3 | 3 | 100.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 10.404m | 4.797ms | 1 | 1 | 100.00 |
| V3 | otp_ctrl_calibration | otp_ctrl_calibration | 0 | 0 | -- | ||
| V3 | otp_ctrl_partition_access_locked | otp_ctrl_partition_access_locked | 0 | 0 | -- | ||
| V3 | otp_ctrl_check_timeout | otp_ctrl_check_timeout | 0 | 0 | -- | ||
| V3 | chip_sw_sensor_ctrl_deep_sleep_wake_up | chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 10.466m | 6.685ms | 3 | 3 | 100.00 |
| V3 | chip_sw_pwrmgr_usb_clk_disabled_when_active | chip_sw_pwrmgr_usb_clk_disabled_when_active | 9.561m | 4.848ms | 3 | 3 | 100.00 |
| V3 | chip_sw_all_resets | chip_sw_pwrmgr_all_reset_reqs | 32.005m | 9.548ms | 3 | 3 | 100.00 |
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_rom_ctrl_digests | chip_sw_rom_ctrl_digests | 0 | 0 | -- | ||
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 13.917m | 6.758ms | 97 | 100 | 97.00 |
| V3 | tick_configuration | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | counter_wrap | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | chip_sw_spi_device_pass_through_flash_model | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_output_when_disabled_or_sleeping | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_pass_through | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_configuration | //sw/device/tests:spi_host_config_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_events | chip_sw_spi_host_events | 0 | 0 | -- | ||
| V3 | chip_sw_sram_memset | chip_sw_sram_memset | 0 | 0 | -- | ||
| V3 | chip_sw_sram_readback | chip_sw_sram_readback | 0 | 0 | -- | ||
| V3 | chip_sw_sram_subword_access | chip_sw_sram_subword_access | 0 | 0 | -- | ||
| V3 | chip_sw_uart_parity | chip_sw_uart_parity | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_loopback | chip_sw_uart_line_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_system_loopback | chip_sw_uart_system_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_break | chip_sw_uart_line_break | 0 | 0 | -- | ||
| V3 | chip_sw_uart_watermarks | chip_sw_uart_tx_rx | 12.231m | 4.826ms | 5 | 5 | 100.00 |
| V3 | chip_sw_usbdev_stream | chip_sw_usbdev_stream | 1.200h | 18.742ms | 1 | 1 | 100.00 |
| V3 | chip_sw_usbdev_iso | chip_sw_usbdev_iso | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_mixed | chip_sw_usbdev_mixed | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_suspend_resume | chip_sw_usbdev_suspend_resume | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_reset | chip_sw_usbdev_aon_wake_reset | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_disconnect | chip_sw_usbdev_aon_wake_disconnect | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_toggle_restore | chip_sw_usbdev_toggle_restore | 0 | 0 | -- | ||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 31.991m | 10.728ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 39.011m | 11.998ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 41.379m | 11.032ms | 1 | 1 | 100.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 10.306m | 5.672ms | 3 | 3 | 100.00 |
| V3 | TOTAL | 42 | 48 | 87.50 | |||
| Unmapped tests | chip_sival_flash_info_access | 6.589m | 3.748ms | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_rst_cnsty_escalation | 14.043m | 5.320ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_ecc_error_vendor_test | 5.706m | 3.507ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq | 1.000h | 16.490ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_rnd | 19.829m | 5.186ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_nmi_irq | 16.928m | 5.127ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_lowpower_cancel | 8.691m | 3.988ms | 2 | 3 | 66.67 | ||
| chip_sw_pwrmgr_sleep_wake_5_bug | 8.145m | 6.623ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_address_translation | 5.533m | 2.773ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_lockstep_glitch | 3.230m | 2.598ms | 2 | 3 | 66.67 | ||
| chip_sw_flash_ctrl_write_clear | 7.312m | 3.093ms | 3 | 3 | 100.00 | ||
| TOTAL | 2932 | 2948 | 99.46 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 11 | 11 | 9 | 81.82 |
| V1 | 18 | 18 | 17 | 94.44 |
| V2 | 285 | 270 | 266 | 93.33 |
| V2S | 1 | 1 | 1 | 100.00 |
| V3 | 90 | 22 | 20 | 22.22 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 95.98 | 95.29 | 93.64 | 95.33 | -- | 94.46 | 97.53 | 99.62 |
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 9 failures:
Test chip_sw_rv_timer_systick_test has 3 failures.
0.chip_sw_rv_timer_systick_test.83284899617666433789251000247927552565643226849322191262602353809180518056753
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
Job ID: smart:76ea060c-0d9a-4f84-bb8f-802bb36eae12
1.chip_sw_rv_timer_systick_test.84278462059587793958825057540814641138282577952567840166077131330529987746460
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
Job ID: smart:546830b5-5cd1-4a97-a22d-de6728e8c539
... and 1 more failures.
Test chip_sw_ast_clk_rst_inputs has 1 failures.
0.chip_sw_ast_clk_rst_inputs.102482294436252797788633407640792740884823208338477545310435736141418612428891
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
Job ID: smart:14bdfeab-2813-4573-8106-551ce30704a5
Test chip_sw_power_virus has 3 failures.
0.chip_sw_power_virus.108350891266282961346919054729108588776592551420294171932872854882229689314839
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
Job ID: smart:cc812c60-6ba2-4e25-8bdb-319b7998f345
1.chip_sw_power_virus.43827587205932624100004774191359895136752421591960087373766084080026108117367
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
Job ID: smart:37ab60a5-df46-439a-b0de-c88541c0c24c
... and 1 more failures.
Test chip_tap_straps_testunlock0 has 2 failures.
2.chip_tap_straps_testunlock0.109101102705238162767065439661451355663982478127941915606418060349504210364854
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_testunlock0/latest/run.log
Job ID: smart:3df9273a-8bcf-49b6-b937-2db089233d68
4.chip_tap_straps_testunlock0.53854161521232108379349492018371338578223356974407088470667955946452870195350
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/4.chip_tap_straps_testunlock0/latest/run.log
Job ID: smart:53e00dad-5190-4b78-a9b3-5cc8677b47b1
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 3 failures:
12.chip_sw_all_escalation_resets.66764276267519493322925120395464094972558407418126127078131952927005326201634
Line 784, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/12.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 3173.594590 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 3173.594590 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.chip_sw_all_escalation_resets.73705278299097516322480312509426059259066365457321677037836583378747475858191
Line 805, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/32.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 2726.081278 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 2726.081278 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
0.chip_sw_rv_core_ibex_lockstep_glitch.15416896178505751540997079794958235034175963368967616955184396367024125662972
Line 819, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
UVM_FATAL @ 2598.316524 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 2598.316524 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:84)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status() has 1 failures:
1.chip_sw_pwrmgr_lowpower_cancel.59263912181719112202370344862613085693394596599420405236227491087573327999032
Line 791, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_lowpower_cancel/latest/run.log
UVM_ERROR @ 2763.256822 us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:84)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for !get_wakeup_status()
UVM_INFO @ 2763.256822 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * us hit, indicating a probable testbench issue has 1 failures:
1.chip_tap_straps_rma.112153658967094157818075938391247069317181833093044147899644371899002998957139
Line 6038, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_tap_straps_rma/latest/run.log
UVM_FATAL @ 60000.000000 us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 60000.000000 us hit, indicating a probable testbench issue
UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job chip_earlgrey_asic-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
2.chip_csr_aliasing.36633411279504595852097640288300394913771869365498322189024230209461370752890
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_aliasing/latest/run.log
Job ID: smart:bcf1e487-816c-445a-8e02-f1e6bd1abd36