Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1139625	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

34811350

1

T4

5277

T5

98379

T6

7411

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	25150334	1			T4	2146		T5	55266		T6	3461
values[0x0]	9660102	1			T4	3131		T5	43113		T6	3950
values[0x1]	1140539	1			T4	384		T5	486		T6	502

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8770	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

35942205

1

T4

5661

T5

98865

T6

7913

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17961909	1			T4	2831		T5	49433		T6	3957
valid_sources[0x01]	17960943	1			T4	2830		T5	49432		T6	3956
valid_sources[0x02]	476	1			T117	2		T221	2		T40	59
valid_sources[0x03]	403	1			T61	1		T64	1		T40	54
valid_sources[0x04]	530	1			T221	1		T40	72		T41	52
valid_sources[0x05]	392	1			T61	1		T117	3		T221	2
valid_sources[0x06]	440	1			T61	1		T117	2		T221	2
valid_sources[0x07]	343	1			T221	1		T40	22		T41	30
valid_sources[0x08]	351	1			T117	1		T40	27		T41	24
valid_sources[0x09]	3014	1			T1	1		T221	1		T40	76
valid_sources[0x0a]	392	1			T117	1		T40	52		T41	29
valid_sources[0x0b]	374	1			T64	1		T117	1		T40	32
valid_sources[0x0c]	329	1			T1	1		T221	2		T40	34
valid_sources[0x0d]	399	1			T1	1		T64	1		T117	2
valid_sources[0x0e]	413	1			T61	3		T64	3		T40	25
valid_sources[0x0f]	389	1			T61	1		T1	2		T64	1
valid_sources[0x10]	464	1			T117	2		T221	2		T40	35
valid_sources[0x11]	466	1			T64	1		T40	74		T41	45
valid_sources[0x12]	521	1			T1	1		T64	2		T117	1
valid_sources[0x13]	388	1			T1	2		T40	43		T41	21
valid_sources[0x14]	423	1			T221	2		T40	42		T41	45
valid_sources[0x15]	430	1			T1	2		T64	1		T117	1
valid_sources[0x16]	353	1			T61	2		T117	1		T221	1
valid_sources[0x17]	365	1			T61	1		T1	1		T64	1
valid_sources[0x18]	467	1			T1	1		T221	1		T40	78
valid_sources[0x19]	397	1			T61	2		T1	1		T64	1
valid_sources[0x1a]	434	1			T64	2		T40	40		T41	24
valid_sources[0x1b]	365	1			T1	1		T117	1		T40	30
valid_sources[0x1c]	340	1			T61	3		T40	52		T41	11
valid_sources[0x1d]	378	1			T64	3		T40	42		T41	22
valid_sources[0x1e]	303	1			T61	1		T40	29		T41	49
valid_sources[0x1f]	492	1			T1	3		T64	2		T40	43
valid_sources[0x20]	500	1			T40	54		T41	68		T249	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25150334

1

T4

2146

T5

55266

T6

3461

values[0x0]

all_enables

biggest_size

9655675

1

T4

3131

T5

43113

T6

3950

values[0x1]

all_enables

biggest_size

5341

1

T61

28

T1

27

T64

23