| SCORE |
LINE |
COND |
TOGGLE |
FSM |
BRANCH |
ASSERT |
GROUP |
|
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
| 40.66 |
40.66 |
44.90 |
44.90 |
43.07 |
43.07 |
31.34 |
31.34 |
|
|
57.96 |
57.96 |
59.44 |
59.44 |
7.24 |
7.24 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.897063511 |
| 51.50 |
10.84 |
53.06 |
8.16 |
52.13 |
9.06 |
35.23 |
3.89 |
|
|
65.78 |
7.82 |
85.66 |
26.22 |
17.11 |
9.87 |
/workspace/coverage/default/1.chip_jtag_csr_rw.1448946453 |
| 57.53 |
6.04 |
65.63 |
12.58 |
60.56 |
8.42 |
39.09 |
3.86 |
|
|
77.14 |
11.35 |
85.66 |
0.00 |
17.11 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.3514453211 |
| 63.24 |
5.71 |
77.13 |
11.50 |
66.64 |
6.08 |
43.51 |
4.42 |
|
|
80.48 |
3.34 |
90.21 |
4.55 |
21.49 |
4.39 |
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.425971458 |
| 68.24 |
5.00 |
77.18 |
0.04 |
66.69 |
0.05 |
44.02 |
0.51 |
|
|
80.49 |
0.01 |
90.21 |
0.00 |
50.88 |
29.39 |
/workspace/coverage/default/1.chip_sw_alert_test.4006042875 |
| 71.12 |
2.88 |
78.36 |
1.19 |
68.54 |
1.85 |
45.06 |
1.04 |
|
|
81.83 |
1.34 |
90.21 |
0.00 |
62.72 |
11.84 |
/workspace/coverage/default/1.chip_sw_alert_handler_entropy.1095795370 |
| 73.82 |
2.70 |
78.36 |
0.00 |
68.54 |
0.00 |
61.07 |
16.01 |
|
|
81.83 |
0.00 |
90.21 |
0.00 |
62.94 |
0.22 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.1930292941 |
| 75.90 |
2.07 |
82.09 |
3.72 |
72.55 |
4.00 |
61.70 |
0.64 |
|
|
85.69 |
3.86 |
90.21 |
0.00 |
63.16 |
0.22 |
/workspace/coverage/default/2.chip_jtag_csr_rw.1792809725 |
| 77.32 |
1.42 |
82.29 |
0.20 |
72.60 |
0.05 |
69.60 |
7.89 |
|
|
85.70 |
0.02 |
90.56 |
0.35 |
63.16 |
0.00 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1319711536 |
| 78.44 |
1.12 |
83.61 |
1.32 |
73.79 |
1.18 |
72.21 |
2.62 |
|
|
86.74 |
1.04 |
90.91 |
0.35 |
63.38 |
0.22 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.1883919176 |
| 79.51 |
1.07 |
85.10 |
1.50 |
76.19 |
2.41 |
72.38 |
0.16 |
|
|
89.11 |
2.37 |
90.91 |
0.00 |
63.38 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.517252666 |
| 80.37 |
0.86 |
86.07 |
0.97 |
77.10 |
0.91 |
73.87 |
1.49 |
|
|
89.81 |
0.70 |
90.91 |
0.00 |
64.47 |
1.10 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2265402335 |
| 81.17 |
0.80 |
87.31 |
1.23 |
78.09 |
0.99 |
75.26 |
1.39 |
|
|
90.98 |
1.17 |
90.91 |
0.00 |
64.47 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.2340719258 |
| 81.96 |
0.79 |
87.78 |
0.47 |
78.28 |
0.19 |
75.27 |
0.01 |
|
|
91.19 |
0.21 |
94.76 |
3.85 |
64.47 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.4211241545 |
| 82.59 |
0.63 |
88.43 |
0.65 |
78.86 |
0.58 |
75.76 |
0.49 |
|
|
91.88 |
0.69 |
95.28 |
0.52 |
65.35 |
0.88 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1729631170 |
| 83.21 |
0.62 |
89.33 |
0.90 |
79.47 |
0.61 |
77.48 |
1.72 |
|
|
92.36 |
0.48 |
95.28 |
0.00 |
65.35 |
0.00 |
/workspace/coverage/default/0.chip_sw_gpio_smoketest.50334111 |
| 83.73 |
0.52 |
89.34 |
0.01 |
79.47 |
0.01 |
80.57 |
3.09 |
|
|
92.36 |
0.00 |
95.28 |
0.00 |
65.35 |
0.00 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.1251061379 |
| 84.16 |
0.43 |
89.89 |
0.55 |
79.95 |
0.47 |
81.66 |
1.08 |
|
|
92.82 |
0.46 |
95.28 |
0.00 |
65.35 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.1408567926 |
| 84.49 |
0.33 |
89.89 |
0.00 |
79.95 |
0.00 |
81.66 |
0.01 |
|
|
92.82 |
0.00 |
95.28 |
0.00 |
67.32 |
1.97 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1794592604 |
| 84.82 |
0.33 |
90.03 |
0.14 |
79.99 |
0.05 |
82.74 |
1.08 |
|
|
92.84 |
0.02 |
95.98 |
0.70 |
67.32 |
0.00 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.389505439 |
| 85.11 |
0.29 |
90.06 |
0.03 |
80.00 |
0.01 |
82.75 |
0.01 |
|
|
92.84 |
0.01 |
96.15 |
0.17 |
68.86 |
1.54 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1656531459 |
| 85.32 |
0.21 |
90.21 |
0.16 |
80.07 |
0.07 |
83.35 |
0.60 |
|
|
92.89 |
0.05 |
96.50 |
0.35 |
68.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3613257595 |
| 85.50 |
0.18 |
90.24 |
0.02 |
80.14 |
0.07 |
84.18 |
0.83 |
|
|
93.05 |
0.16 |
96.50 |
0.00 |
68.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.344710409 |
| 85.67 |
0.17 |
90.25 |
0.01 |
80.14 |
0.00 |
84.99 |
0.81 |
|
|
93.05 |
0.00 |
96.50 |
0.00 |
69.08 |
0.22 |
/workspace/coverage/default/0.chip_jtag_csr_rw.552193988 |
| 85.82 |
0.15 |
90.45 |
0.21 |
80.46 |
0.32 |
85.34 |
0.36 |
|
|
93.05 |
0.00 |
96.50 |
0.00 |
69.08 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2980359240 |
| 85.96 |
0.14 |
90.52 |
0.07 |
80.57 |
0.10 |
85.91 |
0.57 |
|
|
93.15 |
0.10 |
96.50 |
0.00 |
69.08 |
0.00 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2745636743 |
| 86.09 |
0.14 |
90.52 |
0.00 |
80.57 |
0.00 |
86.75 |
0.83 |
|
|
93.15 |
0.00 |
96.50 |
0.00 |
69.08 |
0.00 |
/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.4162767126 |
| 86.22 |
0.13 |
91.02 |
0.50 |
80.63 |
0.06 |
86.93 |
0.19 |
|
|
93.16 |
0.01 |
96.50 |
0.00 |
69.08 |
0.00 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3892948486 |
| 86.34 |
0.12 |
91.04 |
0.02 |
80.94 |
0.31 |
86.95 |
0.02 |
|
|
93.52 |
0.36 |
96.50 |
0.00 |
69.08 |
0.00 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1297082909 |
| 86.43 |
0.10 |
91.16 |
0.12 |
81.18 |
0.24 |
86.95 |
0.00 |
|
|
93.73 |
0.21 |
96.50 |
0.00 |
69.08 |
0.00 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.2776115431 |
| 86.52 |
0.09 |
91.24 |
0.07 |
81.22 |
0.04 |
86.96 |
0.01 |
|
|
93.75 |
0.02 |
96.68 |
0.17 |
69.30 |
0.22 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.2366467584 |
| 86.61 |
0.09 |
91.30 |
0.07 |
81.26 |
0.04 |
86.96 |
0.00 |
|
|
93.79 |
0.04 |
96.85 |
0.17 |
69.52 |
0.22 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.3182960238 |
| 86.70 |
0.09 |
91.30 |
0.00 |
81.26 |
0.00 |
87.48 |
0.52 |
|
|
93.79 |
0.00 |
96.85 |
0.00 |
69.52 |
0.00 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1455749416 |
| 86.78 |
0.08 |
91.31 |
0.01 |
81.47 |
0.21 |
87.48 |
0.00 |
|
|
94.04 |
0.24 |
96.85 |
0.00 |
69.52 |
0.00 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.580589083 |
| 86.85 |
0.07 |
91.32 |
0.01 |
81.49 |
0.02 |
87.49 |
0.01 |
|
|
94.04 |
0.01 |
97.03 |
0.17 |
69.74 |
0.22 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.1828002156 |
| 86.92 |
0.07 |
91.32 |
0.01 |
81.51 |
0.01 |
87.50 |
0.01 |
|
|
94.05 |
0.01 |
97.20 |
0.17 |
69.96 |
0.22 |
/workspace/coverage/default/45.chip_sw_all_escalation_resets.1327903404 |
| 86.99 |
0.07 |
91.32 |
0.00 |
81.51 |
0.01 |
87.91 |
0.42 |
|
|
94.05 |
0.00 |
97.20 |
0.00 |
69.96 |
0.00 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.3771813713 |
| 87.05 |
0.06 |
91.33 |
0.01 |
81.53 |
0.02 |
88.07 |
0.16 |
|
|
94.05 |
0.00 |
97.38 |
0.17 |
69.96 |
0.00 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.3821377379 |
| 87.10 |
0.05 |
91.33 |
0.00 |
81.53 |
0.00 |
88.39 |
0.31 |
|
|
94.05 |
0.00 |
97.38 |
0.00 |
69.96 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.224272947 |
| 87.15 |
0.05 |
91.33 |
0.00 |
81.53 |
0.00 |
88.68 |
0.30 |
|
|
94.05 |
0.00 |
97.38 |
0.00 |
69.96 |
0.00 |
/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.2395489892 |
| 87.20 |
0.05 |
91.33 |
0.00 |
81.53 |
0.00 |
88.75 |
0.07 |
|
|
94.05 |
0.00 |
97.38 |
0.00 |
70.18 |
0.22 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.328861689 |
| 87.25 |
0.05 |
91.43 |
0.10 |
81.62 |
0.09 |
88.75 |
0.00 |
|
|
94.14 |
0.09 |
97.38 |
0.00 |
70.18 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.2481333563 |
| 87.30 |
0.05 |
91.43 |
0.00 |
81.65 |
0.03 |
88.78 |
0.02 |
|
|
94.15 |
0.01 |
97.38 |
0.00 |
70.39 |
0.22 |
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1663843576 |
| 87.34 |
0.04 |
91.43 |
0.00 |
81.65 |
0.00 |
88.80 |
0.03 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
70.61 |
0.22 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.2680513282 |
| 87.38 |
0.04 |
91.43 |
0.00 |
81.65 |
0.00 |
88.83 |
0.03 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
70.83 |
0.22 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.2067679377 |
| 87.42 |
0.04 |
91.46 |
0.03 |
81.65 |
0.00 |
89.05 |
0.22 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
70.83 |
0.00 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.4131755134 |
| 87.46 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.07 |
0.02 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
71.05 |
0.22 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3675158095 |
| 87.50 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.08 |
0.02 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
71.27 |
0.22 |
/workspace/coverage/default/36.chip_sw_all_escalation_resets.577975387 |
| 87.54 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.10 |
0.01 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
71.49 |
0.22 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.2187935910 |
| 87.58 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.01 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
71.71 |
0.22 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.348761848 |
| 87.61 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.01 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
71.93 |
0.22 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.2491542396 |
| 87.65 |
0.04 |
91.46 |
0.00 |
81.65 |
0.01 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
72.15 |
0.22 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.2365704985 |
| 87.69 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.01 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
72.37 |
0.22 |
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3743561453 |
| 87.72 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
72.59 |
0.22 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2334557720 |
| 87.76 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
72.81 |
0.22 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.1335262550 |
| 87.80 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
73.03 |
0.22 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3560267897 |
| 87.83 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
73.25 |
0.22 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.1971409254 |
| 87.87 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
73.46 |
0.22 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.4237102201 |
| 87.91 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
73.68 |
0.22 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1426143957 |
| 87.94 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
73.90 |
0.22 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.4044272371 |
| 87.98 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
74.12 |
0.22 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2806405632 |
| 88.02 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
74.34 |
0.22 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.678816535 |
| 88.05 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
74.56 |
0.22 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.3411933467 |
| 88.09 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
74.78 |
0.22 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3779651895 |
| 88.13 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
75.00 |
0.22 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2394636195 |
| 88.16 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
75.22 |
0.22 |
/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1690797726 |
| 88.20 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
75.44 |
0.22 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.4149122537 |
| 88.23 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
75.66 |
0.22 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.558797607 |
| 88.27 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
75.88 |
0.22 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.3190820702 |
| 88.31 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
76.10 |
0.22 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.663757734 |
| 88.34 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
76.32 |
0.22 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2366285314 |
| 88.38 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
76.54 |
0.22 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3542557095 |
| 88.42 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
76.75 |
0.22 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2310819662 |
| 88.45 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
76.97 |
0.22 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.664451224 |
| 88.49 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
77.19 |
0.22 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.2693698622 |
| 88.53 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
77.41 |
0.22 |
/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1663919648 |
| 88.56 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
77.63 |
0.22 |
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.475222130 |
| 88.60 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
77.85 |
0.22 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.2293404381 |
| 88.64 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
78.07 |
0.22 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.660748518 |
| 88.67 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
78.29 |
0.22 |
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1557181797 |
| 88.71 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
78.51 |
0.22 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.2180657938 |
| 88.75 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
78.73 |
0.22 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.998460690 |
| 88.78 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
78.95 |
0.22 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.2338121666 |
| 88.82 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
79.17 |
0.22 |
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2302870110 |
| 88.86 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
79.39 |
0.22 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.3320378298 |
| 88.89 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
79.61 |
0.22 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1648334229 |
| 88.93 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
79.82 |
0.22 |
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3537680296 |
| 88.97 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
80.04 |
0.22 |
/workspace/coverage/default/47.chip_sw_all_escalation_resets.2964164641 |
| 89.00 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
80.26 |
0.22 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.2846773116 |
| 89.04 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
80.48 |
0.22 |
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2014736738 |
| 89.08 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
80.70 |
0.22 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.2861979553 |
| 89.11 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
80.92 |
0.22 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.2751167640 |
| 89.15 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
81.14 |
0.22 |
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2386604172 |
| 89.19 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
81.36 |
0.22 |
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.269677592 |
| 89.22 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
81.58 |
0.22 |
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1824238013 |
| 89.26 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
81.80 |
0.22 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.3516341477 |
| 89.29 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
82.02 |
0.22 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.1229673525 |
| 89.33 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
82.24 |
0.22 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.3447555678 |
| 89.37 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
82.46 |
0.22 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.479937528 |
| 89.40 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
82.68 |
0.22 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.2911373543 |
| 89.44 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
82.89 |
0.22 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2134057863 |
| 89.48 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
83.11 |
0.22 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.930477082 |
| 89.51 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
83.33 |
0.22 |
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1441725777 |
| 89.55 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
83.55 |
0.22 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.2826664155 |
| 89.59 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
83.77 |
0.22 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3819859945 |
| 89.62 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
83.99 |
0.22 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.2257155005 |
| 89.66 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
84.21 |
0.22 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.4085533151 |
| 89.70 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
84.43 |
0.22 |
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2741445742 |
| 89.73 |
0.04 |
91.46 |
0.00 |
81.65 |
0.00 |
89.11 |
0.00 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
84.65 |
0.22 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.1304706598 |
| 89.77 |
0.03 |
91.46 |
0.00 |
81.65 |
0.00 |
89.31 |
0.20 |
|
|
94.15 |
0.00 |
97.38 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.4255979778 |
| 89.80 |
0.03 |
91.46 |
0.00 |
81.65 |
0.00 |
89.31 |
0.00 |
|
|
94.15 |
0.00 |
97.55 |
0.17 |
84.65 |
0.00 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.1501691385 |
| 89.82 |
0.03 |
91.51 |
0.06 |
81.70 |
0.05 |
89.32 |
0.01 |
|
|
94.21 |
0.06 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/2.chip_sw_plic_sw_irq.2432576621 |
| 89.85 |
0.03 |
91.51 |
0.00 |
81.70 |
0.00 |
89.49 |
0.17 |
|
|
94.21 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1478816040 |
| 89.88 |
0.03 |
91.58 |
0.07 |
81.73 |
0.03 |
89.51 |
0.01 |
|
|
94.26 |
0.05 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1942604870 |
| 89.90 |
0.02 |
91.66 |
0.07 |
81.73 |
0.00 |
89.57 |
0.07 |
|
|
94.26 |
0.01 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/2.chip_tap_straps_rma.337291762 |
| 89.93 |
0.02 |
91.66 |
0.00 |
81.88 |
0.15 |
89.57 |
0.00 |
|
|
94.26 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.3044616381 |
| 89.95 |
0.02 |
91.66 |
0.00 |
81.88 |
0.00 |
89.72 |
0.14 |
|
|
94.26 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.836723708 |
| 89.98 |
0.02 |
91.75 |
0.09 |
81.90 |
0.02 |
89.72 |
0.00 |
|
|
94.29 |
0.02 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.880418069 |
| 90.00 |
0.02 |
91.80 |
0.06 |
81.96 |
0.06 |
89.72 |
0.00 |
|
|
94.30 |
0.02 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.559197298 |
| 90.02 |
0.02 |
91.85 |
0.05 |
82.02 |
0.06 |
89.72 |
0.00 |
|
|
94.32 |
0.02 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.1420140499 |
| 90.04 |
0.02 |
91.96 |
0.11 |
82.03 |
0.01 |
89.72 |
0.01 |
|
|
94.33 |
0.01 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.266604229 |
| 90.06 |
0.02 |
91.99 |
0.02 |
82.08 |
0.05 |
89.74 |
0.02 |
|
|
94.35 |
0.02 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.515286327 |
| 90.08 |
0.02 |
92.00 |
0.01 |
82.12 |
0.03 |
89.80 |
0.06 |
|
|
94.37 |
0.02 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.1914338045 |
| 90.10 |
0.02 |
92.00 |
0.00 |
82.12 |
0.00 |
89.90 |
0.11 |
|
|
94.37 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.304653059 |
| 90.11 |
0.01 |
92.00 |
0.00 |
82.12 |
0.00 |
89.99 |
0.08 |
|
|
94.37 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1496350253 |
| 90.13 |
0.01 |
92.00 |
0.00 |
82.20 |
0.08 |
89.99 |
0.00 |
|
|
94.37 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.3147483604 |
| 90.14 |
0.01 |
92.02 |
0.02 |
82.22 |
0.02 |
90.00 |
0.01 |
|
|
94.39 |
0.02 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/28.chip_sw_all_escalation_resets.621140095 |
| 90.15 |
0.01 |
92.02 |
0.00 |
82.28 |
0.06 |
90.00 |
0.00 |
|
|
94.39 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.3256851836 |
| 90.16 |
0.01 |
92.02 |
0.00 |
82.28 |
0.00 |
90.06 |
0.06 |
|
|
94.39 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.3879634470 |
| 90.17 |
0.01 |
92.04 |
0.02 |
82.28 |
0.01 |
90.06 |
0.01 |
|
|
94.41 |
0.02 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2967072299 |
| 90.18 |
0.01 |
92.04 |
0.00 |
82.32 |
0.04 |
90.08 |
0.02 |
|
|
94.41 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/1.chip_sw_gpio.637468281 |
| 90.18 |
0.01 |
92.04 |
0.00 |
82.37 |
0.05 |
90.08 |
0.00 |
|
|
94.41 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.3620639251 |
| 90.19 |
0.01 |
92.04 |
0.00 |
82.37 |
0.01 |
90.12 |
0.04 |
|
|
94.41 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3768127434 |
| 90.20 |
0.01 |
92.04 |
0.00 |
82.37 |
0.00 |
90.16 |
0.04 |
|
|
94.41 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3313816361 |
| 90.21 |
0.01 |
92.04 |
0.00 |
82.37 |
0.00 |
90.20 |
0.04 |
|
|
94.41 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/1.chip_sw_flash_init.1277975233 |
| 90.21 |
0.01 |
92.08 |
0.03 |
82.38 |
0.01 |
90.20 |
0.00 |
|
|
94.41 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.319950697 |
| 90.22 |
0.01 |
92.08 |
0.00 |
82.38 |
0.00 |
90.24 |
0.04 |
|
|
94.41 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.3051782274 |
| 90.22 |
0.01 |
92.08 |
0.00 |
82.41 |
0.03 |
90.24 |
0.00 |
|
|
94.42 |
0.01 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2988204626 |
| 90.23 |
0.01 |
92.08 |
0.00 |
82.41 |
0.00 |
90.28 |
0.04 |
|
|
94.42 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.116655921 |
| 90.24 |
0.01 |
92.09 |
0.01 |
82.42 |
0.02 |
90.29 |
0.01 |
|
|
94.42 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.888204540 |
| 90.24 |
0.01 |
92.09 |
0.00 |
82.45 |
0.03 |
90.29 |
0.00 |
|
|
94.42 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.1326306033 |
| 90.25 |
0.01 |
92.09 |
0.00 |
82.45 |
0.00 |
90.31 |
0.03 |
|
|
94.42 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3088098437 |
| 90.25 |
0.01 |
92.09 |
0.00 |
82.46 |
0.01 |
90.33 |
0.02 |
|
|
94.42 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.3454214659 |
| 90.25 |
0.01 |
92.09 |
0.00 |
82.46 |
0.00 |
90.35 |
0.02 |
|
|
94.43 |
0.01 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2317565489 |
| 90.26 |
0.01 |
92.09 |
0.01 |
82.47 |
0.01 |
90.35 |
0.01 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_pattgen_ios.2903724442 |
| 90.26 |
0.01 |
92.09 |
0.00 |
82.49 |
0.02 |
90.35 |
0.00 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3137329920 |
| 90.26 |
0.01 |
92.09 |
0.00 |
82.49 |
0.01 |
90.37 |
0.01 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3026935172 |
| 90.27 |
0.01 |
92.09 |
0.00 |
82.49 |
0.00 |
90.39 |
0.02 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/1.chip_sw_kmac_entropy.2850971062 |
| 90.27 |
0.01 |
92.10 |
0.01 |
82.50 |
0.01 |
90.39 |
0.01 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3589682656 |
| 90.27 |
0.01 |
92.10 |
0.00 |
82.50 |
0.00 |
90.41 |
0.02 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.3326860475 |
| 90.28 |
0.01 |
92.10 |
0.00 |
82.52 |
0.02 |
90.41 |
0.00 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.358021744 |
| 90.28 |
0.01 |
92.10 |
0.00 |
82.52 |
0.00 |
90.43 |
0.02 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.183390105 |
| 90.28 |
0.01 |
92.10 |
0.01 |
82.53 |
0.01 |
90.43 |
0.01 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.2314943249 |
| 90.28 |
0.01 |
92.11 |
0.01 |
82.53 |
0.01 |
90.44 |
0.01 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.4022793813 |
| 90.29 |
0.01 |
92.11 |
0.00 |
82.53 |
0.00 |
90.45 |
0.01 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_jtag_mem_access.3868305883 |
| 90.29 |
0.01 |
92.11 |
0.00 |
82.53 |
0.00 |
90.47 |
0.01 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2783942379 |
| 90.29 |
0.01 |
92.11 |
0.00 |
82.54 |
0.01 |
90.47 |
0.00 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4103695206 |
| 90.29 |
0.01 |
92.11 |
0.00 |
82.55 |
0.01 |
90.47 |
0.00 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.888897505 |
| 90.29 |
0.01 |
92.11 |
0.00 |
82.56 |
0.01 |
90.47 |
0.00 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.786818540 |
| 90.30 |
0.01 |
92.11 |
0.00 |
82.56 |
0.00 |
90.48 |
0.01 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1481434918 |
| 90.30 |
0.01 |
92.11 |
0.00 |
82.56 |
0.00 |
90.49 |
0.01 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.2781659636 |
| 90.30 |
0.01 |
92.11 |
0.00 |
82.56 |
0.00 |
90.49 |
0.01 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/1.chip_sw_hmac_enc_idle.1696749420 |
| 90.30 |
0.01 |
92.11 |
0.00 |
82.56 |
0.00 |
90.50 |
0.01 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2723351108 |
| 90.30 |
0.01 |
92.11 |
0.00 |
82.56 |
0.00 |
90.50 |
0.00 |
|
|
94.43 |
0.01 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/1.chip_tap_straps_dev.440174316 |
| 90.30 |
0.01 |
92.11 |
0.00 |
82.57 |
0.01 |
90.50 |
0.00 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.193806949 |
| 90.30 |
0.01 |
92.11 |
0.00 |
82.58 |
0.01 |
90.50 |
0.00 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.421118965 |
| 90.31 |
0.01 |
92.11 |
0.00 |
82.59 |
0.01 |
90.50 |
0.00 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/2.chip_sw_gpio.3647046582 |
| 90.31 |
0.01 |
92.11 |
0.00 |
82.59 |
0.00 |
90.51 |
0.01 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1735007279 |
| 90.31 |
0.01 |
92.11 |
0.00 |
82.59 |
0.00 |
90.52 |
0.01 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.252444062 |
| 90.31 |
0.01 |
92.11 |
0.00 |
82.59 |
0.00 |
90.52 |
0.01 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.2822577417 |
| 90.31 |
0.01 |
92.11 |
0.01 |
82.59 |
0.00 |
90.53 |
0.01 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2447696343 |
| 90.31 |
0.01 |
92.11 |
0.00 |
82.59 |
0.00 |
90.53 |
0.01 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_ast_clk_outputs.753249538 |
| 90.31 |
0.01 |
92.11 |
0.00 |
82.59 |
0.00 |
90.54 |
0.01 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2234777843 |
| 90.31 |
0.01 |
92.11 |
0.00 |
82.59 |
0.00 |
90.54 |
0.01 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.2051566729 |
| 90.31 |
0.01 |
92.11 |
0.00 |
82.59 |
0.00 |
90.55 |
0.01 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2432056919 |
| 90.31 |
0.01 |
92.11 |
0.00 |
82.59 |
0.00 |
90.55 |
0.01 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2937792457 |
| 90.31 |
0.01 |
92.11 |
0.00 |
82.59 |
0.00 |
90.56 |
0.01 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.4272768432 |
| 90.32 |
0.01 |
92.11 |
0.00 |
82.59 |
0.00 |
90.56 |
0.01 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.705929918 |
| 90.32 |
0.01 |
92.11 |
0.00 |
82.59 |
0.00 |
90.56 |
0.01 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.3969123024 |
| 90.32 |
0.01 |
92.11 |
0.00 |
82.59 |
0.00 |
90.57 |
0.01 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2611539745 |
| 90.32 |
0.01 |
92.11 |
0.00 |
82.59 |
0.01 |
90.57 |
0.00 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3315151442 |
| 90.32 |
0.01 |
92.11 |
0.00 |
82.59 |
0.01 |
90.57 |
0.00 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3051703210 |
| 90.32 |
0.01 |
92.11 |
0.00 |
82.60 |
0.01 |
90.57 |
0.00 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.488542953 |
| 90.32 |
0.01 |
92.11 |
0.00 |
82.60 |
0.00 |
90.57 |
0.01 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.567677080 |
| 90.32 |
0.01 |
92.11 |
0.00 |
82.60 |
0.00 |
90.57 |
0.01 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.63715599 |
| 90.32 |
0.01 |
92.11 |
0.00 |
82.60 |
0.00 |
90.58 |
0.01 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.rom_raw_unlock.174527983 |
| 90.32 |
0.01 |
92.11 |
0.00 |
82.60 |
0.00 |
90.58 |
0.01 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.4131015662 |
| 90.32 |
0.01 |
92.11 |
0.00 |
82.60 |
0.00 |
90.58 |
0.01 |
|
|
94.43 |
0.00 |
97.55 |
0.00 |
84.65 |
0.00 |
/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3381331535 |
| Name |
| /workspace/coverage/default/0.chip_sival_flash_info_access.1512303238 |
| /workspace/coverage/default/0.chip_sw_aes_enc.4259247720 |
| /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.4221382232 |
| /workspace/coverage/default/0.chip_sw_aes_entropy.160870424 |
| /workspace/coverage/default/0.chip_sw_aes_idle.1722813986 |
| /workspace/coverage/default/0.chip_sw_aes_masking_off.3352682687 |
| /workspace/coverage/default/0.chip_sw_aes_smoketest.1228095483 |
| /workspace/coverage/default/0.chip_sw_alert_handler_entropy.3270179782 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1664047488 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.40870161 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.385432254 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1212224062 |
| /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.384746527 |
| /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.187216194 |
| /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3661840376 |
| /workspace/coverage/default/0.chip_sw_alert_test.2107876674 |
| /workspace/coverage/default/0.chip_sw_aon_timer_irq.2068025238 |
| /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3951796693 |
| /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.3657786843 |
| /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.305440904 |
| /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1495085433 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2873137642 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2195779023 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2413728963 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1159258035 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3124864763 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2702177633 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter.3699194260 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3758802897 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1028705891 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1314473589 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.3936516169 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1814867630 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3309280292 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.680474768 |
| /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.1028206398 |
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| /workspace/coverage/default/64.chip_sw_all_escalation_resets.1918462543 |
| /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3826436229 |
| /workspace/coverage/default/65.chip_sw_all_escalation_resets.3803540433 |
| /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3108955999 |
| /workspace/coverage/default/67.chip_sw_all_escalation_resets.472496839 |
| /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.4055058194 |
| /workspace/coverage/default/69.chip_sw_all_escalation_resets.3093913181 |
| /workspace/coverage/default/7.chip_sw_all_escalation_resets.946892940 |
| /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.1373410928 |
| /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2019130377 |
| /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2649339021 |
| /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.975856442 |
| /workspace/coverage/default/70.chip_sw_all_escalation_resets.236193874 |
| /workspace/coverage/default/71.chip_sw_all_escalation_resets.2396085709 |
| /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.590951 |
| /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3076723001 |
| /workspace/coverage/default/73.chip_sw_all_escalation_resets.3106975567 |
| /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2341754071 |
| /workspace/coverage/default/74.chip_sw_all_escalation_resets.1360674717 |
| /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1874764156 |
| /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2046060242 |
| /workspace/coverage/default/77.chip_sw_all_escalation_resets.3550915716 |
| /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2124170358 |
| /workspace/coverage/default/78.chip_sw_all_escalation_resets.424181287 |
| /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.4131044809 |
| /workspace/coverage/default/79.chip_sw_all_escalation_resets.2450581348 |
| /workspace/coverage/default/8.chip_sw_all_escalation_resets.3909132720 |
| /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2041155968 |
| /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1949754521 |
| /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.4179470587 |
| /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2118179033 |
| /workspace/coverage/default/80.chip_sw_all_escalation_resets.4187020626 |
| /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.4034411239 |
| /workspace/coverage/default/81.chip_sw_all_escalation_resets.3228176915 |
| /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3130544359 |
| /workspace/coverage/default/82.chip_sw_all_escalation_resets.142836284 |
| /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3188277407 |
| /workspace/coverage/default/83.chip_sw_all_escalation_resets.181964381 |
| /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1456842833 |
| /workspace/coverage/default/84.chip_sw_all_escalation_resets.137932889 |
| /workspace/coverage/default/85.chip_sw_all_escalation_resets.4102421087 |
| /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1895256925 |
| /workspace/coverage/default/86.chip_sw_all_escalation_resets.3818373254 |
| /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1764599091 |
| /workspace/coverage/default/87.chip_sw_all_escalation_resets.199533931 |
| /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3689940213 |
| /workspace/coverage/default/88.chip_sw_all_escalation_resets.4009513218 |
| /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2734178287 |
| /workspace/coverage/default/89.chip_sw_all_escalation_resets.3167484492 |
| /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1787792486 |
| /workspace/coverage/default/9.chip_sw_all_escalation_resets.915234991 |
| /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.2569686388 |
| /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1035796712 |
| /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.4007493717 |
| /workspace/coverage/default/91.chip_sw_all_escalation_resets.4252728227 |
| /workspace/coverage/default/92.chip_sw_all_escalation_resets.461485061 |
| /workspace/coverage/default/93.chip_sw_all_escalation_resets.641711386 |
| /workspace/coverage/default/94.chip_sw_all_escalation_resets.267385976 |
| /workspace/coverage/default/95.chip_sw_all_escalation_resets.1331941619 |
| /workspace/coverage/default/96.chip_sw_all_escalation_resets.2820777608 |
| /workspace/coverage/default/97.chip_sw_all_escalation_resets.1717369429 |
| /workspace/coverage/default/99.chip_sw_all_escalation_resets.4049159143 |
| /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.3728004525 |
| /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.772270036 |
| /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.451408801 |
| /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1363544344 |
| /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.568917921 |
| /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3150757964 |
| /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3547711923 |
| /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.250181597 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T4 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.443652110 |
|
|
Jul 19 06:49:48 PM PDT 24 |
Jul 19 06:54:23 PM PDT 24 |
2827331225 ps |
| T5 |
/workspace/coverage/default/0.chip_sw_usbdev_config_host.1429081725 |
|
|
Jul 19 06:38:53 PM PDT 24 |
Jul 19 07:12:29 PM PDT 24 |
7789140358 ps |
| T6 |
/workspace/coverage/default/0.chip_sw_gpio_smoketest.50334111 |
|
|
Jul 19 06:40:05 PM PDT 24 |
Jul 19 06:45:32 PM PDT 24 |
2426831796 ps |
| T18 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2745636743 |
|
|
Jul 19 06:45:11 PM PDT 24 |
Jul 19 06:56:54 PM PDT 24 |
5040655609 ps |
| T19 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3675158095 |
|
|
Jul 19 07:09:55 PM PDT 24 |
Jul 19 07:16:48 PM PDT 24 |
4191597468 ps |
| T20 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.897063511 |
|
|
Jul 19 07:08:47 PM PDT 24 |
Jul 19 07:18:54 PM PDT 24 |
6071977796 ps |
| T130 |
/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.65428483 |
|
|
Jul 19 06:52:20 PM PDT 24 |
Jul 19 06:57:07 PM PDT 24 |
2764412104 ps |
| T131 |
/workspace/coverage/default/2.chip_sw_aes_entropy.1987901161 |
|
|
Jul 19 06:56:11 PM PDT 24 |
Jul 19 07:02:24 PM PDT 24 |
2897905246 ps |
| T132 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.4119968429 |
|
|
Jul 19 07:06:42 PM PDT 24 |
Jul 19 07:30:54 PM PDT 24 |
7906013014 ps |
| T59 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.888227904 |
|
|
Jul 19 07:02:55 PM PDT 24 |
Jul 19 07:15:31 PM PDT 24 |
4396509430 ps |
| T250 |
/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3535122787 |
|
|
Jul 19 07:04:59 PM PDT 24 |
Jul 19 07:29:29 PM PDT 24 |
8844523914 ps |
| T79 |
/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.2395489892 |
|
|
Jul 19 07:08:42 PM PDT 24 |
Jul 19 08:06:05 PM PDT 24 |
13725979280 ps |
| T125 |
/workspace/coverage/default/1.chip_tap_straps_prod.634418574 |
|
|
Jul 19 06:51:14 PM PDT 24 |
Jul 19 07:09:40 PM PDT 24 |
10675211281 ps |
| T187 |
/workspace/coverage/default/2.chip_sw_plic_sw_irq.2432576621 |
|
|
Jul 19 06:59:57 PM PDT 24 |
Jul 19 07:03:48 PM PDT 24 |
2672302568 ps |
| T43 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.344710409 |
|
|
Jul 19 06:42:18 PM PDT 24 |
Jul 19 06:55:35 PM PDT 24 |
5178881520 ps |
| T71 |
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3743561453 |
|
|
Jul 19 07:09:30 PM PDT 24 |
Jul 19 07:17:06 PM PDT 24 |
3768875918 ps |
| T44 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.158510760 |
|
|
Jul 19 06:58:48 PM PDT 24 |
Jul 19 07:23:52 PM PDT 24 |
8748721298 ps |
| T72 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2265402335 |
|
|
Jul 19 07:06:44 PM PDT 24 |
Jul 19 07:12:20 PM PDT 24 |
3865920616 ps |
| T272 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2626482032 |
|
|
Jul 19 07:09:13 PM PDT 24 |
Jul 19 07:16:36 PM PDT 24 |
3938587598 ps |
| T83 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.1251061379 |
|
|
Jul 19 06:44:30 PM PDT 24 |
Jul 19 07:10:13 PM PDT 24 |
7449811440 ps |
| T122 |
/workspace/coverage/default/28.chip_sw_all_escalation_resets.621140095 |
|
|
Jul 19 07:05:43 PM PDT 24 |
Jul 19 07:13:43 PM PDT 24 |
4504707604 ps |
| T283 |
/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.472016528 |
|
|
Jul 19 07:09:41 PM PDT 24 |
Jul 19 07:14:23 PM PDT 24 |
2903354792 ps |
| T181 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.188332086 |
|
|
Jul 19 07:09:37 PM PDT 24 |
Jul 19 07:20:52 PM PDT 24 |
5152365672 ps |
| T285 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3051703210 |
|
|
Jul 19 06:39:52 PM PDT 24 |
Jul 19 06:52:50 PM PDT 24 |
4436608276 ps |
| T543 |
/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2985779893 |
|
|
Jul 19 06:49:20 PM PDT 24 |
Jul 19 07:00:03 PM PDT 24 |
4640940960 ps |
| T34 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3613257595 |
|
|
Jul 19 06:43:54 PM PDT 24 |
Jul 19 06:49:39 PM PDT 24 |
2785972424 ps |
| T67 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.198771168 |
|
|
Jul 19 06:54:43 PM PDT 24 |
Jul 19 07:01:27 PM PDT 24 |
4574986398 ps |
| T68 |
/workspace/coverage/default/2.chip_sw_ast_clk_outputs.3813560427 |
|
|
Jul 19 07:01:58 PM PDT 24 |
Jul 19 07:19:42 PM PDT 24 |
7197904200 ps |
| T199 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.3821377379 |
|
|
Jul 19 06:41:35 PM PDT 24 |
Jul 19 06:51:41 PM PDT 24 |
5852026592 ps |
| T198 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.328861689 |
|
|
Jul 19 07:09:05 PM PDT 24 |
Jul 19 07:18:11 PM PDT 24 |
3874081928 ps |
| T209 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1314473589 |
|
|
Jul 19 06:41:40 PM PDT 24 |
Jul 19 06:53:33 PM PDT 24 |
5077000520 ps |
| T69 |
/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.3859203623 |
|
|
Jul 19 06:53:07 PM PDT 24 |
Jul 19 07:01:58 PM PDT 24 |
5826888130 ps |
| T192 |
/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2925978446 |
|
|
Jul 19 06:37:49 PM PDT 24 |
Jul 19 06:45:58 PM PDT 24 |
3712377798 ps |
| T70 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3768127434 |
|
|
Jul 19 06:42:50 PM PDT 24 |
Jul 19 07:26:03 PM PDT 24 |
24024083233 ps |
| T314 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.305440904 |
|
|
Jul 19 06:43:28 PM PDT 24 |
Jul 19 06:57:05 PM PDT 24 |
9703182416 ps |
| T207 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.2187935910 |
|
|
Jul 19 07:11:33 PM PDT 24 |
Jul 19 07:22:21 PM PDT 24 |
5121910880 ps |
| T315 |
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1787792486 |
|
|
Jul 19 07:05:30 PM PDT 24 |
Jul 19 07:10:52 PM PDT 24 |
3915827196 ps |
| T73 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3209453912 |
|
|
Jul 19 07:00:29 PM PDT 24 |
Jul 19 08:16:14 PM PDT 24 |
25530598976 ps |
| T154 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3428035545 |
|
|
Jul 19 06:55:07 PM PDT 24 |
Jul 19 07:02:52 PM PDT 24 |
4027787764 ps |
| T60 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2808697127 |
|
|
Jul 19 06:47:07 PM PDT 24 |
Jul 19 06:57:12 PM PDT 24 |
4439482684 ps |
| T422 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2156907205 |
|
|
Jul 19 06:41:48 PM PDT 24 |
Jul 19 07:01:28 PM PDT 24 |
5589731610 ps |
| T263 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.888897505 |
|
|
Jul 19 06:42:52 PM PDT 24 |
Jul 19 06:56:09 PM PDT 24 |
4060312928 ps |
| T123 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2783942379 |
|
|
Jul 19 06:42:13 PM PDT 24 |
Jul 19 06:46:05 PM PDT 24 |
2723988817 ps |
| T193 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.2491542396 |
|
|
Jul 19 07:08:54 PM PDT 24 |
Jul 19 07:21:48 PM PDT 24 |
5472968272 ps |
| T156 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1664047488 |
|
|
Jul 19 06:42:27 PM PDT 24 |
Jul 19 07:18:55 PM PDT 24 |
9201917246 ps |
| T21 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1455749416 |
|
|
Jul 19 06:41:50 PM PDT 24 |
Jul 19 06:50:08 PM PDT 24 |
4414900490 ps |
| T102 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.635626009 |
|
|
Jul 19 06:48:05 PM PDT 24 |
Jul 19 06:58:06 PM PDT 24 |
4373012834 ps |
| T22 |
/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3507152012 |
|
|
Jul 19 06:42:05 PM PDT 24 |
Jul 19 06:50:20 PM PDT 24 |
8686796664 ps |
| T23 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.4255979778 |
|
|
Jul 19 06:55:31 PM PDT 24 |
Jul 19 07:00:35 PM PDT 24 |
3528650664 ps |
| T107 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.2067679377 |
|
|
Jul 19 07:10:43 PM PDT 24 |
Jul 19 07:21:32 PM PDT 24 |
6031298150 ps |
| T364 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.2664336822 |
|
|
Jul 19 06:43:23 PM PDT 24 |
Jul 19 06:51:39 PM PDT 24 |
8076297600 ps |
| T54 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.1883919176 |
|
|
Jul 19 06:45:01 PM PDT 24 |
Jul 19 07:57:25 PM PDT 24 |
14356399963 ps |
| T65 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.1212702374 |
|
|
Jul 19 06:43:49 PM PDT 24 |
Jul 19 06:48:39 PM PDT 24 |
2955293238 ps |
| T108 |
/workspace/coverage/default/1.chip_sw_alert_handler_entropy.1095795370 |
|
|
Jul 19 06:45:04 PM PDT 24 |
Jul 19 06:49:53 PM PDT 24 |
3398596437 ps |
| T55 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.728868885 |
|
|
Jul 19 06:45:45 PM PDT 24 |
Jul 19 08:19:50 PM PDT 24 |
17855175008 ps |
| T58 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2019130377 |
|
|
Jul 19 07:05:00 PM PDT 24 |
Jul 19 07:16:33 PM PDT 24 |
8858083659 ps |
| T420 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.3691490199 |
|
|
Jul 19 07:00:03 PM PDT 24 |
Jul 19 07:22:18 PM PDT 24 |
5127842916 ps |
| T61 |
/workspace/coverage/default/1.chip_jtag_mem_access.1028753696 |
|
|
Jul 19 06:41:10 PM PDT 24 |
Jul 19 07:05:19 PM PDT 24 |
14417251800 ps |
| T62 |
/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3880974196 |
|
|
Jul 19 06:49:27 PM PDT 24 |
Jul 19 06:59:12 PM PDT 24 |
5033913794 ps |
| T212 |
/workspace/coverage/default/2.chip_sw_kmac_entropy.338485750 |
|
|
Jul 19 06:55:12 PM PDT 24 |
Jul 19 06:59:28 PM PDT 24 |
2714098468 ps |
| T421 |
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1764599091 |
|
|
Jul 19 07:11:39 PM PDT 24 |
Jul 19 07:18:37 PM PDT 24 |
3073729646 ps |
| T544 |
/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.3350377087 |
|
|
Jul 19 07:06:31 PM PDT 24 |
Jul 19 07:11:31 PM PDT 24 |
3245255284 ps |
| T219 |
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2041155968 |
|
|
Jul 19 07:04:54 PM PDT 24 |
Jul 19 07:56:03 PM PDT 24 |
12286227398 ps |
| T104 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3088098437 |
|
|
Jul 19 06:42:24 PM PDT 24 |
Jul 19 06:53:36 PM PDT 24 |
3722136910 ps |
| T369 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3594918147 |
|
|
Jul 19 06:54:21 PM PDT 24 |
Jul 19 07:39:32 PM PDT 24 |
24647671166 ps |
| T405 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.279799431 |
|
|
Jul 19 06:42:06 PM PDT 24 |
Jul 19 06:45:51 PM PDT 24 |
3065354894 ps |
| T167 |
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1352301218 |
|
|
Jul 19 07:08:07 PM PDT 24 |
Jul 19 07:14:46 PM PDT 24 |
4188174078 ps |
| T208 |
/workspace/coverage/default/1.chip_sw_hmac_enc_idle.1696749420 |
|
|
Jul 19 06:44:12 PM PDT 24 |
Jul 19 06:48:07 PM PDT 24 |
2574064048 ps |
| T213 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.1930292941 |
|
|
Jul 19 06:39:40 PM PDT 24 |
Jul 19 07:50:45 PM PDT 24 |
14157799680 ps |
| T105 |
/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3073831436 |
|
|
Jul 19 07:05:01 PM PDT 24 |
Jul 19 07:13:21 PM PDT 24 |
7231751382 ps |
| T406 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2134057863 |
|
|
Jul 19 07:10:32 PM PDT 24 |
Jul 19 07:17:39 PM PDT 24 |
3729329412 ps |
| T170 |
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2734178287 |
|
|
Jul 19 07:12:04 PM PDT 24 |
Jul 19 07:17:34 PM PDT 24 |
3416414062 ps |
| T228 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.3514453211 |
|
|
Jul 19 06:41:05 PM PDT 24 |
Jul 19 07:03:53 PM PDT 24 |
6206966238 ps |
| T393 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.2826664155 |
|
|
Jul 19 07:09:53 PM PDT 24 |
Jul 19 07:19:55 PM PDT 24 |
5302644060 ps |
| T356 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.267385976 |
|
|
Jul 19 07:11:46 PM PDT 24 |
Jul 19 07:20:10 PM PDT 24 |
4954696324 ps |
| T178 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.2383393572 |
|
|
Jul 19 07:01:18 PM PDT 24 |
Jul 19 07:09:16 PM PDT 24 |
5175841100 ps |
| T74 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.898234852 |
|
|
Jul 19 06:41:10 PM PDT 24 |
Jul 19 06:45:15 PM PDT 24 |
3485981499 ps |
| T57 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.1648416274 |
|
|
Jul 19 06:49:13 PM PDT 24 |
Jul 19 08:03:01 PM PDT 24 |
15738204538 ps |
| T286 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.2650002812 |
|
|
Jul 19 06:57:02 PM PDT 24 |
Jul 19 07:45:46 PM PDT 24 |
10867606212 ps |
| T545 |
/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2038144624 |
|
|
Jul 19 06:40:45 PM PDT 24 |
Jul 19 06:46:21 PM PDT 24 |
2981423140 ps |
| T383 |
/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.786818540 |
|
|
Jul 19 06:48:15 PM PDT 24 |
Jul 19 06:55:41 PM PDT 24 |
4337085292 ps |
| T155 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.1267100493 |
|
|
Jul 19 06:46:53 PM PDT 24 |
Jul 19 07:12:47 PM PDT 24 |
9577121826 ps |
| T546 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3088050953 |
|
|
Jul 19 06:56:52 PM PDT 24 |
Jul 19 07:10:42 PM PDT 24 |
6429574220 ps |
| T373 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.4237102201 |
|
|
Jul 19 07:06:36 PM PDT 24 |
Jul 19 07:16:52 PM PDT 24 |
4875669664 ps |
| T437 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.1971409254 |
|
|
Jul 19 07:06:58 PM PDT 24 |
Jul 19 07:20:02 PM PDT 24 |
6188985732 ps |
| T216 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.2231914868 |
|
|
Jul 19 06:59:52 PM PDT 24 |
Jul 19 07:08:18 PM PDT 24 |
5196784720 ps |
| T217 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3309280292 |
|
|
Jul 19 06:43:14 PM PDT 24 |
Jul 19 06:53:51 PM PDT 24 |
5727381520 ps |
| T231 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.917049426 |
|
|
Jul 19 06:44:01 PM PDT 24 |
Jul 19 06:57:57 PM PDT 24 |
4800906624 ps |
| T266 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.266604229 |
|
|
Jul 19 06:38:53 PM PDT 24 |
Jul 19 06:43:10 PM PDT 24 |
3451340536 ps |
| T188 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3685577724 |
|
|
Jul 19 06:48:43 PM PDT 24 |
Jul 19 07:04:00 PM PDT 24 |
4625627850 ps |
| T161 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3857451065 |
|
|
Jul 19 06:40:55 PM PDT 24 |
Jul 19 07:12:39 PM PDT 24 |
14192862250 ps |
| T438 |
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.4131044809 |
|
|
Jul 19 07:11:29 PM PDT 24 |
Jul 19 07:17:43 PM PDT 24 |
3860826144 ps |
| T106 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1319711536 |
|
|
Jul 19 06:56:03 PM PDT 24 |
Jul 19 08:23:08 PM PDT 24 |
46527378235 ps |
| T75 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1496350253 |
|
|
Jul 19 06:41:00 PM PDT 24 |
Jul 19 06:51:53 PM PDT 24 |
4630162836 ps |
| T173 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.2922184403 |
|
|
Jul 19 06:39:17 PM PDT 24 |
Jul 19 06:56:21 PM PDT 24 |
11309765678 ps |
| T334 |
/workspace/coverage/default/2.rom_keymgr_functest.2235100873 |
|
|
Jul 19 07:01:49 PM PDT 24 |
Jul 19 07:10:34 PM PDT 24 |
4070103928 ps |
| T185 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.830912797 |
|
|
Jul 19 06:39:54 PM PDT 24 |
Jul 19 06:42:10 PM PDT 24 |
2788702477 ps |
| T51 |
/workspace/coverage/default/2.chip_sw_spi_device_tpm.564495690 |
|
|
Jul 19 06:56:29 PM PDT 24 |
Jul 19 07:02:03 PM PDT 24 |
3454729243 ps |
| T265 |
/workspace/coverage/default/0.chip_sival_flash_info_access.1512303238 |
|
|
Jul 19 06:38:17 PM PDT 24 |
Jul 19 06:44:03 PM PDT 24 |
2791554880 ps |
| T477 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2806405632 |
|
|
Jul 19 07:07:21 PM PDT 24 |
Jul 19 07:14:12 PM PDT 24 |
4157800810 ps |
| T80 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.567677080 |
|
|
Jul 19 06:41:13 PM PDT 24 |
Jul 19 06:51:37 PM PDT 24 |
3340803832 ps |
| T214 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3102357681 |
|
|
Jul 19 06:38:41 PM PDT 24 |
Jul 19 07:02:14 PM PDT 24 |
9578884760 ps |
| T379 |
/workspace/coverage/default/2.chip_sw_otbn_randomness.876979100 |
|
|
Jul 19 06:57:34 PM PDT 24 |
Jul 19 07:10:31 PM PDT 24 |
5881412420 ps |
| T370 |
/workspace/coverage/default/6.chip_sw_all_escalation_resets.1466808052 |
|
|
Jul 19 07:04:07 PM PDT 24 |
Jul 19 07:15:09 PM PDT 24 |
6005338986 ps |
| T232 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.691747845 |
|
|
Jul 19 06:44:33 PM PDT 24 |
Jul 19 06:58:34 PM PDT 24 |
4198121560 ps |
| T87 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1470215537 |
|
|
Jul 19 06:43:13 PM PDT 24 |
Jul 19 07:54:43 PM PDT 24 |
18091435938 ps |
| T76 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2662591785 |
|
|
Jul 19 06:58:30 PM PDT 24 |
Jul 19 07:07:26 PM PDT 24 |
3642254404 ps |
| T547 |
/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.3894864421 |
|
|
Jul 19 06:51:47 PM PDT 24 |
Jul 19 06:59:01 PM PDT 24 |
3240443670 ps |
| T433 |
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.614204882 |
|
|
Jul 19 07:03:22 PM PDT 24 |
Jul 19 09:12:28 PM PDT 24 |
27052319230 ps |
| T548 |
/workspace/coverage/default/0.chip_sw_kmac_idle.3081350403 |
|
|
Jul 19 06:42:35 PM PDT 24 |
Jul 19 06:46:22 PM PDT 24 |
2507124170 ps |
| T360 |
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.4007493717 |
|
|
Jul 19 07:04:39 PM PDT 24 |
Jul 19 07:49:55 PM PDT 24 |
13275497776 ps |
| T99 |
/workspace/coverage/default/0.chip_tap_straps_testunlock0.2469499128 |
|
|
Jul 19 06:43:49 PM PDT 24 |
Jul 19 06:52:04 PM PDT 24 |
5593393709 ps |
| T186 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1429417466 |
|
|
Jul 19 06:41:19 PM PDT 24 |
Jul 19 06:43:52 PM PDT 24 |
2463050178 ps |
| T549 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter.4091299429 |
|
|
Jul 19 07:02:54 PM PDT 24 |
Jul 19 07:07:58 PM PDT 24 |
3246080595 ps |
| T550 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3784059074 |
|
|
Jul 19 06:41:37 PM PDT 24 |
Jul 19 06:55:42 PM PDT 24 |
7837652830 ps |
| T160 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2984480608 |
|
|
Jul 19 06:47:36 PM PDT 24 |
Jul 19 08:10:26 PM PDT 24 |
15222259232 ps |
| T260 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.2366467584 |
|
|
Jul 19 06:52:21 PM PDT 24 |
Jul 19 07:01:24 PM PDT 24 |
4844176648 ps |
| T349 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.424181287 |
|
|
Jul 19 07:11:13 PM PDT 24 |
Jul 19 07:23:08 PM PDT 24 |
5303639612 ps |
| T77 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3035310100 |
|
|
Jul 19 06:45:55 PM PDT 24 |
Jul 19 06:56:30 PM PDT 24 |
4406402716 ps |
| T350 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.181964381 |
|
|
Jul 19 07:11:34 PM PDT 24 |
Jul 19 07:21:39 PM PDT 24 |
5737809356 ps |
| T351 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.3220897076 |
|
|
Jul 19 07:04:26 PM PDT 24 |
Jul 19 08:20:28 PM PDT 24 |
15628759127 ps |
| T352 |
/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.655314061 |
|
|
Jul 19 06:38:35 PM PDT 24 |
Jul 19 06:42:55 PM PDT 24 |
4301515615 ps |
| T27 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through.2663930879 |
|
|
Jul 19 06:43:12 PM PDT 24 |
Jul 19 06:53:50 PM PDT 24 |
5873524401 ps |
| T182 |
/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.4162767126 |
|
|
Jul 19 06:53:12 PM PDT 24 |
Jul 19 08:15:27 PM PDT 24 |
44916708796 ps |
| T215 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.4192744653 |
|
|
Jul 19 06:50:03 PM PDT 24 |
Jul 19 06:56:16 PM PDT 24 |
2655754745 ps |
| T353 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.4151628653 |
|
|
Jul 19 06:51:48 PM PDT 24 |
Jul 19 06:54:47 PM PDT 24 |
2571656490 ps |
| T328 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.1278121236 |
|
|
Jul 19 07:05:36 PM PDT 24 |
Jul 19 07:16:37 PM PDT 24 |
4415549988 ps |
| T430 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.3411933467 |
|
|
Jul 19 07:04:51 PM PDT 24 |
Jul 19 07:16:31 PM PDT 24 |
6098076792 ps |
| T377 |
/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2898979936 |
|
|
Jul 19 06:41:42 PM PDT 24 |
Jul 19 07:03:21 PM PDT 24 |
9595750890 ps |
| T551 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3502584879 |
|
|
Jul 19 06:50:46 PM PDT 24 |
Jul 19 06:56:18 PM PDT 24 |
3755735178 ps |
| T552 |
/workspace/coverage/default/2.chip_sw_edn_sw_mode.1901387993 |
|
|
Jul 19 07:00:18 PM PDT 24 |
Jul 19 07:46:01 PM PDT 24 |
11350881170 ps |
| T553 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3660359798 |
|
|
Jul 19 06:42:07 PM PDT 24 |
Jul 19 07:16:53 PM PDT 24 |
8509933127 ps |
| T103 |
/workspace/coverage/default/1.chip_sw_power_idle_load.3242106766 |
|
|
Jul 19 06:52:01 PM PDT 24 |
Jul 19 07:01:47 PM PDT 24 |
4203760960 ps |
| T164 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.1250039553 |
|
|
Jul 19 06:52:52 PM PDT 24 |
Jul 19 07:31:51 PM PDT 24 |
8154552900 ps |
| T435 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.2751167640 |
|
|
Jul 19 07:04:03 PM PDT 24 |
Jul 19 07:18:01 PM PDT 24 |
4911198500 ps |
| T554 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.836723708 |
|
|
Jul 19 06:39:29 PM PDT 24 |
Jul 19 06:44:24 PM PDT 24 |
3550277197 ps |
| T282 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.1529096063 |
|
|
Jul 19 06:36:36 PM PDT 24 |
Jul 19 06:43:47 PM PDT 24 |
5821521716 ps |
| T329 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.3106975567 |
|
|
Jul 19 07:10:48 PM PDT 24 |
Jul 19 07:20:15 PM PDT 24 |
5520384090 ps |
| T218 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.3936516169 |
|
|
Jul 19 06:40:46 PM PDT 24 |
Jul 19 06:49:19 PM PDT 24 |
4344397040 ps |
| T124 |
/workspace/coverage/default/4.chip_tap_straps_dev.578032507 |
|
|
Jul 19 07:02:42 PM PDT 24 |
Jul 19 07:08:14 PM PDT 24 |
3577854311 ps |
| T555 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2627608791 |
|
|
Jul 19 06:46:52 PM PDT 24 |
Jul 19 06:55:55 PM PDT 24 |
3921455846 ps |
| T403 |
/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.87768532 |
|
|
Jul 19 06:55:26 PM PDT 24 |
Jul 19 07:22:01 PM PDT 24 |
11234585275 ps |
| T378 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1449073506 |
|
|
Jul 19 06:56:02 PM PDT 24 |
Jul 19 07:19:07 PM PDT 24 |
12519581736 ps |
| T473 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.982970120 |
|
|
Jul 19 06:48:09 PM PDT 24 |
Jul 19 06:55:11 PM PDT 24 |
2852669256 ps |
| T556 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.3713300098 |
|
|
Jul 19 06:47:26 PM PDT 24 |
Jul 19 06:58:18 PM PDT 24 |
7095223444 ps |
| T371 |
/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.1966226289 |
|
|
Jul 19 07:04:02 PM PDT 24 |
Jul 19 07:11:05 PM PDT 24 |
6469846151 ps |
| T234 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2341754071 |
|
|
Jul 19 07:10:14 PM PDT 24 |
Jul 19 07:17:11 PM PDT 24 |
3852533432 ps |
| T52 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.319950697 |
|
|
Jul 19 06:41:32 PM PDT 24 |
Jul 19 06:47:31 PM PDT 24 |
3139811699 ps |
| T434 |
/workspace/coverage/default/2.chip_sw_aes_masking_off.2191667145 |
|
|
Jul 19 06:57:16 PM PDT 24 |
Jul 19 07:01:29 PM PDT 24 |
3033842780 ps |
| T557 |
/workspace/coverage/default/2.chip_sw_uart_smoketest.3508620123 |
|
|
Jul 19 07:01:00 PM PDT 24 |
Jul 19 07:06:09 PM PDT 24 |
3332279174 ps |
| T558 |
/workspace/coverage/default/2.chip_sw_kmac_idle.1573802507 |
|
|
Jul 19 06:57:21 PM PDT 24 |
Jul 19 07:00:52 PM PDT 24 |
2747363800 ps |
| T559 |
/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.421291369 |
|
|
Jul 19 06:41:22 PM PDT 24 |
Jul 19 06:45:41 PM PDT 24 |
2849533960 ps |
| T514 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2366285314 |
|
|
Jul 19 07:08:41 PM PDT 24 |
Jul 19 07:15:36 PM PDT 24 |
4067289520 ps |
| T210 |
/workspace/coverage/default/2.chip_sw_hmac_smoketest.1332563519 |
|
|
Jul 19 07:01:03 PM PDT 24 |
Jul 19 07:07:42 PM PDT 24 |
2758561634 ps |
| T424 |
/workspace/coverage/default/1.chip_sw_flash_crash_alert.2504993049 |
|
|
Jul 19 06:54:09 PM PDT 24 |
Jul 19 07:07:34 PM PDT 24 |
5836944040 ps |
| T560 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.2332918741 |
|
|
Jul 19 06:47:37 PM PDT 24 |
Jul 19 06:55:28 PM PDT 24 |
4751183750 ps |
| T394 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3459509881 |
|
|
Jul 19 06:39:23 PM PDT 24 |
Jul 19 06:46:19 PM PDT 24 |
3034902336 ps |
| T561 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3051141773 |
|
|
Jul 19 06:42:19 PM PDT 24 |
Jul 19 07:03:04 PM PDT 24 |
6788449504 ps |
| T45 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3892948486 |
|
|
Jul 19 06:53:50 PM PDT 24 |
Jul 19 07:00:51 PM PDT 24 |
2502549754 ps |
| T109 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1417591871 |
|
|
Jul 19 07:08:04 PM PDT 24 |
Jul 19 07:13:51 PM PDT 24 |
3170161800 ps |
| T562 |
/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.2541650606 |
|
|
Jul 19 06:53:11 PM PDT 24 |
Jul 19 06:57:35 PM PDT 24 |
2812776472 ps |
| T372 |
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.475222130 |
|
|
Jul 19 07:06:32 PM PDT 24 |
Jul 19 07:14:57 PM PDT 24 |
4070419088 ps |
| T563 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.4088196588 |
|
|
Jul 19 06:55:15 PM PDT 24 |
Jul 19 07:00:34 PM PDT 24 |
2805200510 ps |
| T404 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.3182960238 |
|
|
Jul 19 07:07:40 PM PDT 24 |
Jul 19 07:17:50 PM PDT 24 |
4665517784 ps |
| T273 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.2693698622 |
|
|
Jul 19 07:05:47 PM PDT 24 |
Jul 19 07:17:14 PM PDT 24 |
5829126396 ps |
| T89 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.184364283 |
|
|
Jul 19 06:46:09 PM PDT 24 |
Jul 19 06:52:12 PM PDT 24 |
4996160242 ps |
| T100 |
/workspace/coverage/default/2.chip_tap_straps_rma.337291762 |
|
|
Jul 19 06:57:42 PM PDT 24 |
Jul 19 07:06:49 PM PDT 24 |
5947124207 ps |
| T294 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3826113661 |
|
|
Jul 19 07:00:27 PM PDT 24 |
Jul 19 07:11:11 PM PDT 24 |
3473378232 ps |
| T174 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4083336123 |
|
|
Jul 19 06:41:36 PM PDT 24 |
Jul 19 06:43:27 PM PDT 24 |
1905525389 ps |
| T235 |
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1780948827 |
|
|
Jul 19 07:07:02 PM PDT 24 |
Jul 19 07:16:18 PM PDT 24 |
3916290960 ps |
| T32 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.1914338045 |
|
|
Jul 19 06:40:54 PM PDT 24 |
Jul 19 08:47:46 PM PDT 24 |
31832109828 ps |
| T295 |
/workspace/coverage/default/9.chip_sw_all_escalation_resets.915234991 |
|
|
Jul 19 07:04:24 PM PDT 24 |
Jul 19 07:15:51 PM PDT 24 |
6164078136 ps |
| T296 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.2633372503 |
|
|
Jul 19 06:41:10 PM PDT 24 |
Jul 19 07:00:59 PM PDT 24 |
5305157072 ps |
| T297 |
/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.3830127858 |
|
|
Jul 19 07:05:54 PM PDT 24 |
Jul 19 07:12:41 PM PDT 24 |
6714662106 ps |
| T30 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3357195262 |
|
|
Jul 19 07:04:50 PM PDT 24 |
Jul 19 07:14:06 PM PDT 24 |
4447942450 ps |
| T31 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.239509215 |
|
|
Jul 19 06:41:20 PM PDT 24 |
Jul 19 06:52:33 PM PDT 24 |
5149218520 ps |
| T78 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1735007279 |
|
|
Jul 19 06:42:02 PM PDT 24 |
Jul 19 06:54:06 PM PDT 24 |
18593207836 ps |
| T81 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.928334479 |
|
|
Jul 19 06:44:40 PM PDT 24 |
Jul 19 06:56:43 PM PDT 24 |
3058648840 ps |
| T361 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.888204540 |
|
|
Jul 19 06:41:19 PM PDT 24 |
Jul 19 06:54:58 PM PDT 24 |
4220307960 ps |
| T28 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.104464428 |
|
|
Jul 19 06:56:01 PM PDT 24 |
Jul 19 07:05:24 PM PDT 24 |
4015366437 ps |
| T236 |
/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.3389199857 |
|
|
Jul 19 06:43:20 PM PDT 24 |
Jul 19 06:51:59 PM PDT 24 |
3968409752 ps |
| T7 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.183390105 |
|
|
Jul 19 06:43:44 PM PDT 24 |
Jul 19 06:50:55 PM PDT 24 |
5170965092 ps |
| T264 |
/workspace/coverage/default/2.chip_sw_pattgen_ios.2104251452 |
|
|
Jul 19 06:53:20 PM PDT 24 |
Jul 19 06:57:18 PM PDT 24 |
3219237540 ps |
| T112 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.1315344897 |
|
|
Jul 19 06:42:07 PM PDT 24 |
Jul 19 10:40:39 PM PDT 24 |
78805872172 ps |
| T110 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.40870161 |
|
|
Jul 19 06:40:32 PM PDT 24 |
Jul 19 07:08:44 PM PDT 24 |
6459580012 ps |
| T444 |
/workspace/coverage/default/2.chip_sw_example_concurrency.1996030733 |
|
|
Jul 19 06:52:19 PM PDT 24 |
Jul 19 06:56:10 PM PDT 24 |
2434671544 ps |
| T66 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.3549104858 |
|
|
Jul 19 06:50:23 PM PDT 24 |
Jul 19 06:54:53 PM PDT 24 |
3569405264 ps |
| T445 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1019829308 |
|
|
Jul 19 07:01:40 PM PDT 24 |
Jul 19 07:17:10 PM PDT 24 |
8401999725 ps |
| T33 |
/workspace/coverage/default/0.chip_sw_usbdev_setuprx.1139497594 |
|
|
Jul 19 06:40:10 PM PDT 24 |
Jul 19 06:50:07 PM PDT 24 |
3261286584 ps |
| T446 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.3866944663 |
|
|
Jul 19 06:40:32 PM PDT 24 |
Jul 19 06:45:48 PM PDT 24 |
3075842331 ps |
| T277 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.1828002156 |
|
|
Jul 19 07:11:27 PM PDT 24 |
Jul 19 07:21:59 PM PDT 24 |
6128194384 ps |
| T316 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.4266453171 |
|
|
Jul 19 06:41:23 PM PDT 24 |
Jul 19 07:01:27 PM PDT 24 |
6575219865 ps |
| T317 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.2990104482 |
|
|
Jul 19 06:43:25 PM PDT 24 |
Jul 19 07:01:12 PM PDT 24 |
5445040022 ps |
| T298 |
/workspace/coverage/default/2.rom_volatile_raw_unlock.1806298903 |
|
|
Jul 19 07:00:11 PM PDT 24 |
Jul 19 07:01:54 PM PDT 24 |
2650512268 ps |
| T318 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.3550915716 |
|
|
Jul 19 07:09:52 PM PDT 24 |
Jul 19 07:20:14 PM PDT 24 |
5425135360 ps |
| T319 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1495085433 |
|
|
Jul 19 06:42:22 PM PDT 24 |
Jul 19 06:53:10 PM PDT 24 |
5034679150 ps |
| T261 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3689940213 |
|
|
Jul 19 07:12:47 PM PDT 24 |
Jul 19 07:18:39 PM PDT 24 |
3894686244 ps |
| T320 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.857251475 |
|
|
Jul 19 06:38:36 PM PDT 24 |
Jul 19 06:42:26 PM PDT 24 |
2768074950 ps |
| T279 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3533203238 |
|
|
Jul 19 06:45:37 PM PDT 24 |
Jul 19 08:34:04 PM PDT 24 |
24170750528 ps |
| T321 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.500040470 |
|
|
Jul 19 07:01:59 PM PDT 24 |
Jul 19 07:07:13 PM PDT 24 |
3256947752 ps |
| T168 |
/workspace/coverage/default/91.chip_sw_all_escalation_resets.4252728227 |
|
|
Jul 19 07:11:49 PM PDT 24 |
Jul 19 07:21:45 PM PDT 24 |
4736624360 ps |
| T419 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2862851561 |
|
|
Jul 19 06:47:05 PM PDT 24 |
Jul 19 08:01:17 PM PDT 24 |
15462262828 ps |
| T534 |
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2455527806 |
|
|
Jul 19 07:09:28 PM PDT 24 |
Jul 19 07:15:17 PM PDT 24 |
4061023896 ps |
| T564 |
/workspace/coverage/default/3.chip_tap_straps_dev.186648795 |
|
|
Jul 19 07:02:24 PM PDT 24 |
Jul 19 07:04:41 PM PDT 24 |
2373753890 ps |
| T517 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.4055058194 |
|
|
Jul 19 07:10:10 PM PDT 24 |
Jul 19 07:16:50 PM PDT 24 |
3919483150 ps |
| T565 |
/workspace/coverage/default/0.rom_e2e_static_critical.2548651221 |
|
|
Jul 19 06:44:47 PM PDT 24 |
Jul 19 07:56:52 PM PDT 24 |
17180399128 ps |
| T35 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.1077635358 |
|
|
Jul 19 06:41:22 PM PDT 24 |
Jul 19 06:46:32 PM PDT 24 |
2897224736 ps |
| T331 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2234777843 |
|
|
Jul 19 06:40:36 PM PDT 24 |
Jul 19 07:05:50 PM PDT 24 |
6438948648 ps |
| T386 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3137329920 |
|
|
Jul 19 07:01:24 PM PDT 24 |
Jul 19 07:12:57 PM PDT 24 |
4401817464 ps |
| T566 |
/workspace/coverage/default/2.rom_e2e_asm_init_rma.4266784986 |
|
|
Jul 19 07:06:59 PM PDT 24 |
Jul 19 08:07:33 PM PDT 24 |
14688885723 ps |
| T567 |
/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.2888513200 |
|
|
Jul 19 06:45:11 PM PDT 24 |
Jul 19 06:52:41 PM PDT 24 |
5526640996 ps |
| T88 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.2847200197 |
|
|
Jul 19 06:47:03 PM PDT 24 |
Jul 19 07:07:55 PM PDT 24 |
7190389699 ps |
| T568 |
/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3951796693 |
|
|
Jul 19 06:40:54 PM PDT 24 |
Jul 19 06:47:53 PM PDT 24 |
7405627418 ps |
| T183 |
/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1478816040 |
|
|
Jul 19 06:41:20 PM PDT 24 |
Jul 19 08:15:52 PM PDT 24 |
43690200556 ps |
| T442 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.1781233470 |
|
|
Jul 19 06:44:24 PM PDT 24 |
Jul 19 07:53:03 PM PDT 24 |
16611584876 ps |
| T569 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.757794204 |
|
|
Jul 19 06:56:42 PM PDT 24 |
Jul 19 08:04:35 PM PDT 24 |
14693919036 ps |
| T570 |
/workspace/coverage/default/1.chip_sw_csrng_smoketest.2553368872 |
|
|
Jul 19 06:51:33 PM PDT 24 |
Jul 19 06:54:34 PM PDT 24 |
2497936362 ps |
| T63 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_rma.1669411224 |
|
|
Jul 19 06:42:05 PM PDT 24 |
Jul 19 07:19:32 PM PDT 24 |
12697627390 ps |
| T121 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3589682656 |
|
|
Jul 19 06:41:05 PM PDT 24 |
Jul 19 06:50:07 PM PDT 24 |
3535365036 ps |
| T1 |
/workspace/coverage/default/1.chip_jtag_csr_rw.1448946453 |
|
|
Jul 19 06:40:55 PM PDT 24 |
Jul 19 07:06:23 PM PDT 24 |
12925959835 ps |
| T211 |
/workspace/coverage/default/0.chip_sw_hmac_enc.2932788997 |
|
|
Jul 19 06:43:03 PM PDT 24 |
Jul 19 06:48:36 PM PDT 24 |
2794103744 ps |
| T244 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.3706367907 |
|
|
Jul 19 06:49:17 PM PDT 24 |
Jul 19 06:53:04 PM PDT 24 |
2330444711 ps |
| T399 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.1110917954 |
|
|
Jul 19 06:55:24 PM PDT 24 |
Jul 19 07:06:31 PM PDT 24 |
7924046579 ps |
| T400 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2701945258 |
|
|
Jul 19 06:50:42 PM PDT 24 |
Jul 19 08:16:48 PM PDT 24 |
25091460038 ps |
| T401 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3779651895 |
|
|
Jul 19 07:05:06 PM PDT 24 |
Jul 19 07:11:23 PM PDT 24 |
3820684588 ps |
| T2 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.640475782 |
|
|
Jul 19 06:48:36 PM PDT 24 |
Jul 19 06:56:02 PM PDT 24 |
7848289088 ps |
| T146 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.348761848 |
|
|
Jul 19 07:09:58 PM PDT 24 |
Jul 19 07:19:10 PM PDT 24 |
5103801992 ps |
| T147 |
/workspace/coverage/default/1.chip_sw_aes_masking_off.1644548071 |
|
|
Jul 19 06:43:22 PM PDT 24 |
Jul 19 06:47:50 PM PDT 24 |
3178320646 ps |
| T148 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.479937528 |
|
|
Jul 19 07:03:57 PM PDT 24 |
Jul 19 07:11:42 PM PDT 24 |
3799434342 ps |
| T149 |
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1610220049 |
|
|
Jul 19 07:02:57 PM PDT 24 |
Jul 19 07:12:55 PM PDT 24 |
3979557488 ps |
| T150 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.935685258 |
|
|
Jul 19 06:59:17 PM PDT 24 |
Jul 19 07:07:42 PM PDT 24 |
4186329336 ps |
| T90 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1942604870 |
|
|
Jul 19 06:40:46 PM PDT 24 |
Jul 19 06:56:41 PM PDT 24 |
8882232072 ps |
| T151 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.4266025441 |
|
|
Jul 19 06:58:32 PM PDT 24 |
Jul 19 07:33:46 PM PDT 24 |
8842597324 ps |
| T152 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.143924307 |
|
|
Jul 19 06:40:27 PM PDT 24 |
Jul 19 06:49:19 PM PDT 24 |
4522532881 ps |
| T153 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1028705891 |
|
|
Jul 19 06:39:37 PM PDT 24 |
Jul 19 06:43:00 PM PDT 24 |
3040644685 ps |
| T571 |
/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.3995093034 |
|
|
Jul 19 06:53:13 PM PDT 24 |
Jul 19 06:58:42 PM PDT 24 |
2751746820 ps |
| T242 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.2257155005 |
|
|
Jul 19 07:10:46 PM PDT 24 |
Jul 19 07:20:15 PM PDT 24 |
5521060020 ps |
| T572 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1619327067 |
|
|
Jul 19 06:54:59 PM PDT 24 |
Jul 19 07:13:14 PM PDT 24 |
8125605312 ps |
| T165 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.389505439 |
|
|
Jul 19 06:43:08 PM PDT 24 |
Jul 19 09:49:05 PM PDT 24 |
58052561356 ps |
| T194 |
/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.339189858 |
|
|
Jul 19 06:45:24 PM PDT 24 |
Jul 19 06:54:11 PM PDT 24 |
4772157072 ps |
| T573 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.35269295 |
|
|
Jul 19 06:43:05 PM PDT 24 |
Jul 19 06:48:28 PM PDT 24 |
5526992492 ps |
| T518 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.4044272371 |
|
|
Jul 19 07:04:04 PM PDT 24 |
Jul 19 07:15:02 PM PDT 24 |
6015586902 ps |
| T574 |
/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.3139474544 |
|
|
Jul 19 06:45:13 PM PDT 24 |
Jul 19 06:50:05 PM PDT 24 |
3271456556 ps |
| T575 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2011308024 |
|
|
Jul 19 06:52:50 PM PDT 24 |
Jul 19 06:56:55 PM PDT 24 |
2196814415 ps |
| T408 |
/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2684920884 |
|
|
Jul 19 06:40:31 PM PDT 24 |
Jul 19 06:51:40 PM PDT 24 |
6104982680 ps |
| T576 |
/workspace/coverage/default/1.chip_sw_hmac_oneshot.4176890479 |
|
|
Jul 19 06:44:36 PM PDT 24 |
Jul 19 06:49:14 PM PDT 24 |
2986347688 ps |
| T3 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1729631170 |
|
|
Jul 19 07:00:59 PM PDT 24 |
Jul 19 07:29:02 PM PDT 24 |
24346883780 ps |
| T274 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.3167484492 |
|
|
Jul 19 07:11:28 PM PDT 24 |
Jul 19 07:19:29 PM PDT 24 |
4960404920 ps |
| T175 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.142836284 |
|
|
Jul 19 07:11:14 PM PDT 24 |
Jul 19 07:21:54 PM PDT 24 |
6356610898 ps |
| T101 |
/workspace/coverage/default/1.chip_tap_straps_testunlock0.2219092341 |
|
|
Jul 19 06:50:41 PM PDT 24 |
Jul 19 06:59:52 PM PDT 24 |
5486882533 ps |