Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	513538252	59133375	0	0
DepthKnown_A	513538252	513431109	0	0
RvalidKnown_A	513538252	513431109	0	0
WreadyKnown_A	513538252	513431109	0	0
gen_passthru_fifo.paramCheckPass	1018	1018	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	59133375	0	0
T4	99713	20884	0	0
T5	608213	82898	0	0
T6	107153	11388	0	0
T18	222940	22982	0	0
T19	142870	19263	0	0
T20	239390	31370	0	0
T59	201916	26362	0	0
T130	84985	9972	0	0
T131	102259	11951	0	0
T132	618483	56286	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	513431109	0	0
T4	99713	99655	0	0
T5	608213	608155	0	0
T6	107153	107098	0	0
T18	222940	222878	0	0
T19	142870	142815	0	0
T20	239390	239277	0	0
T59	201916	201854	0	0
T130	84985	84923	0	0
T131	102259	102208	0	0
T132	618483	618428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	513431109	0	0
T4	99713	99655	0	0
T5	608213	608155	0	0
T6	107153	107098	0	0
T18	222940	222878	0	0
T19	142870	142815	0	0
T20	239390	239277	0	0
T59	201916	201854	0	0
T130	84985	84923	0	0
T131	102259	102208	0	0
T132	618483	618428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	513431109	0	0
T4	99713	99655	0	0
T5	608213	608155	0	0
T6	107153	107098	0	0
T18	222940	222878	0	0
T19	142870	142815	0	0
T20	239390	239277	0	0
T59	201916	201854	0	0
T130	84985	84923	0	0
T131	102259	102208	0	0
T132	618483	618428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1018	1018	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T59	1	1	0	0
T130	1	1	0	0
T131	1	1	0	0
T132	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	513538252	45224366	0	0
DepthKnown_A	513538252	513431109	0	0
RvalidKnown_A	513538252	513431109	0	0
WreadyKnown_A	513538252	513431109	0	0
gen_passthru_fifo.paramCheckPass	1018	1018	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	45224366	0	0
T4	99713	13288	0	0
T5	608213	77238	0	0
T6	107153	9486	0	0
T18	222940	18918	0	0
T19	142870	14129	0	0
T20	239390	21788	0	0
T59	201916	23654	0	0
T130	84985	7587	0	0
T131	102259	9618	0	0
T132	618483	52296	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	513431109	0	0
T4	99713	99655	0	0
T5	608213	608155	0	0
T6	107153	107098	0	0
T18	222940	222878	0	0
T19	142870	142815	0	0
T20	239390	239277	0	0
T59	201916	201854	0	0
T130	84985	84923	0	0
T131	102259	102208	0	0
T132	618483	618428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	513431109	0	0
T4	99713	99655	0	0
T5	608213	608155	0	0
T6	107153	107098	0	0
T18	222940	222878	0	0
T19	142870	142815	0	0
T20	239390	239277	0	0
T59	201916	201854	0	0
T130	84985	84923	0	0
T131	102259	102208	0	0
T132	618483	618428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	513431109	0	0
T4	99713	99655	0	0
T5	608213	608155	0	0
T6	107153	107098	0	0
T18	222940	222878	0	0
T19	142870	142815	0	0
T20	239390	239277	0	0
T59	201916	201854	0	0
T130	84985	84923	0	0
T131	102259	102208	0	0
T132	618483	618428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1018	1018	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T59	1	1	0	0
T130	1	1	0	0
T131	1	1	0	0
T132	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	513538252	42656372	0	0
DepthKnown_A	513538252	513431109	0	0
RvalidKnown_A	513538252	513431109	0	0
WreadyKnown_A	513538252	513431109	0	0
gen_passthru_fifo.paramCheckPass	1018	1018	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	42656372	0	0
T4	99713	5792	0	0
T5	608213	99025	0	0
T6	107153	8035	0	0
T18	222940	20939	0	0
T19	142870	8169	0	0
T20	239390	15458	0	0
T59	201916	6058	0	0
T130	84985	5473	0	0
T131	102259	6781	0	0
T132	618483	66296	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	513431109	0	0
T4	99713	99655	0	0
T5	608213	608155	0	0
T6	107153	107098	0	0
T18	222940	222878	0	0
T19	142870	142815	0	0
T20	239390	239277	0	0
T59	201916	201854	0	0
T130	84985	84923	0	0
T131	102259	102208	0	0
T132	618483	618428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	513431109	0	0
T4	99713	99655	0	0
T5	608213	608155	0	0
T6	107153	107098	0	0
T18	222940	222878	0	0
T19	142870	142815	0	0
T20	239390	239277	0	0
T59	201916	201854	0	0
T130	84985	84923	0	0
T131	102259	102208	0	0
T132	618483	618428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	513431109	0	0
T4	99713	99655	0	0
T5	608213	608155	0	0
T6	107153	107098	0	0
T18	222940	222878	0	0
T19	142870	142815	0	0
T20	239390	239277	0	0
T59	201916	201854	0	0
T130	84985	84923	0	0
T131	102259	102208	0	0
T132	618483	618428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1018	1018	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T59	1	1	0	0
T130	1	1	0	0
T131	1	1	0	0
T132	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	513538252	36019341	0	0
DepthKnown_A	513538252	513431109	0	0
RvalidKnown_A	513538252	513431109	0	0
WreadyKnown_A	513538252	513431109	0	0
gen_passthru_fifo.paramCheckPass	1018	1018	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	36019341	0	0
T4	99713	5661	0	0
T5	608213	98865	0	0
T6	107153	7913	0	0
T18	222940	20725	0	0
T19	142870	7891	0	0
T20	239390	15075	0	0
T59	201916	5854	0	0
T130	84985	5339	0	0
T131	102259	6649	0	0
T132	618483	66090	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	513431109	0	0
T4	99713	99655	0	0
T5	608213	608155	0	0
T6	107153	107098	0	0
T18	222940	222878	0	0
T19	142870	142815	0	0
T20	239390	239277	0	0
T59	201916	201854	0	0
T130	84985	84923	0	0
T131	102259	102208	0	0
T132	618483	618428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	513431109	0	0
T4	99713	99655	0	0
T5	608213	608155	0	0
T6	107153	107098	0	0
T18	222940	222878	0	0
T19	142870	142815	0	0
T20	239390	239277	0	0
T59	201916	201854	0	0
T130	84985	84923	0	0
T131	102259	102208	0	0
T132	618483	618428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	513431109	0	0
T4	99713	99655	0	0
T5	608213	608155	0	0
T6	107153	107098	0	0
T18	222940	222878	0	0
T19	142870	142815	0	0
T20	239390	239277	0	0
T59	201916	201854	0	0
T130	84985	84923	0	0
T131	102259	102208	0	0
T132	618483	618428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1018	1018	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T59	1	1	0	0
T130	1	1	0	0
T131	1	1	0	0
T132	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	513538252	64962	0	0
DepthKnown_A	513538252	513431109	0	0
RvalidKnown_A	513538252	513431109	0	0
WreadyKnown_A	513538252	513431109	0	0
gen_passthru_fifo.paramCheckPass	1018	1018	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	64962	0	0
T4	99713	13	0	0
T5	608213	13	0	0
T6	107153	13	0	0
T18	222940	56	0	0
T19	142870	26	0	0
T20	239390	151	0	0
T59	201916	78	0	0
T130	84985	13	0	0
T131	102259	13	0	0
T132	618483	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	513431109	0	0
T4	99713	99655	0	0
T5	608213	608155	0	0
T6	107153	107098	0	0
T18	222940	222878	0	0
T19	142870	142815	0	0
T20	239390	239277	0	0
T59	201916	201854	0	0
T130	84985	84923	0	0
T131	102259	102208	0	0
T132	618483	618428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	513431109	0	0
T4	99713	99655	0	0
T5	608213	608155	0	0
T6	107153	107098	0	0
T18	222940	222878	0	0
T19	142870	142815	0	0
T20	239390	239277	0	0
T59	201916	201854	0	0
T130	84985	84923	0	0
T131	102259	102208	0	0
T132	618483	618428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	513431109	0	0
T4	99713	99655	0	0
T5	608213	608155	0	0
T6	107153	107098	0	0
T18	222940	222878	0	0
T19	142870	142815	0	0
T20	239390	239277	0	0
T59	201916	201854	0	0
T130	84985	84923	0	0
T131	102259	102208	0	0
T132	618483	618428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1018	1018	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T59	1	1	0	0
T130	1	1	0	0
T131	1	1	0	0
T132	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	513538252	64962	0	0
DepthKnown_A	513538252	513431109	0	0
RvalidKnown_A	513538252	513431109	0	0
WreadyKnown_A	513538252	513431109	0	0
gen_passthru_fifo.paramCheckPass	1018	1018	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	64962	0	0
T4	99713	13	0	0
T5	608213	13	0	0
T6	107153	13	0	0
T18	222940	56	0	0
T19	142870	26	0	0
T20	239390	151	0	0
T59	201916	78	0	0
T130	84985	13	0	0
T131	102259	13	0	0
T132	618483	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	513431109	0	0
T4	99713	99655	0	0
T5	608213	608155	0	0
T6	107153	107098	0	0
T18	222940	222878	0	0
T19	142870	142815	0	0
T20	239390	239277	0	0
T59	201916	201854	0	0
T130	84985	84923	0	0
T131	102259	102208	0	0
T132	618483	618428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	513431109	0	0
T4	99713	99655	0	0
T5	608213	608155	0	0
T6	107153	107098	0	0
T18	222940	222878	0	0
T19	142870	142815	0	0
T20	239390	239277	0	0
T59	201916	201854	0	0
T130	84985	84923	0	0
T131	102259	102208	0	0
T132	618483	618428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	513431109	0	0
T4	99713	99655	0	0
T5	608213	608155	0	0
T6	107153	107098	0	0
T18	222940	222878	0	0
T19	142870	142815	0	0
T20	239390	239277	0	0
T59	201916	201854	0	0
T130	84985	84923	0	0
T131	102259	102208	0	0
T132	618483	618428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1018	1018	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T59	1	1	0	0
T130	1	1	0	0
T131	1	1	0	0
T132	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	513538252	51669	0	0
DepthKnown_A	513538252	513431109	0	0
RvalidKnown_A	513538252	513431109	0	0
WreadyKnown_A	513538252	513431109	0	0
gen_passthru_fifo.paramCheckPass	1018	1018	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	51669	0	0
T4	99713	12	0	0
T5	608213	12	0	0
T6	107153	12	0	0
T18	222940	55	0	0
T19	142870	23	0	0
T20	239390	95	0	0
T59	201916	77	0	0
T130	84985	12	0	0
T131	102259	12	0	0
T132	618483	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	513431109	0	0
T4	99713	99655	0	0
T5	608213	608155	0	0
T6	107153	107098	0	0
T18	222940	222878	0	0
T19	142870	142815	0	0
T20	239390	239277	0	0
T59	201916	201854	0	0
T130	84985	84923	0	0
T131	102259	102208	0	0
T132	618483	618428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	513431109	0	0
T4	99713	99655	0	0
T5	608213	608155	0	0
T6	107153	107098	0	0
T18	222940	222878	0	0
T19	142870	142815	0	0
T20	239390	239277	0	0
T59	201916	201854	0	0
T130	84985	84923	0	0
T131	102259	102208	0	0
T132	618483	618428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	513431109	0	0
T4	99713	99655	0	0
T5	608213	608155	0	0
T6	107153	107098	0	0
T18	222940	222878	0	0
T19	142870	142815	0	0
T20	239390	239277	0	0
T59	201916	201854	0	0
T130	84985	84923	0	0
T131	102259	102208	0	0
T132	618483	618428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1018	1018	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T59	1	1	0	0
T130	1	1	0	0
T131	1	1	0	0
T132	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	513538252	51669	0	0
DepthKnown_A	513538252	513431109	0	0
RvalidKnown_A	513538252	513431109	0	0
WreadyKnown_A	513538252	513431109	0	0
gen_passthru_fifo.paramCheckPass	1018	1018	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	51669	0	0
T4	99713	12	0	0
T5	608213	12	0	0
T6	107153	12	0	0
T18	222940	55	0	0
T19	142870	23	0	0
T20	239390	95	0	0
T59	201916	77	0	0
T130	84985	12	0	0
T131	102259	12	0	0
T132	618483	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	513431109	0	0
T4	99713	99655	0	0
T5	608213	608155	0	0
T6	107153	107098	0	0
T18	222940	222878	0	0
T19	142870	142815	0	0
T20	239390	239277	0	0
T59	201916	201854	0	0
T130	84985	84923	0	0
T131	102259	102208	0	0
T132	618483	618428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	513431109	0	0
T4	99713	99655	0	0
T5	608213	608155	0	0
T6	107153	107098	0	0
T18	222940	222878	0	0
T19	142870	142815	0	0
T20	239390	239277	0	0
T59	201916	201854	0	0
T130	84985	84923	0	0
T131	102259	102208	0	0
T132	618483	618428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	513431109	0	0
T4	99713	99655	0	0
T5	608213	608155	0	0
T6	107153	107098	0	0
T18	222940	222878	0	0
T19	142870	142815	0	0
T20	239390	239277	0	0
T59	201916	201854	0	0
T130	84985	84923	0	0
T131	102259	102208	0	0
T132	618483	618428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1018	1018	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T59	1	1	0	0
T130	1	1	0	0
T131	1	1	0	0
T132	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	513538252	13293	0	0
DepthKnown_A	513538252	513431109	0	0
RvalidKnown_A	513538252	513431109	0	0
WreadyKnown_A	513538252	513431109	0	0
gen_passthru_fifo.paramCheckPass	1018	1018	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	13293	0	0
T4	99713	1	0	0
T5	608213	1	0	0
T6	107153	1	0	0
T18	222940	1	0	0
T19	142870	3	0	0
T20	239390	56	0	0
T59	201916	1	0	0
T130	84985	1	0	0
T131	102259	1	0	0
T132	618483	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	513431109	0	0
T4	99713	99655	0	0
T5	608213	608155	0	0
T6	107153	107098	0	0
T18	222940	222878	0	0
T19	142870	142815	0	0
T20	239390	239277	0	0
T59	201916	201854	0	0
T130	84985	84923	0	0
T131	102259	102208	0	0
T132	618483	618428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	513431109	0	0
T4	99713	99655	0	0
T5	608213	608155	0	0
T6	107153	107098	0	0
T18	222940	222878	0	0
T19	142870	142815	0	0
T20	239390	239277	0	0
T59	201916	201854	0	0
T130	84985	84923	0	0
T131	102259	102208	0	0
T132	618483	618428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	513431109	0	0
T4	99713	99655	0	0
T5	608213	608155	0	0
T6	107153	107098	0	0
T18	222940	222878	0	0
T19	142870	142815	0	0
T20	239390	239277	0	0
T59	201916	201854	0	0
T130	84985	84923	0	0
T131	102259	102208	0	0
T132	618483	618428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1018	1018	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T59	1	1	0	0
T130	1	1	0	0
T131	1	1	0	0
T132	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	513538252	13293	0	0
DepthKnown_A	513538252	513431109	0	0
RvalidKnown_A	513538252	513431109	0	0
WreadyKnown_A	513538252	513431109	0	0
gen_passthru_fifo.paramCheckPass	1018	1018	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	13293	0	0
T4	99713	1	0	0
T5	608213	1	0	0
T6	107153	1	0	0
T18	222940	1	0	0
T19	142870	3	0	0
T20	239390	56	0	0
T59	201916	1	0	0
T130	84985	1	0	0
T131	102259	1	0	0
T132	618483	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	513431109	0	0
T4	99713	99655	0	0
T5	608213	608155	0	0
T6	107153	107098	0	0
T18	222940	222878	0	0
T19	142870	142815	0	0
T20	239390	239277	0	0
T59	201916	201854	0	0
T130	84985	84923	0	0
T131	102259	102208	0	0
T132	618483	618428	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	513431109	0	0
T4	99713	99655	0	0
T5	608213	608155	0	0
T6	107153	107098	0	0
T18	222940	222878	0	0
T19	142870	142815	0	0
T20	239390	239277	0	0
T59	201916	201854	0	0
T130	84985	84923	0	0
T131	102259	102208	0	0
T132	618483	618428	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513538252	513431109	0	0
T4	99713	99655	0	0
T5	608213	608155	0	0
T6	107153	107098	0	0
T18	222940	222878	0	0
T19	142870	142815	0	0
T20	239390	239277	0	0
T59	201916	201854	0	0
T130	84985	84923	0	0
T131	102259	102208	0	0
T132	618483	618428	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1018	1018	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T59	1	1	0	0
T130	1	1	0	0
T131	1	1	0	0
T132	1	1	0	0