Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3758842	1			T76	1205		T77	465		T78	114
values[2]	755450	1			T76	441		T77	129		T78	60
values[3]	107074	1			T76	38		T78	1		T126	139
values[4]	56106	1			T126	68		T443	145		T472	276
values[5]	36834	1			T126	42		T443	92		T472	139
values[6]	27480	1			T126	10		T443	100		T472	81
values[7]	22668	1			T126	5		T443	86		T472	73
values[8]	19243	1			T126	2		T443	70		T472	53
values[9]	17260	1			T126	2		T443	45		T472	66
values[10]	15838	1			T126	2		T443	36		T472	31
values[11]	14482	1			T126	1		T443	20		T472	46
values[12]	13799	1			T126	1		T443	24		T472	70
values[13]	12885	1			T126	4		T443	10		T472	56
values[14]	12076	1			T126	3		T443	21		T472	36
values[15]	11730	1			T126	1		T443	13		T472	14
values[16]	11608	1			T126	1		T443	11		T472	14
values[17]	11122	1			T126	1		T443	7		T472	14
values[18]	10777	1			T126	1		T443	23		T472	6
values[19]	10514	1			T126	3		T443	17		T472	5
values[20]	10063	1			T126	3		T443	16		T472	3
values[21]	9592	1			T126	1		T443	8		T472	8
values[22]	9452	1			T126	1		T443	6		T472	4
values[23]	9196	1			T126	3		T443	15		T472	10
values[24]	8626	1			T126	1		T443	13		T472	11
values[25]	8423	1			T126	1		T443	9		T472	9
values[26]	8066	1			T126	1		T443	10		T472	19
values[27]	7518	1			T126	1		T443	10		T472	39
values[28]	7334	1			T126	1		T443	5		T472	22
values[29]	7081	1			T126	1		T443	4		T472	4
values[30]	6400	1			T126	3		T443	9		T472	9
values[31]	5871	1			T126	3		T443	6		T472	9
values[32]	5395	1			T126	1		T443	2		T472	7
values[33]	5144	1			T126	1		T443	5		T472	6
values[34]	4951	1			T126	1		T443	2		T472	5
values[35]	4667	1			T126	1		T443	10		T472	11
values[36]	4362	1			T126	4		T443	7		T472	18
values[37]	4014	1			T126	3		T443	8		T472	23
values[38]	3931	1			T126	1		T443	15		T472	3
values[39]	3791	1			T126	2		T443	8		T854	4
values[40]	3691	1			T126	4		T443	3		T854	3
values[41]	3508	1			T126	1		T443	3		T854	4
values[42]	3426	1			T126	3		T443	2		T854	5
values[43]	3265	1			T126	2		T854	6		T857	10
values[44]	3226	1			T126	1		T854	3		T857	10
values[45]	3214	1			T126	1		T854	6		T857	9
values[46]	3204	1			T126	3		T854	5		T857	9
values[47]	3172	1			T126	1		T854	6		T857	9
values[48]	3123	1			T126	2		T854	5		T857	9
values[49]	3015	1			T126	4		T854	3		T857	9
values[50]	2922	1			T126	4		T854	5		T857	9
values[51]	2889	1			T126	2		T854	5		T857	9
values[52]	2870	1			T126	5		T854	5		T857	9
values[53]	2814	1			T126	1		T854	8		T857	9
values[54]	2826	1			T126	1		T854	4		T857	10
values[55]	2792	1			T126	4		T854	10		T857	10
values[56]	2675	1			T126	1		T854	3		T857	9
values[57]	2621	1			T126	1		T854	3		T857	9
values[58]	2574	1			T126	1		T854	5		T857	9
values[59]	2576	1			T126	2		T854	6		T857	9
values[60]	2571	1			T126	2		T854	3		T857	9
values[61]	2732	1			T126	4		T854	4		T857	10
values[62]	4094	1			T126	7		T854	11		T857	9
values[63]	11112	1			T126	29		T854	67		T857	9
values[64]	247294	1			T126	66		T854	332		T857	1611

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4822004	1			T76	1516		T77	418		T78	144
values[2]	814468	1			T76	404		T77	142		T78	38
values[3]	85554	1			T76	53		T77	3		T78	4
values[4]	14481	1			T76	5		T77	2		T126	12
values[5]	5243	1			T126	5		T152	3		T472	21
values[6]	2933	1			T126	2		T472	4		T857	4
values[7]	2291	1			T126	2		T472	1		T554	11
values[8]	1876	1			T126	2		T554	1		T441	1
values[9]	1792	1			T126	8		T554	2		T441	1
values[10]	1652	1			T126	5		T554	3		T441	1
values[11]	1505	1			T126	5		T554	10		T441	1
values[12]	1335	1			T126	6		T554	18		T441	1
values[13]	1238	1			T126	2		T554	10		T441	1
values[14]	1257	1			T126	2		T554	10		T441	1
values[15]	1095	1			T126	3		T554	3		T441	1
values[16]	1028	1			T126	3		T554	11		T441	1
values[17]	911	1			T126	3		T554	9		T441	1
values[18]	885	1			T126	2		T554	13		T441	1
values[19]	785	1			T126	3		T554	2		T441	1
values[20]	721	1			T126	3		T554	5		T441	1
values[21]	738	1			T126	6		T554	9		T441	1
values[22]	706	1			T126	15		T554	2		T441	1
values[23]	658	1			T126	6		T554	11		T441	1
values[24]	687	1			T126	3		T554	15		T441	1
values[25]	651	1			T126	5		T554	11		T441	1
values[26]	648	1			T126	2		T554	7		T441	1
values[27]	649	1			T126	5		T554	3		T441	1
values[28]	597	1			T126	2		T441	1		T712	2
values[29]	595	1			T126	3		T441	1		T712	2
values[30]	525	1			T126	5		T441	1		T712	2
values[31]	584	1			T126	3		T441	1		T712	2
values[32]	551	1			T126	3		T441	1		T712	2
values[33]	525	1			T126	4		T441	1		T712	2
values[34]	508	1			T126	6		T441	1		T712	2
values[35]	538	1			T126	3		T441	1		T712	2
values[36]	499	1			T126	4		T441	1		T712	2
values[37]	498	1			T126	5		T441	1		T712	2
values[38]	449	1			T126	8		T441	1		T712	2
values[39]	463	1			T126	7		T441	1		T712	2
values[40]	430	1			T126	8		T441	1		T712	2
values[41]	419	1			T126	4		T441	1		T712	2
values[42]	425	1			T126	9		T441	1		T712	1
values[43]	413	1			T126	7		T441	1		T712	1
values[44]	442	1			T126	6		T441	1		T712	2
values[45]	404	1			T126	2		T441	1		T712	2
values[46]	393	1			T126	4		T441	1		T712	2
values[47]	369	1			T126	3		T441	1		T712	2
values[48]	387	1			T126	5		T441	1		T712	2
values[49]	372	1			T126	3		T441	1		T712	2
values[50]	381	1			T126	5		T441	1		T712	2
values[51]	371	1			T126	4		T441	1		T712	2
values[52]	340	1			T126	8		T441	1		T712	2
values[53]	346	1			T126	3		T441	1		T712	2
values[54]	357	1			T126	4		T441	1		T712	3
values[55]	370	1			T126	4		T441	1		T712	2
values[56]	364	1			T126	5		T441	1		T712	2
values[57]	364	1			T126	7		T441	1		T712	2
values[58]	365	1			T126	3		T441	1		T712	2
values[59]	341	1			T126	2		T441	1		T712	1
values[60]	366	1			T126	4		T441	1		T712	1
values[61]	355	1			T126	4		T441	1		T712	3
values[62]	560	1			T126	10		T441	1		T712	2
values[63]	2148	1			T126	44		T441	1		T712	4
values[64]	28413	1			T126	149		T441	206		T712	117

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	592946	1			T76	20		T77	4		T78	1
values[2]	2647319	1			T76	832		T77	449		T78	76
values[3]	1201359	1			T76	571		T77	116		T78	68
values[4]	147542	1			T76	17		T77	1		T78	2
values[5]	75853	1			T126	116		T152	3		T443	56
values[6]	49358	1			T126	76		T443	45		T472	161
values[7]	36187	1			T126	67		T443	39		T472	122
values[8]	28651	1			T126	64		T443	20		T472	94
values[9]	24329	1			T126	92		T443	19		T472	79
values[10]	21159	1			T126	69		T443	19		T472	62
values[11]	19085	1			T126	53		T443	14		T472	58
values[12]	17324	1			T126	47		T443	7		T472	44
values[13]	16422	1			T126	21		T443	5		T472	63
values[14]	15582	1			T126	29		T443	7		T472	60
values[15]	14547	1			T126	31		T443	19		T472	31
values[16]	13800	1			T126	18		T443	9		T472	18
values[17]	13415	1			T126	24		T443	10		T472	19
values[18]	13201	1			T126	14		T443	3		T472	21
values[19]	12922	1			T126	11		T443	5		T472	12
values[20]	12423	1			T126	19		T443	4		T472	15
values[21]	11453	1			T126	20		T443	6		T472	7
values[22]	10964	1			T126	19		T443	7		T472	10
values[23]	10686	1			T126	26		T443	11		T472	16
values[24]	10202	1			T126	19		T443	12		T472	11
values[25]	9677	1			T126	15		T443	2		T472	17
values[26]	9408	1			T126	11		T443	9		T472	17
values[27]	9025	1			T126	14		T443	12		T472	11
values[28]	8411	1			T126	14		T443	5		T472	7
values[29]	7924	1			T126	11		T443	16		T472	5
values[30]	7651	1			T126	10		T443	6		T472	8
values[31]	7021	1			T126	14		T443	8		T472	2
values[32]	6542	1			T126	18		T443	12		T520	1
values[33]	6037	1			T126	17		T443	6		T520	2
values[34]	5447	1			T126	20		T443	4		T520	5
values[35]	5165	1			T126	23		T443	6		T520	7
values[36]	4858	1			T126	25		T443	5		T520	5
values[37]	4484	1			T126	15		T443	1		T520	2
values[38]	4486	1			T126	9		T520	3		T854	7
values[39]	4260	1			T126	10		T520	5		T854	6
values[40]	4152	1			T126	16		T520	11		T854	4
values[41]	3959	1			T126	12		T520	1		T854	4
values[42]	3889	1			T126	20		T520	1		T854	6
values[43]	3832	1			T126	13		T520	2		T854	8
values[44]	3716	1			T126	17		T520	1		T854	9
values[45]	3667	1			T126	14		T520	1		T854	12
values[46]	3643	1			T126	23		T520	1		T854	7
values[47]	3624	1			T126	16		T520	3		T854	8
values[48]	3706	1			T126	9		T520	3		T854	12
values[49]	3489	1			T126	7		T520	5		T854	21
values[50]	3436	1			T126	9		T520	5		T854	24
values[51]	3404	1			T126	13		T520	6		T854	20
values[52]	3365	1			T126	5		T520	1		T854	22
values[53]	3337	1			T126	9		T520	1		T854	17
values[54]	3134	1			T126	9		T520	1		T854	15
values[55]	3093	1			T126	10		T520	1		T854	7
values[56]	3015	1			T126	9		T520	4		T854	10
values[57]	2960	1			T126	9		T520	3		T854	11
values[58]	2967	1			T126	12		T520	3		T854	11
values[59]	2812	1			T126	11		T520	5		T854	8
values[60]	2800	1			T126	8		T520	3		T854	10
values[61]	2871	1			T126	4		T520	1		T854	8
values[62]	3945	1			T126	17		T520	6		T854	24
values[63]	9382	1			T126	70		T520	4		T854	25
values[64]	236806	1			T126	290		T520	21		T854	88