Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2072783	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

37948588

1

T4

211071

T5

8764

T6

348

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	27797819	1			T4	190207		T5	4300		T6	175
values[0x0]	10728143	1			T4	20864		T5	4464		T6	173
values[0x1]	1495409	1			T4	7		T5	551		T6	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	726652	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

39294719

1

T4

211078

T5

9315

T6

351

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18695520	1			T4	105539		T5	4658		T6	176
valid_sources[0x01]	18694525	1			T4	105539		T5	4657		T6	175
valid_sources[0x02]	42268	1			T145	112		T551	20		T146	817
valid_sources[0x03]	43119	1			T145	209		T551	18		T146	801
valid_sources[0x04]	42374	1			T81	1		T11	1		T145	98
valid_sources[0x05]	42192	1			T1	1		T79	1		T215	3
valid_sources[0x06]	42631	1			T1	1		T79	2		T81	1
valid_sources[0x07]	42035	1			T1	1		T79	2		T11	1
valid_sources[0x08]	41207	1			T81	1		T11	1		T145	154
valid_sources[0x09]	42172	1			T81	1		T11	1		T145	114
valid_sources[0x0a]	42933	1			T11	1		T145	120		T551	15
valid_sources[0x0b]	42227	1			T79	2		T81	2		T11	1
valid_sources[0x0c]	42537	1			T79	1		T145	170		T551	30
valid_sources[0x0d]	42662	1			T1	1		T81	1		T145	95
valid_sources[0x0e]	42229	1			T81	3		T145	94		T551	16
valid_sources[0x0f]	41993	1			T11	1		T145	141		T551	20
valid_sources[0x10]	42570	1			T11	1		T145	109		T551	13
valid_sources[0x11]	42267	1			T79	2		T81	2		T145	168
valid_sources[0x12]	42908	1			T11	1		T145	110		T551	32
valid_sources[0x13]	41617	1			T81	2		T145	78		T551	29
valid_sources[0x14]	42130	1			T1	3		T79	1		T145	101
valid_sources[0x15]	42040	1			T11	1		T145	128		T551	19
valid_sources[0x16]	42908	1			T81	1		T11	3		T145	117
valid_sources[0x17]	42510	1			T1	1		T81	1		T11	1
valid_sources[0x18]	42790	1			T79	1		T145	119		T551	18
valid_sources[0x19]	42460	1			T1	3		T81	3		T145	149
valid_sources[0x1a]	43218	1			T79	1		T81	1		T145	79
valid_sources[0x1b]	41282	1			T145	139		T551	14		T146	817
valid_sources[0x1c]	43161	1			T145	117		T551	19		T146	801
valid_sources[0x1d]	43730	1			T1	7		T81	1		T145	72
valid_sources[0x1e]	41548	1			T79	2		T11	1		T145	152
valid_sources[0x1f]	43001	1			T214	39		T11	2		T145	94
valid_sources[0x20]	42603	1			T79	1		T81	1		T145	125

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26986252

1

T4

190207

T5

4300

T6

175

values[0x0]

all_enables

biggest_size

10676050

1

T4

20864

T5

4464

T6

173

values[0x1]

all_enables

biggest_size

286286

1

T1

21

T79

22

T81

22

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2869532	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

453145

1

T76

240

T77

67

T78

25

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1127223	1			T76	529		T77	204		T78	56
values[0x0]	1071601	1			T76	589		T77	180		T78	50
values[0x1]	1123853	1			T76	566		T77	210		T78	69

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2222412	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1100265

1

T76

559

T77

187

T78

60

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51127	1			T76	20		T77	9		T78	4
valid_sources[0x01]	51585	1			T76	22		T77	10		T78	1
valid_sources[0x02]	52242	1			T76	35		T77	12		T78	4
valid_sources[0x03]	52044	1			T76	28		T77	12		T126	10
valid_sources[0x04]	51782	1			T76	26		T77	8		T78	2
valid_sources[0x05]	52159	1			T76	20		T77	9		T126	1
valid_sources[0x06]	52571	1			T76	33		T77	5		T126	4
valid_sources[0x07]	52219	1			T76	23		T77	10		T78	2
valid_sources[0x08]	51950	1			T76	34		T77	12		T126	2
valid_sources[0x09]	52296	1			T76	32		T77	10		T78	5
valid_sources[0x0a]	53590	1			T76	20		T77	11		T78	4
valid_sources[0x0b]	51162	1			T76	31		T77	9		T78	3
valid_sources[0x0c]	51770	1			T76	26		T77	8		T126	2
valid_sources[0x0d]	53193	1			T76	26		T77	8		T126	2
valid_sources[0x0e]	52311	1			T76	29		T77	11		T78	3
valid_sources[0x0f]	51571	1			T76	20		T77	9		T78	4
valid_sources[0x10]	52502	1			T76	27		T77	17		T78	3
valid_sources[0x11]	52119	1			T76	33		T77	16		T78	3
valid_sources[0x12]	51683	1			T76	31		T77	12		T78	6
valid_sources[0x13]	50982	1			T76	19		T77	9		T78	2
valid_sources[0x14]	52234	1			T76	28		T77	7		T78	1
valid_sources[0x15]	52472	1			T76	26		T77	9		T78	3
valid_sources[0x16]	51471	1			T76	25		T77	8		T78	9
valid_sources[0x17]	51989	1			T76	17		T77	6		T78	11
valid_sources[0x18]	52881	1			T76	29		T77	7		T78	3
valid_sources[0x19]	52273	1			T76	42		T77	8		T78	6
valid_sources[0x1a]	50975	1			T76	18		T77	1		T78	2
valid_sources[0x1b]	51141	1			T76	21		T77	21		T126	5
valid_sources[0x1c]	51817	1			T76	20		T77	11		T78	2
valid_sources[0x1d]	51846	1			T76	31		T77	6		T78	3
valid_sources[0x1e]	53006	1			T76	20		T77	8		T78	2
valid_sources[0x1f]	52753	1			T76	21		T77	7		T78	3
valid_sources[0x20]	52012	1			T76	24		T77	13		T126	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47471

1

T76

25

T77

7

T78

1

values[0x0]

all_enables

biggest_size

358164

1

T76

190

T77

54

T78

20

values[0x1]

all_enables

biggest_size

47510

1

T76

25

T77

6

T78

4

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3062760	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

498768

1

T76

264

T77

85

T78

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1219352	1			T76	680		T77	187		T78	64
values[0x0]	1122516	1			T76	641		T77	175		T78	50
values[0x1]	1219660	1			T76	657		T77	203		T78	72

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2349562	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1211966

1

T76

662

T77

195

T78

54

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55619	1			T76	29		T77	7		T126	3
valid_sources[0x01]	55503	1			T76	35		T77	5		T78	3
valid_sources[0x02]	57263	1			T76	38		T77	4		T78	5
valid_sources[0x03]	55309	1			T76	27		T77	13		T126	5
valid_sources[0x04]	56315	1			T76	39		T77	18		T78	2
valid_sources[0x05]	55619	1			T76	26		T77	12		T78	1
valid_sources[0x06]	55109	1			T76	22		T77	10		T78	5
valid_sources[0x07]	55593	1			T76	34		T77	3		T78	3
valid_sources[0x08]	55494	1			T76	39		T77	23		T126	4
valid_sources[0x09]	55949	1			T76	35		T77	3		T78	1
valid_sources[0x0a]	56662	1			T76	24		T77	6		T78	2
valid_sources[0x0b]	54809	1			T76	31		T77	18		T78	1
valid_sources[0x0c]	55690	1			T76	35		T77	20		T78	1
valid_sources[0x0d]	56201	1			T76	34		T77	5		T78	4
valid_sources[0x0e]	55691	1			T76	20		T77	2		T78	5
valid_sources[0x0f]	56067	1			T76	38		T77	9		T78	1
valid_sources[0x10]	56217	1			T76	24		T77	3		T78	4
valid_sources[0x11]	55408	1			T76	31		T77	4		T78	2
valid_sources[0x12]	55306	1			T76	38		T77	17		T78	1
valid_sources[0x13]	55707	1			T76	37		T77	5		T78	4
valid_sources[0x14]	55561	1			T76	18		T77	6		T126	5
valid_sources[0x15]	55316	1			T76	47		T77	11		T78	5
valid_sources[0x16]	55979	1			T76	21		T77	14		T78	2
valid_sources[0x17]	55686	1			T76	38		T77	4		T78	9
valid_sources[0x18]	56460	1			T76	22		T77	23		T126	5
valid_sources[0x19]	56227	1			T76	37		T77	9		T78	5
valid_sources[0x1a]	56401	1			T76	44		T77	15		T78	8
valid_sources[0x1b]	54856	1			T76	31		T77	21		T78	2
valid_sources[0x1c]	55656	1			T76	29		T77	19		T78	6
valid_sources[0x1d]	55108	1			T76	24		T77	17		T78	1
valid_sources[0x1e]	55330	1			T76	36		T77	17		T78	10
valid_sources[0x1f]	55761	1			T76	22		T77	1		T78	7
valid_sources[0x20]	56958	1			T76	30		T77	9		T126	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

52054

1

T76

31

T77

6

T78

4

values[0x0]

all_enables

biggest_size

394296

1

T76

209

T77

74

T78

13

values[0x1]

all_enables

biggest_size

52418

1

T76

24

T77

5

T78

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2891917	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

456012

1

T76

190

T77

74

T78

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1133891	1			T76	472		T77	184		T78	52
values[0x0]	1079458	1			T76	479		T77	189		T78	48
values[0x1]	1134580	1			T76	489		T77	197		T78	47

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2238098	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1109831

1

T76

477

T77

194

T78

41

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52359	1			T76	1		T77	11		T78	1
valid_sources[0x01]	51370	1			T76	29		T77	4		T78	1
valid_sources[0x02]	53235	1			T76	20		T77	8		T78	1
valid_sources[0x03]	51730	1			T76	26		T77	14		T78	4
valid_sources[0x04]	51758	1			T76	38		T77	7		T78	1
valid_sources[0x05]	52702	1			T76	4		T77	3		T126	3
valid_sources[0x06]	51890	1			T76	31		T77	8		T126	7
valid_sources[0x07]	52711	1			T76	27		T77	8		T126	6
valid_sources[0x08]	52090	1			T76	7		T77	7		T78	1
valid_sources[0x09]	52479	1			T76	41		T77	6		T78	1
valid_sources[0x0a]	51914	1			T76	32		T77	15		T78	2
valid_sources[0x0b]	52404	1			T76	22		T77	14		T78	5
valid_sources[0x0c]	51639	1			T76	29		T77	6		T78	2
valid_sources[0x0d]	52270	1			T76	17		T77	10		T78	4
valid_sources[0x0e]	52376	1			T76	7		T77	5		T78	3
valid_sources[0x0f]	52222	1			T76	26		T77	9		T78	10
valid_sources[0x10]	53697	1			T76	25		T77	8		T126	3
valid_sources[0x11]	51789	1			T76	12		T77	10		T78	1
valid_sources[0x12]	52935	1			T76	10		T77	10		T78	6
valid_sources[0x13]	52762	1			T76	29		T77	10		T126	7
valid_sources[0x14]	51829	1			T76	34		T77	9		T78	5
valid_sources[0x15]	52818	1			T76	18		T77	1		T78	3
valid_sources[0x16]	52143	1			T76	49		T77	7		T126	6
valid_sources[0x17]	51962	1			T76	15		T77	16		T78	1
valid_sources[0x18]	52110	1			T76	23		T77	7		T78	1
valid_sources[0x19]	52078	1			T76	27		T77	6		T78	1
valid_sources[0x1a]	52606	1			T76	14		T77	4		T78	2
valid_sources[0x1b]	52206	1			T76	11		T77	17		T78	2
valid_sources[0x1c]	52125	1			T76	29		T77	14		T78	4
valid_sources[0x1d]	52747	1			T76	22		T77	4		T78	1
valid_sources[0x1e]	52611	1			T76	19		T77	12		T78	6
valid_sources[0x1f]	52826	1			T76	14		T77	8		T78	3
valid_sources[0x20]	52908	1			T76	19		T77	3		T78	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47666

1

T76

21

T77

6

T78

3

values[0x0]

all_enables

biggest_size

360496

1

T76

151

T77

61

T78

12

values[0x1]

all_enables

biggest_size

47850

1

T76

18

T77

7

T78

3