Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	514340554	60817008	0	0
DepthKnown_A	514340554	514232878	0	0
RvalidKnown_A	514340554	514232878	0	0
WreadyKnown_A	514340554	514232878	0	0
gen_passthru_fifo.paramCheckPass	1021	1021	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	60817008	0	0
T4	224574	233266	0	0
T5	156767	21159	0	0
T6	83984	3461	0	0
T17	211715	21222	0	0
T18	152736	20468	0	0
T19	200387	16659	0	0
T41	186388	15932	0	0
T42	276620	36376	0	0
T59	189476	20534	0	0
T60	74119	8407	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	514232878	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	514232878	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	514232878	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	514340554	46534358	0	0
DepthKnown_A	514340554	514232878	0	0
RvalidKnown_A	514340554	514232878	0	0
WreadyKnown_A	514340554	514232878	0	0
gen_passthru_fifo.paramCheckPass	1021	1021	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	46534358	0	0
T4	224574	213694	0	0
T5	156767	16079	0	0
T6	83984	1868	0	0
T17	211715	17312	0	0
T18	152736	15392	0	0
T19	200387	12898	0	0
T41	186388	12166	0	0
T42	276620	26753	0	0
T59	189476	16426	0	0
T60	74119	6138	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	514232878	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	514232878	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	514232878	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	514340554	44283745	0	0
DepthKnown_A	514340554	514232878	0	0
RvalidKnown_A	514340554	514232878	0	0
WreadyKnown_A	514340554	514232878	0	0
gen_passthru_fifo.paramCheckPass	1021	1021	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	44283745	0	0
T4	224574	293730	0	0
T5	156767	9583	0	0
T6	83984	459	0	0
T17	211715	20098	0	0
T18	152736	9100	0	0
T19	200387	9972	0	0
T41	186388	9369	0	0
T42	276620	19057	0	0
T59	189476	12145	0	0
T60	74119	4731	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	514232878	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	514232878	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	514232878	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	514340554	37372788	0	0
DepthKnown_A	514340554	514232878	0	0
RvalidKnown_A	514340554	514232878	0	0
WreadyKnown_A	514340554	514232878	0	0
gen_passthru_fifo.paramCheckPass	1021	1021	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	37372788	0	0
T4	224574	211078	0	0
T5	156767	9315	0	0
T6	83984	351	0	0
T17	211715	19892	0	0
T18	152736	8832	0	0
T19	200387	9718	0	0
T41	186388	9126	0	0
T42	276620	18675	0	0
T59	189476	11878	0	0
T60	74119	4607	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	514232878	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	514232878	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	514232878	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	596733869	106280	0	0
DepthKnown_A	596733869	596609896	0	0
RvalidKnown_A	596733869	596609896	0	0
WreadyKnown_A	596733869	596609896	0	0
gen_passthru_fifo.paramCheckPass	2932	2932	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596733869	106280	0	0
T4	224574	56	0	0
T5	156767	26	0	0
T6	83984	8	0	0
T17	211715	53	0	0
T18	152736	26	0	0
T19	200387	34	0	0
T41	186388	28	0	0
T42	276620	151	0	0
T59	189476	27	0	0
T60	74119	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596733869	596609896	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596733869	596609896	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596733869	596609896	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2932	2932	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	596733869	109607	0	0
DepthKnown_A	596733869	596609896	0	0
RvalidKnown_A	596733869	596609896	0	0
WreadyKnown_A	596733869	596609896	0	0
gen_passthru_fifo.paramCheckPass	2932	2932	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596733869	109607	0	0
T4	224574	56	0	0
T5	156767	26	0	0
T6	83984	8	0	0
T17	211715	53	0	0
T18	152736	26	0	0
T19	200387	34	0	0
T41	186388	28	0	0
T42	276620	151	0	0
T59	189476	27	0	0
T60	74119	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596733869	596609896	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596733869	596609896	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596733869	596609896	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2932	2932	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	596733869	52893	0	0
DepthKnown_A	596733869	596609896	0	0
RvalidKnown_A	596733869	596609896	0	0
WreadyKnown_A	596733869	596609896	0	0
gen_passthru_fifo.paramCheckPass	2932	2932	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596733869	52893	0	0
T4	224574	5	0	0
T5	156767	23	0	0
T6	83984	8	0	0
T17	211715	52	0	0
T18	152736	23	0	0
T19	200387	32	0	0
T41	186388	26	0	0
T42	276620	95	0	0
T59	189476	25	0	0
T60	74119	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596733869	596609896	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596733869	596609896	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596733869	596609896	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2932	2932	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	596733869	52893	0	0
DepthKnown_A	596733869	596609896	0	0
RvalidKnown_A	596733869	596609896	0	0
WreadyKnown_A	596733869	596609896	0	0
gen_passthru_fifo.paramCheckPass	2932	2932	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596733869	52893	0	0
T4	224574	5	0	0
T5	156767	23	0	0
T6	83984	8	0	0
T17	211715	52	0	0
T18	152736	23	0	0
T19	200387	32	0	0
T41	186388	26	0	0
T42	276620	95	0	0
T59	189476	25	0	0
T60	74119	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596733869	596609896	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596733869	596609896	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596733869	596609896	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2932	2932	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	596733869	53387	0	0
DepthKnown_A	596733869	596609896	0	0
RvalidKnown_A	596733869	596609896	0	0
WreadyKnown_A	596733869	596609896	0	0
gen_passthru_fifo.paramCheckPass	2932	2932	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596733869	53387	0	0
T4	224574	51	0	0
T5	156767	3	0	0
T6	83984	0	0	0
T17	211715	1	0	0
T18	152736	3	0	0
T19	200387	2	0	0
T20	0	29	0	0
T41	186388	2	0	0
T42	276620	56	0	0
T59	189476	2	0	0
T60	74119	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596733869	596609896	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596733869	596609896	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596733869	596609896	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2932	2932	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	596733869	56714	0	0
DepthKnown_A	596733869	596609896	0	0
RvalidKnown_A	596733869	596609896	0	0
WreadyKnown_A	596733869	596609896	0	0
gen_passthru_fifo.paramCheckPass	2932	2932	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596733869	56714	0	0
T4	224574	51	0	0
T5	156767	3	0	0
T6	83984	0	0	0
T17	211715	1	0	0
T18	152736	3	0	0
T19	200387	2	0	0
T20	0	29	0	0
T41	186388	2	0	0
T42	276620	56	0	0
T59	189476	2	0	0
T60	74119	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596733869	596609896	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596733869	596609896	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596733869	596609896	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2932	2932	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0