Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_0_en_26.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_0_en_26.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 9 | 90.00 |
Logical | 10 | 9 | 90.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T22,T23 |
1 | 0 | Covered | T2,T9,T13 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T22,T23 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T1,T22,T23 |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T2,T9,T13 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_0_en_27.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_0_en_27.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 9 | 90.00 |
Logical | 10 | 9 | 90.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T22,T23 |
1 | 0 | Covered | T2,T9,T13 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T22,T23 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T1,T22,T23 |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T2,T9,T13 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_0_en_28.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_0_en_28.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 9 | 90.00 |
Logical | 10 | 9 | 90.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T22,T23,T24 |
1 | 0 | Covered | T2,T9,T13 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T22,T23,T24 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T22,T23,T24 |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T2,T9,T13 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_0_en_29.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_0_en_29.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 9 | 90.00 |
Logical | 10 | 9 | 90.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T22,T23,T24 |
1 | 0 | Covered | T2,T9,T13 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T22,T23,T24 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T22,T23,T24 |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T2,T9,T13 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_0_en_30.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_0_en_30.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 9 | 90.00 |
Logical | 10 | 9 | 90.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T22,T23,T24 |
1 | 0 | Covered | T2,T9,T13 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T22,T23,T24 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T22,T23,T24 |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T2,T9,T13 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_0_en_31.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_0_en_31.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 9 | 90.00 |
Logical | 10 | 9 | 90.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T22,T23,T24 |
1 | 0 | Covered | T2,T9,T13 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T22,T23,T24 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T22,T23,T24 |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T2,T9,T13 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_32.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_32.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 9 | 90.00 |
Logical | 10 | 9 | 90.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T22,T23 |
1 | 0 | Covered | T145,T611,T146 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T22,T23 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T1,T22,T23 |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T145,T611,T146 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_33.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_33.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 9 | 90.00 |
Logical | 10 | 9 | 90.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T22,T23 |
1 | 0 | Covered | T145,T611,T146 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T22,T23 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T1,T22,T23 |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T145,T611,T146 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_34.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_34.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 9 | 90.00 |
Logical | 10 | 9 | 90.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T22,T23,T24 |
1 | 0 | Covered | T145,T611,T146 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T22,T23,T24 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T22,T23,T24 |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T145,T611,T146 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_35.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_35.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 9 | 90.00 |
Logical | 10 | 9 | 90.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T22,T23,T24 |
1 | 0 | Covered | T145,T611,T146 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T22,T23,T24 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T22,T23,T24 |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T145,T611,T146 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_36.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_36.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 9 | 90.00 |
Logical | 10 | 9 | 90.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T22,T23,T24 |
1 | 0 | Covered | T145,T611,T146 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T22,T23,T24 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T22,T23,T24 |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T145,T611,T146 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_37.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_37.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 9 | 90.00 |
Logical | 10 | 9 | 90.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T22,T23 |
1 | 0 | Covered | T145,T611,T146 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T22,T23 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T1,T22,T23 |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T145,T611,T146 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_38.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
113 |
1 |
1 |
135 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_status_1_en_38.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 9 | 90.00 |
Logical | 10 | 9 | 90.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T22,T23,T24 |
1 | 0 | Covered | T145,T611,T146 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T22,T23,T24 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T22,T23,T24 |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T145,T611,T146 |