Unified Coverage Report :: Module :: aon_timer

Module : aon_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_aon_timer_0.1/rtl/aon_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_aon_timer_aon	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_aon_timer_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : aon_timer

	Total	Covered	Percent
Totals	38	38	100.00
Total Bits	314	314	100.00
Total Bits 0->1	157	157	100.00
Total Bits 1->0	157	157	100.00

Ports	38	38	100.00
Port Bits	314	314	100.00
Port Bits 0->1	157	157	100.00
Port Bits 1->0	157	157	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_aon_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T41,T42,T19	Yes	T4,T5,T6	INPUT
rst_aon_ni	Yes	Yes	T41,T42,T19	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[21:19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[22]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	INPUT
tl_i.a_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_o.a_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_o.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T126	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T18,T42	Yes	T5,T18,T42	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_o.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T126	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T76,*T77,*T126	Yes	T426,T268,T76	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T55,T82,T358	Yes	T55,T82,T358	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T83,T750	Yes	T82,T83,T84	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T83,T84	Yes	T82,T83,T750	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T55,T82,T358	Yes	T55,T82,T358	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T42,T63,T64	Yes	T42,T63,T64	INPUT
intr_wkup_timer_expired_o	Yes	Yes	T5,T18,T209	Yes	T5,T18,T59	OUTPUT
intr_wdog_timer_bark_o	Yes	Yes	T178,T150,T162	Yes	T178,T150,T162	OUTPUT
nmi_wdog_timer_bark_o	Yes	Yes	T178,T150,T162	Yes	T178,T150,T162	OUTPUT
wkup_req_o	Yes	Yes	T5,T18,T209	Yes	T5,T18,T59	OUTPUT
aon_timer_rst_req_o	Yes	Yes	T178,T173,T751	Yes	T178,T173,T751	OUTPUT
sleep_mode_i	Yes	Yes	T4,T5,T6	Yes	T5,T18,T41	INPUT

*Tests covering at least one bit in the range