Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T41,T42,T59	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	INPUT
tl_i.a_valid	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	INPUT
tl_o.a_ready	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_o.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_o.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T1,*T265,*T268	Yes	T1,T265,T268	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T20,*T52	Yes	T4,T20,T52	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T18,T63,T1	Yes	T18,T63,T1	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T274,T83	Yes	T82,T274,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T274,T83	Yes	T82,T274,T83	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T18,T63,T1	Yes	T18,T63,T1	OUTPUT
cio_rx_i	Yes	Yes	T41,T42,T19	Yes	T5,T6,T17	INPUT
cio_tx_o	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T1,T148,T85	Yes	T1,T148,T85	OUTPUT
intr_tx_empty_o	Yes	Yes	T1,T148,T85	Yes	T1,T148,T85	OUTPUT
intr_rx_watermark_o	Yes	Yes	T148,T85,T228	Yes	T148,T85,T228	OUTPUT
intr_tx_done_o	Yes	Yes	T148,T85,T228	Yes	T148,T85,T228	OUTPUT
intr_rx_overflow_o	Yes	Yes	T148,T85,T228	Yes	T148,T85,T228	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T343,T332,T333	Yes	T343,T332,T333	OUTPUT
intr_rx_break_err_o	Yes	Yes	T343,T332,T333	Yes	T343,T332,T333	OUTPUT
intr_rx_timeout_o	Yes	Yes	T343,T332,T333	Yes	T343,T332,T333	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T343,T332,T333	Yes	T343,T332,T333	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T41,T42,T59	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	INPUT
tl_i.a_valid	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	INPUT
tl_o.a_ready	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_o.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_o.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T1,*T265,*T268	Yes	T1,T265,T268	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T126	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T20,*T52	Yes	T4,T20,T52	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T162,T754	Yes	T1,T162,T754	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T162,T754	Yes	T1,T162,T754	OUTPUT
cio_rx_i	Yes	Yes	T41,T42,T19	Yes	T5,T6,T17	INPUT
cio_tx_o	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T1,T228,T119	Yes	T1,T228,T119	OUTPUT
intr_tx_empty_o	Yes	Yes	T228,T119,T339	Yes	T228,T119,T339	OUTPUT
intr_rx_watermark_o	Yes	Yes	T228,T119,T339	Yes	T228,T119,T339	OUTPUT
intr_tx_done_o	Yes	Yes	T228,T119,T339	Yes	T228,T119,T339	OUTPUT
intr_rx_overflow_o	Yes	Yes	T228,T119,T339	Yes	T228,T119,T339	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T343,T332,T333	Yes	T343,T332,T333	OUTPUT
intr_rx_break_err_o	Yes	Yes	T343,T332,T333	Yes	T343,T332,T333	OUTPUT
intr_rx_timeout_o	Yes	Yes	T343,T332,T333	Yes	T343,T332,T333	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T343,T332,T333	Yes	T343,T332,T333	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T41,T42,T59	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T85,T224	Yes	T1,T85,T224	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T85,T224	Yes	T1,T85,T224	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	INPUT
tl_i.a_valid	Yes	Yes	T1,T162,T85	Yes	T1,T162,T85	INPUT
tl_o.a_ready	Yes	Yes	T1,T162,T85	Yes	T1,T162,T85	OUTPUT
tl_o.d_error	Yes	Yes	T76,T78,T126	Yes	T76,T78,T126	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T85,T224	Yes	T1,T85,T224	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T162,T85	Yes	T1,T162,T85	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T162,T85	Yes	T1,T162,T85	OUTPUT
tl_o.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T1,*T76,*T77	Yes	T1,T76,T77	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T85,*T224	Yes	T1,T85,T224	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T162,T85	Yes	T1,T162,T85	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T18,T1,T162	Yes	T18,T1,T162	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T18,T1,T162	Yes	T18,T1,T162	OUTPUT
cio_rx_i	Yes	Yes	T85,T224,T344	Yes	T85,T26,T22	INPUT
cio_tx_o	Yes	Yes	T1,T85,T224	Yes	T1,T85,T224	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T85,T224,T344	Yes	T85,T224,T344	OUTPUT
intr_tx_empty_o	Yes	Yes	T1,T85,T224	Yes	T1,T85,T224	OUTPUT
intr_rx_watermark_o	Yes	Yes	T85,T224,T344	Yes	T85,T224,T344	OUTPUT
intr_tx_done_o	Yes	Yes	T85,T224,T344	Yes	T85,T224,T344	OUTPUT
intr_rx_overflow_o	Yes	Yes	T85,T224,T344	Yes	T85,T224,T344	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T343,T332,T333	Yes	T343,T332,T333	OUTPUT
intr_rx_break_err_o	Yes	Yes	T343,T332,T333	Yes	T343,T332,T333	OUTPUT
intr_rx_timeout_o	Yes	Yes	T343,T332,T333	Yes	T343,T332,T333	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T343,T332,T333	Yes	T343,T332,T333	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T41,T42,T59	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T148,T149	Yes	T1,T148,T149	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T148,T149	Yes	T1,T148,T149	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	INPUT
tl_i.a_valid	Yes	Yes	T1,T148,T162	Yes	T1,T148,T162	INPUT
tl_o.a_ready	Yes	Yes	T1,T148,T162	Yes	T1,T148,T162	OUTPUT
tl_o.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T148,T149	Yes	T1,T148,T149	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T148,T162	Yes	T1,T148,T162	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T148,T162	Yes	T1,T148,T162	OUTPUT
tl_o.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T1,*T76,*T77	Yes	T1,T76,T77	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T148,*T149	Yes	T1,T148,T149	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T148,T162	Yes	T1,T148,T162	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T162,T755	Yes	T1,T162,T755	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T83,T84	Yes	T82,T83,T84	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T162,T755	Yes	T1,T162,T755	OUTPUT
cio_rx_i	Yes	Yes	T148,T149,T340	Yes	T148,T149,T340	INPUT
cio_tx_o	Yes	Yes	T148,T149,T340	Yes	T148,T149,T340	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T1,T148,T149	Yes	T1,T148,T149	OUTPUT
intr_tx_empty_o	Yes	Yes	T1,T148,T149	Yes	T1,T148,T149	OUTPUT
intr_rx_watermark_o	Yes	Yes	T148,T149,T340	Yes	T148,T149,T340	OUTPUT
intr_tx_done_o	Yes	Yes	T148,T149,T340	Yes	T148,T149,T340	OUTPUT
intr_rx_overflow_o	Yes	Yes	T148,T149,T340	Yes	T148,T149,T340	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T343,T332,T333	Yes	T343,T332,T333	OUTPUT
intr_rx_break_err_o	Yes	Yes	T343,T332,T333	Yes	T343,T332,T333	OUTPUT
intr_rx_timeout_o	Yes	Yes	T343,T332,T333	Yes	T343,T332,T333	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T343,T332,T333	Yes	T343,T332,T333	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T41,T42,T59	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T17,T1,T328	Yes	T17,T1,T328	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T17,T1,T328	Yes	T17,T1,T328	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	INPUT
tl_i.a_valid	Yes	Yes	T17,T1,T162	Yes	T17,T1,T162	INPUT
tl_o.a_ready	Yes	Yes	T17,T1,T162	Yes	T17,T1,T162	OUTPUT
tl_o.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T17,T328,T329	Yes	T17,T328,T329	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T17,T1,T162	Yes	T17,T1,T162	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T17,T1,T162	Yes	T17,T1,T162	OUTPUT
tl_o.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T1,*T76,*T77	Yes	T1,T76,T77	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T17,*T1,*T328	Yes	T17,T1,T328	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T17,T1,T162	Yes	T17,T1,T162	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T63,T1,T162	Yes	T63,T1,T162	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T274,T83	Yes	T82,T274,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T274,T83	Yes	T82,T274,T83	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T63,T1,T162	Yes	T63,T1,T162	OUTPUT
cio_rx_i	Yes	Yes	T17,T328,T329	Yes	T17,T328,T329	INPUT
cio_tx_o	Yes	Yes	T17,T1,T328	Yes	T17,T1,T328	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T17,T328,T329	Yes	T17,T328,T329	OUTPUT
intr_tx_empty_o	Yes	Yes	T17,T328,T329	Yes	T17,T328,T329	OUTPUT
intr_rx_watermark_o	Yes	Yes	T17,T328,T329	Yes	T17,T328,T329	OUTPUT
intr_tx_done_o	Yes	Yes	T17,T328,T329	Yes	T17,T328,T329	OUTPUT
intr_rx_overflow_o	Yes	Yes	T17,T328,T329	Yes	T17,T328,T329	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T343,T332,T333	Yes	T343,T332,T333	OUTPUT
intr_rx_break_err_o	Yes	Yes	T343,T332,T333	Yes	T343,T332,T333	OUTPUT
intr_rx_timeout_o	Yes	Yes	T343,T332,T333	Yes	T343,T332,T333	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T343,T332,T333	Yes	T343,T332,T333	OUTPUT

*Tests covering at least one bit in the range