Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_fixed_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_usb_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host0_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host1_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_main_ni	Yes	Yes	T41,T42,T59	Yes	T4,T5,T6	INPUT
rst_fixed_ni	Yes	Yes	T41,T42,T59	Yes	T4,T5,T6	INPUT
rst_usb_ni	Yes	Yes	T41,T42,T59	Yes	T4,T5,T6	INPUT
rst_spi_host0_ni	Yes	Yes	T41,T42,T59	Yes	T4,T5,T6	INPUT
rst_spi_host1_ni	Yes	Yes	T41,T42,T59	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T76,T78,T126	Yes	T76,T77,T78	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T126,T259,T260	Yes	T126,T259,T260	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T42,T20,T171	Yes	T42,T20,T171	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T42,T20,T171	Yes	T42,T20,T171	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T1,T79,T215	Yes	T1,T79,T215	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T1,T79,T215	Yes	T1,T79,T215	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T42,T20,T63	Yes	T42,T20,T63	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T41,T42,T59	Yes	T5,T17,T60	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T1,T65,T66	Yes	T1,T65,T66	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T41,T42,T59	Yes	T5,T17,T60	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T41,T42,T59	Yes	T5,T17,T60	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T1,T65,T66	Yes	T1,T65,T66	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T41,T42,T59	Yes	T5,T17,T60	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T1,T65,T66	Yes	T1,T65,T66	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T41,T42,T59	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T1,T65,T66	Yes	T1,T65,T66	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T65,T66	Yes	T1,T65,T66	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T1,T65,T66	Yes	T1,T65,T66	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T1,*T65,*T66	Yes	T1,T65,T66	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T1,T65,T66	Yes	T1,T65,T66	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T41,T42,T59	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T1,T11,T76	Yes	T1,T11,T76	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T11,T76	Yes	T1,T11,T76	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T1,T11,T76	Yes	T1,T11,T76	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T1,T11,T76	Yes	T1,T11,T76	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T1,T11,T76	Yes	T1,T11,T76	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T1,*T11,T76	Yes	T1,T11,T76	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T1,T11,T76	Yes	T1,T11,T76	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T1,T11,T76	Yes	T1,T11,T76	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T1,T11,T76	Yes	T1,T11,T76	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T11,T76	Yes	T1,T11,T76	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T1,T11,T76	Yes	T1,T11,T76	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T1,*T11,T76	Yes	T1,T11,T76	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T1,*T11,*T76	Yes	T1,T11,T76	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T1,T11,T76	Yes	T1,T11,T76	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T41,T42,T59	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T265,T266	Yes	T1,T265,T266	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T265,T266	Yes	T1,T265,T266	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T265,T266	Yes	T1,T265,T266	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T1,T265,T266	Yes	T1,T265,T266	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T1,T265,T266	Yes	T1,T265,T266	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T265,*T266,*T267	Yes	T265,T266,T267	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T1,T265,T266	Yes	T1,T265,T266	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T5,T17,T60	Yes	T5,T17,T60	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T5,T17,T60	Yes	T41,T42,T59	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T265,T266,T267	Yes	T265,T266,T267	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T265,T266	Yes	T1,T265,T266	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T5,T17,T60	Yes	T41,T42,T59	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T265,*T266,*T267	Yes	T265,T266,T267	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T5,*T17,*T60	Yes	T41,T42,T59	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T1,T265,T266	Yes	T1,T265,T266	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T20	Yes	T4,T6,T20	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T41,T42,T59	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T1,T55,T56	Yes	T1,T55,T56	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T188,T1,T55	Yes	T188,T1,T55	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T188,T1,T55	Yes	T188,T1,T55	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T1,T55,T56	Yes	T1,T55,T56	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T188,T1,T55	Yes	T188,T1,T55	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T1,*T11,*T76	Yes	T1,T11,T76	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T188,T1,T55	Yes	T188,T1,T55	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T188,T1,T55	Yes	T188,T1,T55	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T188,T98,T416	Yes	T188,T98,T416	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T11,T76	Yes	T1,T55,T56	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T188,T1,T98	Yes	T188,T1,T55	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T1,*T11,T76	Yes	T1,T11,T76	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T188,*T1,*T417	Yes	T188,T1,T417	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T188,T1,T55	Yes	T188,T1,T55	INPUT
tl_peri_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_error	Yes	Yes	T42,T64,T105	Yes	T42,T64,T105	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T25,T162,T26	Yes	T25,T162,T26	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T25,T162,T26	Yes	T25,T162,T26	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T25,T162,T26	Yes	T25,T162,T26	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T25,T162,T26	Yes	T25,T162,T26	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T25,T162,T26	Yes	T25,T162,T26	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T25,T162,T26	Yes	T25,T162,T26	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T27,T210,T213	Yes	T27,T210,T213	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T25,T162,T26	Yes	T25,T162,T26	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T25,T162,T26	Yes	T25,T162,T26	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T25,T26,T400	Yes	T25,T26,T400	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T25,T162,T26	Yes	T25,T162,T26	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T25,T26,T400	Yes	T25,T26,T400	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T76,*T77,*T126	Yes	T76,T77,T78	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T25,*T26,*T400	Yes	T25,T26,T400	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T25,T162,T26	Yes	T25,T162,T26	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T400,T157,T410	Yes	T400,T157,T410	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T400,T157,T410	Yes	T400,T157,T410	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T400,T157,T410	Yes	T400,T157,T410	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T400,T157,T410	Yes	T400,T157,T410	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T400,T157,T410	Yes	T400,T157,T410	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T400,T157,T410	Yes	T400,T157,T410	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T400,T157,T410	Yes	T400,T157,T410	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T400,T157,T410	Yes	T400,T157,T410	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T400,T157,T410	Yes	T400,T157,T410	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T400,T157,T410	Yes	T400,T157,T410	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T400,T157,T410	Yes	T400,T157,T410	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T400,*T157,*T410	Yes	T400,T157,T410	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T400,T157,T410	Yes	T400,T157,T410	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T29,T1,T400	Yes	T29,T1,T400	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T29,T1,T400	Yes	T29,T1,T400	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T29,T1,T400	Yes	T29,T1,T400	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T29,T1,T400	Yes	T29,T1,T400	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T29,T1,T400	Yes	T29,T1,T400	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T29,T1,T400	Yes	T29,T1,T400	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T1,*T76,*T77	Yes	T1,T76,T77	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T76,T77,T126	Yes	T76,T77,T126	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T29,T1,T400	Yes	T29,T1,T400	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T29,T1,T400	Yes	T29,T1,T400	INPUT
tl_usbdev_i.d_error	Yes	Yes	T76,T77,T126	Yes	T76,T77,T126	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T29,T1,T400	Yes	T29,T1,T400	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T29,T1,T400	Yes	T29,T1,T400	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T29,T1,T400	Yes	T29,T1,T400	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T76,T77,T126	Yes	T76,T77,T126	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T1,*T76,*T77	Yes	T1,T76,T77	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T76,T77,T126	Yes	T76,T77,T126	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T29,*T1,*T400	Yes	T29,T1,T400	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T29,T1,T400	Yes	T29,T1,T400	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T79,*T76,*T77	Yes	T79,T76,T77	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T4,T5,T6	Yes	T41,T42,T59	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T41,T42	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T79,*T76,*T77	Yes	T79,T76,T77	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T41,T42,T59	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T79,T76,T77	Yes	T79,T76,T77	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T79,T76,T77	Yes	T79,T76,T77	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T79,T76,T77	Yes	T79,T76,T77	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T79,T76,T77	Yes	T79,T76,T77	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T79,T76,T77	Yes	T79,T76,T77	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T79,T76,T77	Yes	T79,T76,T77	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T79,T76,T77	Yes	T79,T76,T77	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T79,T76,T78	Yes	T79,T76,T77	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T79,T76,T77	Yes	T79,T76,T77	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T79,T76,T77	Yes	T79,T76,T77	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T79,T76,T77	Yes	T79,T76,T77	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T79,T76,T77	Yes	T79,T76,T77	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T79,*T76,*T77	Yes	T79,T76,T77	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T79,T76,T77	Yes	T79,T76,T77	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T17	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T41,T42,T59	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_hmac_o.d_ready	Yes	Yes	T4,T41,T42	Yes	T4,T5,T6	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T79,*T76,*T77	Yes	T79,T76,T77	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T311,T740,T353	Yes	T311,T740,T353	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	INPUT
tl_hmac_i.d_error	Yes	Yes	T76,T78,T126	Yes	T76,T78,T126	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	INPUT
tl_hmac_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T79,*T76,*T77	Yes	T79,T76,T77	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T4,*T20,*T52	Yes	T4,T20,T52	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	INPUT
tl_kmac_o.d_ready	Yes	Yes	T41,T42,T59	Yes	T4,T5,T6	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T155,T304,T229	Yes	T155,T304,T229	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T155,T304,T113	Yes	T155,T304,T113	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T155,T304,T113	Yes	T155,T304,T113	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T155,T304,T229	Yes	T155,T304,T229	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T155,T304,T113	Yes	T155,T304,T113	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T79,*T76,*T77	Yes	T79,T76,T77	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T304,T434,T435	Yes	T304,T434,T435	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T155,T304,T113	Yes	T155,T304,T113	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T155,T304,T113	Yes	T155,T304,T113	INPUT
tl_kmac_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T155,T304,T113	Yes	T155,T304,T113	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T155,T304,T113	Yes	T155,T304,T113	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T155,T304,T113	Yes	T155,T304,T230	INPUT
tl_kmac_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T79,*T76,*T77	Yes	T79,T76,T77	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T155,*T304,*T113	Yes	T304,T230,T434	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T155,T304,T113	Yes	T155,T304,T113	INPUT
tl_aes_o.d_ready	Yes	Yes	T41,T42,T59	Yes	T4,T5,T6	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T113,T732,T377	Yes	T113,T732,T377	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T113,T732,T377	Yes	T113,T732,T377	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T113,T269,T732	Yes	T113,T269,T732	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T113,T732,T377	Yes	T113,T732,T377	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T113,T269,T732	Yes	T113,T269,T732	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T126	Yes	T76,T77,T126	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T113,T269,T732	Yes	T113,T269,T732	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T113,T269,T732	Yes	T113,T269,T732	INPUT
tl_aes_i.d_error	Yes	Yes	T76,T77,T126	Yes	T76,T77,T126	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T113,T269,T732	Yes	T113,T269,T732	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T113,T269,T732	Yes	T113,T269,T732	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T269,T732,T377	Yes	T113,T269,T732	INPUT
tl_aes_i.d_sink	Yes	Yes	T76,T77,T126	Yes	T76,T77,T78	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T76,*T77,*T126	Yes	T76,T77,T126	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T126	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T113,*T269,*T732	Yes	T113,T269,T732	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T113,T269,T732	Yes	T113,T269,T732	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T79,*T76,*T77	Yes	T79,T76,T77	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T60,T124,T125	Yes	T60,T124,T125	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T60,T41	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T4,T60,T41	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T79,*T76,*T77	Yes	T79,T76,T77	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T60,*T20,*T124	Yes	T4,T60,T20	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T60,T112,T113	Yes	T60,T112,T113	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T79,*T76,*T77	Yes	T79,T76,T77	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T60,T112,T113	Yes	T60,T112,T113	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T60,T41,T42	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T41,T42,T59	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T79,*T76,*T77	Yes	T79,T76,T77	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T60,*T112,*T113	Yes	T60,T112,T113	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T60,T112,T113	Yes	T60,T112,T113	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T60,T112,T113	Yes	T60,T112,T113	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T79,*T76,*T77	Yes	T79,T76,T77	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_error	Yes	Yes	T76,T77,T126	Yes	T76,T77,T78	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T60,T112,T113	Yes	T60,T112,T113	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T60,T41,T42	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T60,T41,T42	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_sink	Yes	Yes	T76,T77,T126	Yes	T76,T77,T126	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T79,*T76,*T77	Yes	T79,T76,T77	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T76,T77,T126	Yes	T76,T77,T78	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T60,*T112,*T113	Yes	T60,T112,T113	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn1_o.d_ready	Yes	Yes	T60,T41,T42	Yes	T4,T5,T6	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T60,T112,T113	Yes	T60,T112,T113	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T60,T112,T113	Yes	T60,T112,T113	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T60,T112,T113	Yes	T60,T112,T113	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T60,T112,T113	Yes	T60,T112,T113	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T60,T112,T113	Yes	T60,T112,T113	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T79,*T76,*T77	Yes	T79,T76,T77	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T60,T112,T113	Yes	T60,T112,T113	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T60,T112,T113	Yes	T60,T112,T113	INPUT
tl_edn1_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T60,T112,T113	Yes	T60,T112,T113	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T112,T113,T269	Yes	T60,T112,T113	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T112,T113,T269	Yes	T60,T112,T113	INPUT
tl_edn1_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T79,*T76,*T77	Yes	T79,T76,T77	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T60,*T112,*T113	Yes	T60,T112,T113	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T60,T112,T113	Yes	T60,T112,T113	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T5,T17,T18	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T5,*T17,*T18	Yes	T5,T17,T18	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T5,T17,T18	Yes	T5,T17,T18	INPUT
tl_otbn_o.d_ready	Yes	Yes	T4,T41,T42	Yes	T4,T5,T6	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T81,*T214,*T215	Yes	T81,T214,T215	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	INPUT
tl_otbn_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	INPUT
tl_otbn_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T81,*T214,*T215	Yes	T81,T214,T215	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T4,*T20,*T52	Yes	T4,T20,T52	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T4,T41,T42	Yes	T4,T5,T6	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T20,T52,T172	Yes	T20,T52,T172	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T79,*T76,*T77	Yes	T79,T76,T77	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	INPUT
tl_keymgr_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T155,T113,T229	Yes	T155,T113,T229	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T79,*T76,*T77	Yes	T79,T76,T77	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T4,*T20,*T52	Yes	T4,T20,T52	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T1,*T268,*T11	Yes	T1,T268,T11	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T1,T11,T76	Yes	T1,T11,T76	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T1,*T11,*T76	Yes	T1,T268,T11	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T4,T41,T42	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T426,*T427,*T76	Yes	T426,T427,T76	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T191,T192,T312	Yes	T191,T192,T312	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T20,T21,T51	Yes	T4,T20,T52	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T20,T21,T51	Yes	T4,T20,T52	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T76,*T77,*T126	Yes	T426,T427,T76	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T116,*T117,*T191	Yes	T116,T117,T191	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T41,T42,T59	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range