Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_peri_ni	Yes	Yes	T41,T42,T59	Yes	T4,T5,T6	INPUT
tl_main_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	INPUT
tl_main_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_error	Yes	Yes	T42,T64,T105	Yes	T42,T64,T105	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	INPUT
tl_uart0_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	INPUT
tl_uart0_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T1,*T265,*T268	Yes	T1,T265,T268	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T126	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T4,*T20,*T52	Yes	T4,T20,T52	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	INPUT
tl_uart1_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T1,T85,T224	Yes	T1,T85,T224	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T1,T85,T224	Yes	T1,T85,T224	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T1,T162,T85	Yes	T1,T162,T85	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T1,T162,T85	Yes	T1,T162,T85	INPUT
tl_uart1_i.d_error	Yes	Yes	T76,T78,T126	Yes	T76,T78,T126	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T1,T85,T224	Yes	T1,T85,T224	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T162,T85	Yes	T1,T162,T85	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T1,T162,T85	Yes	T1,T162,T85	INPUT
tl_uart1_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T1,*T76,*T77	Yes	T1,T76,T77	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T1,*T85,*T224	Yes	T1,T85,T224	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T1,T162,T85	Yes	T1,T162,T85	INPUT
tl_uart2_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T1,T148,T149	Yes	T1,T148,T149	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T1,T148,T149	Yes	T1,T148,T149	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T1,T148,T162	Yes	T1,T148,T162	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T1,T148,T162	Yes	T1,T148,T162	INPUT
tl_uart2_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T1,T148,T149	Yes	T1,T148,T149	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T148,T162	Yes	T1,T148,T162	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T1,T148,T162	Yes	T1,T148,T162	INPUT
tl_uart2_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T1,*T76,*T77	Yes	T1,T76,T77	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T1,*T148,*T149	Yes	T1,T148,T149	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T1,T148,T162	Yes	T1,T148,T162	INPUT
tl_uart3_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T17,T1,T328	Yes	T17,T1,T328	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T17,T1,T328	Yes	T17,T1,T328	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T17,T1,T162	Yes	T17,T1,T162	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T17,T1,T162	Yes	T17,T1,T162	INPUT
tl_uart3_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T17,T328,T329	Yes	T17,T328,T329	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T1,T162	Yes	T17,T1,T162	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T17,T1,T162	Yes	T17,T1,T162	INPUT
tl_uart3_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T1,*T76,*T77	Yes	T1,T76,T77	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T17,*T1,*T328	Yes	T17,T1,T328	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T17,T1,T162	Yes	T17,T1,T162	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T400,T322,T79	Yes	T400,T322,T79	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T400,T322,T79	Yes	T400,T322,T79	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T162,T400,T322	Yes	T162,T400,T322	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T162,T400,T322	Yes	T162,T400,T322	INPUT
tl_i2c0_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T126	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T322,T79,T330	Yes	T322,T79,T330	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T162,T400,T322	Yes	T162,T400,T322	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T162,T400,T322	Yes	T162,T400,T322	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T79,*T76,*T77	Yes	T79,T76,T77	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T76,T77,T126	Yes	T76,T77,T78	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T400,*T322,*T79	Yes	T400,T322,T79	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T162,T400,T322	Yes	T162,T400,T322	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T225,T226,T400	Yes	T225,T226,T400	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T225,T226,T400	Yes	T225,T226,T400	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T225,T226,T162	Yes	T225,T226,T162	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T225,T226,T162	Yes	T225,T226,T162	INPUT
tl_i2c1_i.d_error	Yes	Yes	T76,T77,T126	Yes	T76,T77,T126	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T225,T226,T322	Yes	T225,T226,T322	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T225,T226,T162	Yes	T225,T226,T162	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T225,T226,T162	Yes	T225,T226,T162	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T79,*T76,*T77	Yes	T79,T76,T77	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T76,T77,T126	Yes	T76,T77,T78	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T225,*T226,*T400	Yes	T225,T226,T400	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T225,T226,T162	Yes	T225,T226,T162	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T400,T322,T79	Yes	T400,T322,T79	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T400,T322,T79	Yes	T400,T322,T79	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T162,T400,T322	Yes	T162,T400,T322	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T162,T400,T322	Yes	T162,T400,T322	INPUT
tl_i2c2_i.d_error	Yes	Yes	T76,T77,T126	Yes	T76,T77,T126	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T322,T79,T342	Yes	T322,T79,T342	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T162,T400,T322	Yes	T162,T400,T322	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T162,T400,T322	Yes	T162,T400,T322	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T79,*T76,*T77	Yes	T79,T76,T77	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T400,*T322,*T79	Yes	T400,T322,T79	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T162,T400,T322	Yes	T162,T400,T322	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T157,T158,T159	Yes	T157,T158,T159	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T157,T158,T159	Yes	T157,T158,T159	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T157,T55,T158	Yes	T157,T55,T158	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T157,T55,T158	Yes	T157,T55,T158	INPUT
tl_pattgen_i.d_error	Yes	Yes	T76,T77,T126	Yes	T76,T77,T126	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T157,T158,T159	Yes	T157,T158,T159	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T157,T158,T159	Yes	T157,T55,T158	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T157,T158,T159	Yes	T157,T55,T158	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	T76,T77,T126	Yes	T76,T77,T78	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T157,*T158,*T159	Yes	T157,T158,T159	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T157,T55,T158	Yes	T157,T55,T158	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T150,T227	Yes	T1,T150,T227	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T1,T150,T227	Yes	T1,T150,T227	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T1,T150,T227	Yes	T1,T150,T227	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T1,T150,T227	Yes	T1,T150,T227	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T150,T227	Yes	T1,T150,T227	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T150,T227	Yes	T1,T150,T227	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T1,T150,T227	Yes	T1,T150,T227	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	*T1,*T11,T76	Yes	T1,T11,T76	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T1,*T150,*T227	Yes	T1,T150,T227	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T1,T150,T227	Yes	T1,T150,T227	INPUT
tl_gpio_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_gpio_i.d_error	Yes	Yes	T76,T77,T126	Yes	T76,T77,T126	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T28,T322,T79	Yes	T28,T322,T79	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T28,T322,T79	Yes	T150,T2,T28	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T28,T322,T79	Yes	T150,T2,T28	INPUT
tl_gpio_i.d_sink	Yes	Yes	T76,T77,T126	Yes	T76,T77,T126	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T79,*T76,*T77	Yes	T79,T76,T77	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T76,T77,T126	Yes	T76,T77,T126	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T41,*T42,*T59	Yes	T4,T5,T17	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T25,T85,T86	Yes	T25,T85,T86	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T25,T85,T86	Yes	T25,T85,T86	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T25,T85,T86	Yes	T25,T85,T86	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T25,T85,T86	Yes	T25,T85,T86	INPUT
tl_spi_device_i.d_error	Yes	Yes	T76,T78,T126	Yes	T76,T126,T152	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T25,T85,T86	Yes	T25,T85,T86	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T25,T85,T86	Yes	T25,T85,T86	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T25,T85,T86	Yes	T25,T85,T86	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T76,T77,T126	Yes	T76,T77,T126	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T76,*T77,*T126	Yes	T76,T77,T126	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T25,*T85,*T86	Yes	T25,T85,T86	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T25,T85,T86	Yes	T25,T85,T86	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T150,T106,T298	Yes	T150,T106,T298	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T150,T106,T298	Yes	T150,T106,T298	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T150,T106,T298	Yes	T150,T106,T298	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T150,T106,T298	Yes	T150,T106,T298	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T76,T77,T126	Yes	T76,T77,T126	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T106,T298,T264	Yes	T106,T298,T264	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T150,T106,T298	Yes	T150,T106,T298	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T150,T106,T298	Yes	T150,T106,T298	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T76,T77,T126	Yes	T76,T77,T78	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T76,*T77,*T126	Yes	T76,T77,T78	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T150,*T106,*T298	Yes	T150,T106,T298	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T150,T106,T298	Yes	T150,T106,T298	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T76,T126,T152	Yes	T76,T126,T152	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T126	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T1,*T11,*T76	Yes	T1,T11,T76	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T126	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T41,T42	Yes	T4,T5,T17	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T4,T41,T42	Yes	T4,T5,T17	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T1,*T11,*T76	Yes	T1,T11,T76	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T126	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T17,T42,T115	Yes	T17,T42,T115	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T17,T42,T112	Yes	T17,T42,T112	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T17,T42,T115	Yes	T17,T42,T115	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T41,T42	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T17,T41,T42	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T76,*T77,*T126	Yes	T80,T153,T748	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T17,*T42,*T115	Yes	T17,T42,T115	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T1,*T11,*T76	Yes	T1,T11,T76	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T76,T78,T152	Yes	T76,T78,T152	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T80,*T153,*T154	Yes	T80,T153,T154	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T155,*T113,*T156	Yes	T155,T113,T156	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T5,T17,T60	Yes	T5,T17,T60	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T5,T17,T60	Yes	T41,T42,T59	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T5,T17,T60	Yes	T41,T42,T59	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	T76,T77,T126	Yes	T76,T77,T78	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T5,*T17,*T60	Yes	T41,T42,T59	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T4,T19,T20	Yes	T4,T19,T20	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T4,T19,T20	Yes	T4,T19,T20	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T4,T19,T20	Yes	T4,T19,T20	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T4,T19,T20	Yes	T4,T19,T20	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T4,T19,T20	Yes	T4,T19,T20	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T19,T61,T53	Yes	T19,T61,T53	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T4,T19,T20	Yes	T4,T19,T20	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T76,T77,T126	Yes	T76,T77,T78	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T267,*T371,*T372	Yes	T267,T371,T372	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T19,*T20,*T21	Yes	T4,T19,T20	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T4,T19,T20	Yes	T4,T19,T20	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T52,T21	Yes	T4,T52,T21	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T52,T21	Yes	T4,T52,T21	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T4,T41,T42	Yes	T4,T5,T6	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T76,*T77,*T126	Yes	T76,T77,T78	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T4,*T41,*T42	Yes	T4,T5,T6	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T76,T77,T126	Yes	T76,T77,T126	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T76,*T77,*T126	Yes	T76,T77,T78	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T5,*T18,*T42	Yes	T4,T5,T18	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T126	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T116,T117,T189	Yes	T116,T117,T189	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T20,T21,T51	Yes	T4,T20,T52	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T20,T21,T51	Yes	T4,T20,T52	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T76,*T77,*T126	Yes	T76,T77,T78	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T126	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T116,*T117,*T189	Yes	T116,T117,T189	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T4,T20,T52	Yes	T4,T20,T52	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T41,T42,T19	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T81,*T214,*T215	Yes	T81,T214,T215	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T17	Yes	T4,T5,T17	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T4,T5,T17	Yes	T4,T5,T17	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T126	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T5,T18,T42	Yes	T5,T18,T42	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T126	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T76,*T77,*T126	Yes	T426,T268,T76	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T178,T444,T198	Yes	T178,T444,T198	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T178,T444,T198	Yes	T178,T444,T198	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T178,T444,T198	Yes	T178,T444,T198	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T178,T444,T198	Yes	T178,T444,T198	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T178,T444,T198	Yes	T178,T444,T198	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T178,T444,T198	Yes	T178,T444,T198	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T178,T444,T198	Yes	T178,T444,T198	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T1,*T76,*T77	Yes	T1,T76,T77	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T178,*T444,*T198	Yes	T178,T444,T198	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T178,T444,T198	Yes	T178,T444,T198	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T322,T108,T3	Yes	T322,T108,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T322,T108,T3	Yes	T322,T108,T3	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T322,T108,T3	Yes	T322,T108,T3	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T322,T108,T3	Yes	T322,T108,T3	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T322,T108,T3	Yes	T322,T108,T3	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T322,T108,T3	Yes	T322,T108,T3	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T108,T3,T109	Yes	T322,T108,T3	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T322,*T108,*T3	Yes	T322,T108,T3	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T322,T108,T3	Yes	T322,T108,T3	INPUT
tl_ast_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T1,*T79,*T80	Yes	T1,T79,T80	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T1,T79,T81	Yes	T1,T79,T81	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_ast_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T41,T42,T59	Yes	T4,T5,T6	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T41,T42,T59	Yes	T4,T5,T6	INPUT
tl_ast_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	*T76,*T77,*T126	Yes	T76,T77,T78	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range