SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
85.02 | 85.02 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.top_earlgrey.u_otp_ctrl | 85.21 | 85.21 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
85.21 | 85.21 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
85.21 | 85.21 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
93.34 | 90.68 | 89.34 | 100.00 | top_earlgrey |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Covered | Percent | |
---|---|---|---|
Totals | 164 | 141 | 85.98 |
Total Bits | 11012 | 9362 | 85.02 |
Total Bits 0->1 | 5506 | 4696 | 85.29 |
Total Bits 1->0 | 5506 | 4666 | 84.74 |
Ports | 164 | 141 | 85.98 |
Port Bits | 11012 | 9362 | 85.02 |
Port Bits 0->1 | 5506 | 4696 | 85.29 |
Port Bits 1->0 | 5506 | 4666 | 84.74 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
rst_ni | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T6 | INPUT |
clk_edn_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
rst_edn_ni | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T6 | INPUT |
edn_o.edn_req | Yes | Yes | T4,T5,T17 | Yes | T4,T5,T17 | OUTPUT |
edn_i.edn_bus[31:0] | Yes | Yes | T4,T5,T17 | Yes | T4,T5,T17 | INPUT |
edn_i.edn_fips | No | No | Yes | T112,T114,T151 | INPUT | |
edn_i.edn_ack | Yes | Yes | T4,T5,T17 | Yes | T4,T5,T17 | INPUT |
core_tl_i.d_ready | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
core_tl_i.a_user.data_intg[6:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
core_tl_i.a_user.cmd_intg[6:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
core_tl_i.a_user.instr_type[3:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
core_tl_i.a_user.rsvd[4:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
core_tl_i.a_data[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
core_tl_i.a_mask[3:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
core_tl_i.a_address[11:0] | Yes | Yes | *T76,*T77,*T78 | Yes | T76,T77,T78 | INPUT |
core_tl_i.a_address[15:12] | Unreachable | Unreachable | Unreachable | INPUT | ||
core_tl_i.a_address[17:16] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
core_tl_i.a_address[19:18] | Unreachable | Unreachable | Unreachable | INPUT | ||
core_tl_i.a_address[20] | Yes | Yes | *T4,*T5,*T6 | Yes | T4,T5,T6 | INPUT |
core_tl_i.a_address[29:21] | Unreachable | Unreachable | Unreachable | INPUT | ||
core_tl_i.a_address[30] | Yes | Yes | *T4,*T5,*T6 | Yes | T4,T5,T6 | INPUT |
core_tl_i.a_address[31] | Unreachable | Unreachable | Unreachable | INPUT | ||
core_tl_i.a_source[5:0] | Yes | Yes | *T1,*T79,*T80 | Yes | T1,T79,T80 | INPUT |
core_tl_i.a_source[7:6] | Unreachable | Unreachable | Unreachable | INPUT | ||
core_tl_i.a_size[1:0] | Yes | Yes | T76,T77,T78 | Yes | T76,T77,T78 | INPUT |
core_tl_i.a_param[2:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
core_tl_i.a_opcode[2:0] | Yes | Yes | T1,T79,T81 | Yes | T1,T79,T81 | INPUT |
core_tl_i.a_valid | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
core_tl_o.a_ready | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
core_tl_o.d_error | Yes | Yes | T76,T78,T152 | Yes | T76,T78,T152 | OUTPUT |
core_tl_o.d_user.data_intg[6:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
core_tl_o.d_user.rsp_intg[6:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
core_tl_o.d_data[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
core_tl_o.d_sink | Yes | Yes | T76,T77,T78 | Yes | T76,T77,T78 | OUTPUT |
core_tl_o.d_source[5:0] | Yes | Yes | *T80,*T153,*T154 | Yes | T80,T153,T154 | OUTPUT |
core_tl_o.d_source[7:6] | Unreachable | Unreachable | Unreachable | OUTPUT | ||
core_tl_o.d_size[1:0] | Yes | Yes | T76,T77,T78 | Yes | T76,T77,T78 | OUTPUT |
core_tl_o.d_param[2:0] | Unreachable | Unreachable | Unreachable | OUTPUT | ||
core_tl_o.d_opcode[0] | Yes | Yes | *T155,*T113,*T156 | Yes | T155,T113,T156 | OUTPUT |
core_tl_o.d_opcode[2:1] | Unreachable | Unreachable | Unreachable | OUTPUT | ||
core_tl_o.d_valid | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
prim_tl_i.d_ready | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
prim_tl_i.a_user.data_intg[6:0] | Yes | Yes | T76,T77,T78 | Yes | T76,T77,T78 | INPUT |
prim_tl_i.a_user.cmd_intg[6:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
prim_tl_i.a_user.instr_type[3:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
prim_tl_i.a_user.rsvd[4:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
prim_tl_i.a_data[31:0] | Yes | Yes | T76,T77,T78 | Yes | T76,T77,T78 | INPUT |
prim_tl_i.a_mask[3:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
prim_tl_i.a_address[4:0] | Yes | Yes | *T76,*T77,*T78 | Yes | T76,T77,T78 | INPUT |
prim_tl_i.a_address[14:5] | Unreachable | Unreachable | Unreachable | INPUT | ||
prim_tl_i.a_address[17:15] | Yes | Yes | *T76,*T77,*T78 | Yes | T76,T77,T78 | INPUT |
prim_tl_i.a_address[19:18] | Unreachable | Unreachable | Unreachable | INPUT | ||
prim_tl_i.a_address[20] | Yes | Yes | *T4,*T5,*T6 | Yes | T4,T5,T6 | INPUT |
prim_tl_i.a_address[29:21] | Unreachable | Unreachable | Unreachable | INPUT | ||
prim_tl_i.a_address[30] | Yes | Yes | *T4,*T5,*T6 | Yes | T4,T5,T6 | INPUT |
prim_tl_i.a_address[31] | Unreachable | Unreachable | Unreachable | INPUT | ||
prim_tl_i.a_source[5:0] | Yes | Yes | *T1,*T79,*T80 | Yes | T1,T79,T80 | INPUT |
prim_tl_i.a_source[7:6] | Unreachable | Unreachable | Unreachable | INPUT | ||
prim_tl_i.a_size[1:0] | Yes | Yes | T76,T77,T78 | Yes | T76,T77,T78 | INPUT |
prim_tl_i.a_param[2:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
prim_tl_i.a_opcode[2:0] | Yes | Yes | T1,T79,T81 | Yes | T1,T79,T81 | INPUT |
prim_tl_i.a_valid | Yes | Yes | T76,T77,T78 | Yes | T76,T77,T78 | INPUT |
prim_tl_o.a_ready | Yes | Yes | T5,T17,T60 | Yes | T5,T17,T60 | OUTPUT |
prim_tl_o.d_error | Yes | Yes | T5,T17,T60 | Yes | T41,T42,T59 | OUTPUT |
prim_tl_o.d_user.data_intg[6:0] | Yes | Yes | T76,T77,T78 | Yes | T76,T77,T78 | OUTPUT |
prim_tl_o.d_user.rsp_intg[6:0] | Yes | Yes | T76,T77,T78 | Yes | T76,T77,T78 | OUTPUT |
prim_tl_o.d_data[31:0] | Yes | Yes | T5,T17,T60 | Yes | T41,T42,T59 | OUTPUT |
prim_tl_o.d_sink | Yes | Yes | T76,T77,T78 | Yes | T76,T77,T78 | OUTPUT |
prim_tl_o.d_source[5:0] | Yes | Yes | T76,T77,T126 | Yes | T76,T77,T78 | OUTPUT |
prim_tl_o.d_source[7:6] | Unreachable | Unreachable | Unreachable | OUTPUT | ||
prim_tl_o.d_size[1:0] | Yes | Yes | T76,T77,T78 | Yes | T76,T77,T78 | OUTPUT |
prim_tl_o.d_param[2:0] | Unreachable | Unreachable | Unreachable | OUTPUT | ||
prim_tl_o.d_opcode[0] | Yes | Yes | *T5,*T17,*T60 | Yes | T41,T42,T59 | OUTPUT |
prim_tl_o.d_opcode[2:1] | Unreachable | Unreachable | Unreachable | OUTPUT | ||
prim_tl_o.d_valid | Yes | Yes | T76,T77,T78 | Yes | T76,T77,T78 | OUTPUT |
intr_otp_operation_done_o | Yes | Yes | T157,T158,T159 | Yes | T157,T158,T159 | OUTPUT |
intr_otp_error_o | Yes | Yes | T157,T158,T159 | Yes | T157,T158,T159 | OUTPUT |
alert_rx_i[0].ack_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
alert_rx_i[0].ack_p | Yes | Yes | T55,T82,T160 | Yes | T55,T82,T160 | INPUT |
alert_rx_i[0].ping_n | Yes | Yes | T82,T83,T84 | Yes | T82,T83,T84 | INPUT |
alert_rx_i[0].ping_p | Yes | Yes | T82,T83,T84 | Yes | T82,T83,T84 | INPUT |
alert_rx_i[1].ack_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
alert_rx_i[1].ack_p | Yes | Yes | T42,T63,T64 | Yes | T42,T63,T64 | INPUT |
alert_rx_i[1].ping_n | Yes | Yes | T161,T82,T83 | Yes | T82,T83,T84 | INPUT |
alert_rx_i[1].ping_p | Yes | Yes | T82,T83,T84 | Yes | T161,T82,T83 | INPUT |
alert_rx_i[2].ack_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
alert_rx_i[2].ack_p | Yes | Yes | T162,T55,T82 | Yes | T162,T55,T82 | INPUT |
alert_rx_i[2].ping_n | Yes | Yes | T82,T83,T84 | Yes | T82,T83,T84 | INPUT |
alert_rx_i[2].ping_p | Yes | Yes | T82,T83,T84 | Yes | T82,T83,T84 | INPUT |
alert_rx_i[3].ack_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
alert_rx_i[3].ack_p | Yes | Yes | T163,T164,T165 | Yes | T163,T164,T165 | INPUT |
alert_rx_i[3].ping_n | Yes | Yes | T82,T83,T84 | Yes | T82,T83,T84 | INPUT |
alert_rx_i[3].ping_p | Yes | Yes | T82,T83,T84 | Yes | T82,T83,T84 | INPUT |
alert_rx_i[4].ack_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
alert_rx_i[4].ack_p | Yes | Yes | T55,T166,T82 | Yes | T55,T166,T82 | INPUT |
alert_rx_i[4].ping_n | Yes | Yes | T166,T82,T83 | Yes | T166,T82,T83 | INPUT |
alert_rx_i[4].ping_p | Yes | Yes | T166,T82,T83 | Yes | T166,T82,T83 | INPUT |
alert_tx_o[0].alert_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
alert_tx_o[0].alert_p | Yes | Yes | T55,T82,T160 | Yes | T55,T82,T160 | OUTPUT |
alert_tx_o[1].alert_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
alert_tx_o[1].alert_p | Yes | Yes | T42,T63,T64 | Yes | T42,T63,T64 | OUTPUT |
alert_tx_o[2].alert_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
alert_tx_o[2].alert_p | Yes | Yes | T162,T55,T82 | Yes | T162,T55,T82 | OUTPUT |
alert_tx_o[3].alert_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
alert_tx_o[3].alert_p | Yes | Yes | T163,T164,T165 | Yes | T163,T164,T165 | OUTPUT |
alert_tx_o[4].alert_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT |
alert_tx_o[4].alert_p | Yes | Yes | T55,T166,T82 | Yes | T55,T166,T82 | OUTPUT |
obs_ctrl_i.obmen[3:0] | No | No | No | INPUT | ||
obs_ctrl_i.obmsl[3:0] | No | No | No | INPUT | ||
obs_ctrl_i.obgsl[3:0] | No | No | No | INPUT | ||
otp_obs_o[7:0] | Unreachable | Unreachable | Unreachable | OUTPUT | ||
otp_ast_pwr_seq_o.pwr_seq[1:0] | No | No | No | OUTPUT | ||
otp_ast_pwr_seq_h_i.pwr_seq_h[0] | No | No | No | INPUT | ||
otp_ast_pwr_seq_h_i.pwr_seq_h[1] | Yes | Yes | T4,T5,T6 | Yes | T41,T59,T68 | INPUT |
pwr_otp_i.otp_init | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT |
pwr_otp_o.otp_idle | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T6 | OUTPUT |
pwr_otp_o.otp_done | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T6 | OUTPUT |
lc_otp_vendor_test_i.ctrl[12:0] | No | No | Yes | T167,T168,T169 | INPUT | |
lc_otp_vendor_test_i.ctrl[13] | No | No | No | INPUT | ||
lc_otp_vendor_test_i.ctrl[21:14] | No | No | Yes | T169,T168,T167 | INPUT | |
lc_otp_vendor_test_i.ctrl[22] | No | No | No | INPUT | ||
lc_otp_vendor_test_i.ctrl[24:23] | No | No | Yes | T167,T169,T168 | INPUT | |
lc_otp_vendor_test_i.ctrl[25] | No | No | No | INPUT | ||
lc_otp_vendor_test_i.ctrl[26] | No | No | Yes | T169 | INPUT | |
lc_otp_vendor_test_i.ctrl[27] | No | No | No | INPUT | ||
lc_otp_vendor_test_i.ctrl[31:28] | No | No | Yes | T169,T168,T167 | INPUT | |
lc_otp_vendor_test_o.status[31:0] | No | No | No | OUTPUT | ||
lc_otp_program_i.count[0] | No | No | No | INPUT | ||
lc_otp_program_i.count[11:1] | Yes | Yes | *T62,*T170,*T118 | Yes | T62,T170,T118 | INPUT |
lc_otp_program_i.count[12] | No | No | No | INPUT | ||
lc_otp_program_i.count[13] | Yes | Yes | *T62,*T170,*T118 | Yes | T62,T170,T118 | INPUT |
lc_otp_program_i.count[14] | No | No | No | INPUT | ||
lc_otp_program_i.count[20:15] | Yes | Yes | *T171,*T62,*T170 | Yes | T171,T62,T170 | INPUT |
lc_otp_program_i.count[21] | No | No | No | INPUT | ||
lc_otp_program_i.count[22] | Yes | Yes | *T172,*T51,*T173 | Yes | T51,T173,T171 | INPUT |
lc_otp_program_i.count[23] | No | No | No | INPUT | ||
lc_otp_program_i.count[25:24] | Yes | Yes | *T172,*T51,*T173 | Yes | T51,T173,T174 | INPUT |
lc_otp_program_i.count[26] | No | No | No | INPUT | ||
lc_otp_program_i.count[51:27] | Yes | Yes | *T172,*T51,*T173 | Yes | T51,T173,T171 | INPUT |
lc_otp_program_i.count[52] | No | No | No | INPUT | ||
lc_otp_program_i.count[60:53] | Yes | Yes | *T171,*T175,*T160 | Yes | T171,T175,T160 | INPUT |
lc_otp_program_i.count[61] | No | No | No | INPUT | ||
lc_otp_program_i.count[65:62] | Yes | Yes | *T172,*T51,*T173 | Yes | T51,T173,T171 | INPUT |
lc_otp_program_i.count[66] | No | No | No | INPUT | ||
lc_otp_program_i.count[70:67] | Yes | Yes | *T172,*T51,*T173 | Yes | T51,T173,T174 | INPUT |
lc_otp_program_i.count[71] | No | No | No | INPUT | ||
lc_otp_program_i.count[77:72] | Yes | Yes | *T172,*T51,*T173 | Yes | T51,T173,T171 | INPUT |
lc_otp_program_i.count[78] | No | No | No | INPUT | ||
lc_otp_program_i.count[91:79] | Yes | Yes | *T62,*T170,*T118 | Yes | T62,T170,T118 | INPUT |
lc_otp_program_i.count[92] | No | No | No | INPUT | ||
lc_otp_program_i.count[106:93] | Yes | Yes | *T171,*T175,*T160 | Yes | T171,T175,T160 | INPUT |
lc_otp_program_i.count[109:107] | No | No | No | INPUT | ||
lc_otp_program_i.count[110] | Yes | Yes | *T171,*T62,*T170 | Yes | T171,T62,T170 | INPUT |
lc_otp_program_i.count[111] | No | No | No | INPUT | ||
lc_otp_program_i.count[113:112] | Yes | Yes | T171,*T62,*T170 | Yes | T171,T62,T170 | INPUT |
lc_otp_program_i.count[114] | No | No | No | INPUT | ||
lc_otp_program_i.count[116:115] | Yes | Yes | T171,*T62,*T170 | Yes | T171,T62,T170 | INPUT |
lc_otp_program_i.count[117] | No | No | No | INPUT | ||
lc_otp_program_i.count[118] | Yes | Yes | *T4,*T6,*T54 | Yes | T21,T51,T173 | INPUT |
lc_otp_program_i.count[119] | No | No | No | INPUT | ||
lc_otp_program_i.count[127:120] | Yes | Yes | *T62,*T170,*T118 | Yes | T62,T170,T118 | INPUT |
lc_otp_program_i.count[128] | No | No | No | INPUT | ||
lc_otp_program_i.count[144:129] | Yes | Yes | *T171,*T175,*T160 | Yes | T171,T175,T160 | INPUT |
lc_otp_program_i.count[145] | No | No | No | INPUT | ||
lc_otp_program_i.count[146] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | INPUT |
lc_otp_program_i.count[147] | No | No | No | INPUT | ||
lc_otp_program_i.count[151:148] | Yes | Yes | *T62,*T170,*T118 | Yes | T62,T170,T118 | INPUT |
lc_otp_program_i.count[152] | No | No | No | INPUT | ||
lc_otp_program_i.count[154:153] | Yes | Yes | *T171,*T175,*T160 | Yes | T171,T175,T160 | INPUT |
lc_otp_program_i.count[155] | No | No | No | INPUT | ||
lc_otp_program_i.count[160:156] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | INPUT |
lc_otp_program_i.count[161] | No | No | No | INPUT | ||
lc_otp_program_i.count[165:162] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | INPUT |
lc_otp_program_i.count[166] | No | No | No | INPUT | ||
lc_otp_program_i.count[169:167] | Yes | Yes | *T62,*T170,*T118 | Yes | T62,T170,T118 | INPUT |
lc_otp_program_i.count[171:170] | No | No | No | INPUT | ||
lc_otp_program_i.count[177:172] | Yes | Yes | *T171,*T62,*T170 | Yes | T171,T62,T170 | INPUT |
lc_otp_program_i.count[178] | No | No | No | INPUT | ||
lc_otp_program_i.count[180:179] | Yes | Yes | T171,T175,*T160 | Yes | T171,T175,T160 | INPUT |
lc_otp_program_i.count[181] | No | No | No | INPUT | ||
lc_otp_program_i.count[189:182] | Yes | Yes | *T171,*T175,*T160 | Yes | T171,T175,T160 | INPUT |
lc_otp_program_i.count[190] | No | No | No | INPUT | ||
lc_otp_program_i.count[193:191] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | INPUT |
lc_otp_program_i.count[194] | No | No | No | INPUT | ||
lc_otp_program_i.count[196:195] | Yes | Yes | *T171,*T175,*T160 | Yes | T171,T175,T160 | INPUT |
lc_otp_program_i.count[197] | No | No | No | INPUT | ||
lc_otp_program_i.count[212:198] | Yes | Yes | *T62,*T170,*T118 | Yes | T62,T170,T118 | INPUT |
lc_otp_program_i.count[214:213] | No | No | No | INPUT | ||
lc_otp_program_i.count[223:215] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | INPUT |
lc_otp_program_i.count[224] | No | No | No | INPUT | ||
lc_otp_program_i.count[229:225] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | INPUT |
lc_otp_program_i.count[231:230] | No | No | No | INPUT | ||
lc_otp_program_i.count[239:232] | Yes | Yes | *T62,*T170,*T118 | Yes | T62,T170,T118 | INPUT |
lc_otp_program_i.count[240] | No | No | No | INPUT | ||
lc_otp_program_i.count[242:241] | Yes | Yes | *T171,*T175,*T160 | Yes | T171,T175,T160 | INPUT |
lc_otp_program_i.count[243] | No | No | No | INPUT | ||
lc_otp_program_i.count[245:244] | Yes | Yes | T62,T170,T118 | Yes | T62,T170,T118 | INPUT |
lc_otp_program_i.count[247:246] | No | No | No | INPUT | ||
lc_otp_program_i.count[256:248] | Yes | Yes | *T171,*T62,*T170 | Yes | T171,T62,T170 | INPUT |
lc_otp_program_i.count[257] | No | No | No | INPUT | ||
lc_otp_program_i.count[261:258] | Yes | Yes | *T171,*T62,*T170 | Yes | T171,T62,T170 | INPUT |
lc_otp_program_i.count[262] | No | No | No | INPUT | ||
lc_otp_program_i.count[284:263] | Yes | Yes | *T62,*T170,*T118 | Yes | T62,T170,T118 | INPUT |
lc_otp_program_i.count[285] | No | No | No | INPUT | ||
lc_otp_program_i.count[288:286] | Yes | Yes | *T171,*T175,*T160 | Yes | T171,T175,T160 | INPUT |
lc_otp_program_i.count[289] | No | No | No | INPUT | ||
lc_otp_program_i.count[294:290] | Yes | Yes | *T171,*T175,*T160 | Yes | T171,T175,T160 | INPUT |
lc_otp_program_i.count[295] | No | No | No | INPUT | ||
lc_otp_program_i.count[305:296] | Yes | Yes | *T171,*T62,*T170 | Yes | T171,T62,T170 | INPUT |
lc_otp_program_i.count[306] | No | No | No | INPUT | ||
lc_otp_program_i.count[308:307] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | INPUT |
lc_otp_program_i.count[309] | No | No | No | INPUT | ||
lc_otp_program_i.count[322:310] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | INPUT |
lc_otp_program_i.count[323] | No | No | No | INPUT | ||
lc_otp_program_i.count[338:324] | Yes | Yes | *T62,*T170,*T118 | Yes | T62,T170,T118 | INPUT |
lc_otp_program_i.count[339] | No | No | No | INPUT | ||
lc_otp_program_i.count[348:340] | Yes | Yes | *T62,*T170,*T118 | Yes | T62,T170,T118 | INPUT |
lc_otp_program_i.count[349] | No | No | No | INPUT | ||
lc_otp_program_i.count[351:350] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | INPUT |
lc_otp_program_i.count[352] | No | No | No | INPUT | ||
lc_otp_program_i.count[363:353] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | INPUT |
lc_otp_program_i.count[364] | No | No | No | INPUT | ||
lc_otp_program_i.count[367:365] | Yes | Yes | *T171,*T175,*T160 | Yes | T171,T175,T160 | INPUT |
lc_otp_program_i.count[368] | No | No | No | INPUT | ||
lc_otp_program_i.count[383:369] | Yes | Yes | T171,T175,T160 | Yes | T171,T175,T160 | INPUT |
lc_otp_program_i.state[15:0] | Yes | Yes | *T171,*T62,*T61 | Yes | T171,T62,T170 | INPUT |
lc_otp_program_i.state[16] | No | No | No | INPUT | ||
lc_otp_program_i.state[21:17] | Yes | Yes | *T171,*T175,*T160 | Yes | T171,T175,T160 | INPUT |
lc_otp_program_i.state[22] | No | No | No | INPUT | ||
lc_otp_program_i.state[24:23] | Yes | Yes | *T172,*T51,*T173 | Yes | T51,T173,T171 | INPUT |
lc_otp_program_i.state[25] | No | No | No | INPUT | ||
lc_otp_program_i.state[37:26] | Yes | Yes | *T62,*T61,*T170 | Yes | T62,T170,T118 | INPUT |
lc_otp_program_i.state[38] | No | No | No | INPUT | ||
lc_otp_program_i.state[42:39] | Yes | Yes | T171,*T175,*T160 | Yes | T171,T175,T160 | INPUT |
lc_otp_program_i.state[43] | No | No | No | INPUT | ||
lc_otp_program_i.state[46:44] | Yes | Yes | T62,T61,T170 | Yes | T62,T170,T118 | INPUT |
lc_otp_program_i.state[47] | No | No | No | INPUT | ||
lc_otp_program_i.state[51:48] | Yes | Yes | *T171,*T62,*T61 | Yes | T171,T62,T170 | INPUT |
lc_otp_program_i.state[52] | No | No | No | INPUT | ||
lc_otp_program_i.state[56:53] | Yes | Yes | *T171,T62,T61 | Yes | T171,T62,T170 | INPUT |
lc_otp_program_i.state[57] | No | No | No | INPUT | ||
lc_otp_program_i.state[67:58] | Yes | Yes | *T62,*T61,*T170 | Yes | T62,T170,T118 | INPUT |
lc_otp_program_i.state[68] | No | No | No | INPUT | ||
lc_otp_program_i.state[83:69] | Yes | Yes | *T171,*T62,*T61 | Yes | T171,T62,T170 | INPUT |
lc_otp_program_i.state[84] | No | No | No | INPUT | ||
lc_otp_program_i.state[87:85] | Yes | Yes | T62,T61,*T170 | Yes | T62,T170,T118 | INPUT |
lc_otp_program_i.state[88] | No | No | No | INPUT | ||
lc_otp_program_i.state[91:89] | Yes | Yes | *T171,T62,T61 | Yes | T171,T62,T170 | INPUT |
lc_otp_program_i.state[92] | No | No | No | INPUT | ||
lc_otp_program_i.state[104:93] | Yes | Yes | *T62,*T61,*T170 | Yes | T62,T170,T118 | INPUT |
lc_otp_program_i.state[105] | No | No | No | INPUT | ||
lc_otp_program_i.state[126:106] | Yes | Yes | *T171,*T62,*T61 | Yes | T171,T62,T170 | INPUT |
lc_otp_program_i.state[127] | No | No | No | INPUT | ||
lc_otp_program_i.state[155:128] | Yes | Yes | *T62,*T61,*T170 | Yes | T62,T170,T118 | INPUT |
lc_otp_program_i.state[156] | No | No | No | INPUT | ||
lc_otp_program_i.state[159:157] | Yes | Yes | *T171,T62,T61 | Yes | T171,T62,T170 | INPUT |
lc_otp_program_i.state[160] | No | No | No | INPUT | ||
lc_otp_program_i.state[166:161] | Yes | Yes | *T171,*T175,*T160 | Yes | T171,T175,T160 | INPUT |
lc_otp_program_i.state[167] | No | No | No | INPUT | ||
lc_otp_program_i.state[176:168] | Yes | Yes | *T19,*T172,*T51 | Yes | T19,T51,T173 | INPUT |
lc_otp_program_i.state[178:177] | No | No | No | INPUT | ||
lc_otp_program_i.state[193:179] | Yes | Yes | *T19,*T172,*T51 | Yes | T19,T51,T173 | INPUT |
lc_otp_program_i.state[194] | No | No | No | INPUT | ||
lc_otp_program_i.state[214:195] | Yes | Yes | *T62,*T61,*T170 | Yes | T62,T170,T118 | INPUT |
lc_otp_program_i.state[215] | No | No | No | INPUT | ||
lc_otp_program_i.state[220:216] | Yes | Yes | *T171,*T175,*T160 | Yes | T171,T175,T160 | INPUT |
lc_otp_program_i.state[221] | No | No | No | INPUT | ||
lc_otp_program_i.state[222] | Yes | Yes | *T19,*T172,*T51 | Yes | T19,T51,T173 | INPUT |
lc_otp_program_i.state[223] | No | No | No | INPUT | ||
lc_otp_program_i.state[227:224] | Yes | Yes | *T171,*T175,*T160 | Yes | T171,T175,T160 | INPUT |
lc_otp_program_i.state[228] | No | No | No | INPUT | ||
lc_otp_program_i.state[230:229] | Yes | Yes | *T19,*T172,*T51 | Yes | T19,T51,T173 | INPUT |
lc_otp_program_i.state[231] | No | No | No | INPUT | ||
lc_otp_program_i.state[232] | Yes | Yes | *T171,*T62,*T61 | Yes | T171,T62,T170 | INPUT |
lc_otp_program_i.state[233] | No | No | No | INPUT | ||
lc_otp_program_i.state[254:234] | Yes | Yes | *T19,*T172,*T51 | Yes | T19,T51,T173 | INPUT |
lc_otp_program_i.state[255] | No | No | No | INPUT | ||
lc_otp_program_i.state[265:256] | Yes | Yes | *T4,*T19,*T52 | Yes | T19,T21,T51 | INPUT |
lc_otp_program_i.state[268:266] | No | No | No | INPUT | ||
lc_otp_program_i.state[277:269] | Yes | Yes | *T4,*T19,*T52 | Yes | T19,T21,T51 | INPUT |
lc_otp_program_i.state[278] | No | No | No | INPUT | ||
lc_otp_program_i.state[285:279] | Yes | Yes | *T5,*T6,*T17 | Yes | T41,T42,T59 | INPUT |
lc_otp_program_i.state[288:286] | No | No | No | INPUT | ||
lc_otp_program_i.state[294:289] | Yes | Yes | *T4,*T6,*T19 | Yes | T19,T21,T51 | INPUT |
lc_otp_program_i.state[295] | No | No | No | INPUT | ||
lc_otp_program_i.state[303:296] | Yes | Yes | *T4,*T6,*T19 | Yes | T19,T21,T51 | INPUT |
lc_otp_program_i.state[304] | No | No | No | INPUT | ||
lc_otp_program_i.state[312:305] | Yes | Yes | *T171,*T175,*T160 | Yes | T171,T175,T160 | INPUT |
lc_otp_program_i.state[313] | No | No | No | INPUT | ||
lc_otp_program_i.state[319:314] | Yes | Yes | T4,T6,T19 | Yes | T19,T21,T51 | INPUT |
lc_otp_program_i.req | Yes | Yes | T19,T62,T61 | Yes | T19,T62,T61 | INPUT |
lc_otp_program_o.ack | Yes | Yes | T19,T62,T61 | Yes | T19,T62,T61 | OUTPUT |
lc_otp_program_o.err | Yes | Yes | T61,T176,T177 | Yes | T61,T176,T177 | OUTPUT |
lc_creator_seed_sw_rw_en_i[3:0] | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T6 | INPUT |
lc_owner_seed_sw_rw_en_i[3:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
lc_seed_hw_rd_en_i[3:0] | Yes | Yes | T41,T42,T59 | Yes | T5,T17,T60 | INPUT |
lc_dft_en_i[3:0] | Yes | Yes | T41,T42,T59 | Yes | T5,T17,T60 | INPUT |
lc_escalate_en_i[3:0] | Yes | Yes | T42,T63,T64 | Yes | T42,T63,T64 | INPUT |
lc_check_byp_en_i[3:0] | Yes | Yes | T19,T61,T53 | Yes | T19,T62,T61 | INPUT |
otp_lc_data_o.rma_token[127:0] | Yes | Yes | T4,T60,T18 | Yes | T42,T64,T178 | OUTPUT |
otp_lc_data_o.rma_token_valid[3:0] | Yes | Yes | T20,T179,T180 | Yes | T20,T155,T113 | OUTPUT |
otp_lc_data_o.test_exit_token[127:0] | Yes | Yes | T41,T42,T19 | Yes | T4,T6,T17 | OUTPUT |
otp_lc_data_o.test_unlock_token[127:0] | Yes | Yes | T42,T178,T155 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.test_tokens_valid[3:0] | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.secrets_valid[3:0] | Yes | Yes | T20,T179,T180 | Yes | T20,T155,T113 | OUTPUT |
otp_lc_data_o.count[0] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[11:1] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT |
otp_lc_data_o.count[12] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[13] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT |
otp_lc_data_o.count[14] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[20:15] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.count[21] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[22] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.count[23] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[25:24] | Yes | Yes | *T172,*T51,*T173 | Yes | T51,T173,T174 | OUTPUT |
otp_lc_data_o.count[26] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[51:27] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.count[52] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[60:53] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT |
otp_lc_data_o.count[61] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[65:62] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.count[66] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[70:67] | Yes | Yes | *T172,*T51,*T173 | Yes | T51,T173,T174 | OUTPUT |
otp_lc_data_o.count[71] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[77:72] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.count[78] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[91:79] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT |
otp_lc_data_o.count[92] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[106:93] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT |
otp_lc_data_o.count[109:107] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[110] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.count[111] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[113:112] | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.count[114] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[116:115] | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.count[117] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[118] | Yes | Yes | *T4,*T6,*T54 | Yes | T21,T51,T173 | OUTPUT |
otp_lc_data_o.count[119] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[127:120] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT |
otp_lc_data_o.count[128] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[144:129] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT |
otp_lc_data_o.count[145] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[146] | Yes | Yes | *T53,*T183,*T184 | Yes | T19,T61,T53 | OUTPUT |
otp_lc_data_o.count[147] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[151:148] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT |
otp_lc_data_o.count[152] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[154:153] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT |
otp_lc_data_o.count[155] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[160:156] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT |
otp_lc_data_o.count[161] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[165:162] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT |
otp_lc_data_o.count[166] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[169:167] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT |
otp_lc_data_o.count[171:170] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[177:172] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.count[178] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[180:179] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT |
otp_lc_data_o.count[181] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[189:182] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT |
otp_lc_data_o.count[190] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[193:191] | Yes | Yes | *T184,T185,*T186 | Yes | T61,T53,T183 | OUTPUT |
otp_lc_data_o.count[194] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[196:195] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT |
otp_lc_data_o.count[197] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[212:198] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT |
otp_lc_data_o.count[214:213] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[223:215] | Yes | Yes | *T184,*T185,*T186 | Yes | T61,T184,T185 | OUTPUT |
otp_lc_data_o.count[224] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[229:225] | Yes | Yes | *T184,*T186,*T187 | Yes | T61,T184,T185 | OUTPUT |
otp_lc_data_o.count[231:230] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[239:232] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT |
otp_lc_data_o.count[240] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[242:241] | Yes | Yes | T4,T5,T6 | Yes | T41,T42,T59 | OUTPUT |
otp_lc_data_o.count[243] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[245:244] | Yes | Yes | T62,T170,T118 | Yes | T118,T181,T182 | OUTPUT |
otp_lc_data_o.count[247:246] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[256:248] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.count[257] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[261:258] | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.count[262] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[284:263] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT |
otp_lc_data_o.count[285] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[288:286] | Yes | Yes | T4,T5,T6 | Yes | T41,T42,T59 | OUTPUT |
otp_lc_data_o.count[289] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[294:290] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT |
otp_lc_data_o.count[295] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[305:296] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.count[306] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[308:307] | Yes | Yes | *T184,*T186,*T187 | Yes | T61,T184,T186 | OUTPUT |
otp_lc_data_o.count[309] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[322:310] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT |
otp_lc_data_o.count[323] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[338:324] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT |
otp_lc_data_o.count[339] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[348:340] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT |
otp_lc_data_o.count[349] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[351:350] | Yes | Yes | *T184,*T186,*T187 | Yes | T61,T184,T186 | OUTPUT |
otp_lc_data_o.count[352] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[363:353] | Yes | Yes | *T184,*T186,*T187 | Yes | T61,T184,T186 | OUTPUT |
otp_lc_data_o.count[364] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[367:365] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT |
otp_lc_data_o.count[368] | No | No | No | OUTPUT | ||
otp_lc_data_o.count[383:369] | Yes | Yes | T4,T5,T6 | Yes | T41,T42,T59 | OUTPUT |
otp_lc_data_o.state[15:0] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.state[16] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[21:17] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT |
otp_lc_data_o.state[22] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[24:23] | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.state[25] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[37:26] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT |
otp_lc_data_o.state[38] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[42:39] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT |
otp_lc_data_o.state[43] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[46:44] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT |
otp_lc_data_o.state[47] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[51:48] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.state[52] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[56:53] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.state[57] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[67:58] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT |
otp_lc_data_o.state[68] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[83:69] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.state[84] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[87:85] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT |
otp_lc_data_o.state[88] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[91:89] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.state[92] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[104:93] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT |
otp_lc_data_o.state[105] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[126:106] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.state[127] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[155:128] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT |
otp_lc_data_o.state[156] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[159:157] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.state[160] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[166:161] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT |
otp_lc_data_o.state[167] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[176:168] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.state[178:177] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[193:179] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.state[194] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[214:195] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT |
otp_lc_data_o.state[215] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[220:216] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT |
otp_lc_data_o.state[221] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[222] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.state[223] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[227:224] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT |
otp_lc_data_o.state[228] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[230:229] | Yes | Yes | *T19,*T172,*T51 | Yes | T19,T51,T173 | OUTPUT |
otp_lc_data_o.state[231] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[232] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT |
otp_lc_data_o.state[233] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[254:234] | Yes | Yes | *T19,*T172,*T51 | Yes | T19,T51,T173 | OUTPUT |
otp_lc_data_o.state[255] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[265:256] | Yes | Yes | *T4,*T19,*T52 | Yes | T19,T21,T51 | OUTPUT |
otp_lc_data_o.state[268:266] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[277:269] | Yes | Yes | *T41,*T42,*T59 | Yes | T5,T6,T17 | OUTPUT |
otp_lc_data_o.state[278] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[285:279] | Yes | Yes | *T5,*T6,*T17 | Yes | T41,T42,T59 | OUTPUT |
otp_lc_data_o.state[288:286] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[294:289] | Yes | Yes | *T41,*T42,*T59 | Yes | T5,T17,T60 | OUTPUT |
otp_lc_data_o.state[295] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[303:296] | Yes | Yes | *T4,*T6,*T19 | Yes | T19,T21,T51 | OUTPUT |
otp_lc_data_o.state[304] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[312:305] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT |
otp_lc_data_o.state[313] | No | No | No | OUTPUT | ||
otp_lc_data_o.state[319:314] | Yes | Yes | T4,T6,T19 | Yes | T19,T21,T51 | OUTPUT |
otp_lc_data_o.error | Yes | Yes | T42,T63,T64 | Yes | T42,T63,T64 | OUTPUT |
otp_lc_data_o.valid | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T6 | OUTPUT |
otp_keymgr_key_o.owner_seed_valid | No | No | No | OUTPUT | ||
otp_keymgr_key_o.owner_seed[255:0] | No | No | No | OUTPUT | ||
otp_keymgr_key_o.creator_seed_valid | No | No | No | OUTPUT | ||
otp_keymgr_key_o.creator_seed[255:0] | No | No | No | OUTPUT | ||
otp_keymgr_key_o.creator_root_key_share1_valid | Yes | Yes | T20,T179,T180 | Yes | T20,T155,T113 | OUTPUT |
otp_keymgr_key_o.creator_root_key_share1[255:0] | Yes | Yes | T41,T59,T188 | Yes | T5,T60,T18 | OUTPUT |
otp_keymgr_key_o.creator_root_key_share0_valid | Yes | Yes | T20,T179,T180 | Yes | T20,T155,T113 | OUTPUT |
otp_keymgr_key_o.creator_root_key_share0[255:0] | Yes | Yes | T41,T42,T20 | Yes | T17,T18,T41 | OUTPUT |
flash_otp_key_i.addr_req | Yes | Yes | T4,T5,T17 | Yes | T4,T5,T17 | INPUT |
flash_otp_key_i.data_req | Yes | Yes | T4,T5,T17 | Yes | T4,T5,T17 | INPUT |
flash_otp_key_o.seed_valid | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T17 | OUTPUT |
flash_otp_key_o.rand_key[127:0] | Yes | Yes | T4,T60,T18 | Yes | T4,T5,T17 | OUTPUT |
flash_otp_key_o.key[127:0] | Yes | Yes | T4,T5,T17 | Yes | T4,T41,T59 | OUTPUT |
flash_otp_key_o.addr_ack | Yes | Yes | T4,T5,T17 | Yes | T4,T5,T17 | OUTPUT |
flash_otp_key_o.data_ack | Yes | Yes | T4,T5,T17 | Yes | T4,T5,T17 | OUTPUT |
sram_otp_key_i[0].req | Yes | Yes | T4,T20,T52 | Yes | T4,T20,T52 | INPUT |
sram_otp_key_i[1].req | Yes | Yes | T116,T117,T189 | Yes | T116,T117,T189 | INPUT |
sram_otp_key_i[2].req | Yes | Yes | T190,T191,T192 | Yes | T190,T191,T192 | INPUT |
sram_otp_key_i[3].req | No | No | No | INPUT | ||
sram_otp_key_o[0].seed_valid | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T17 | OUTPUT |
sram_otp_key_o[0].nonce[127:0] | Yes | Yes | T4,T60,T18 | Yes | T4,T5,T17 | OUTPUT |
sram_otp_key_o[0].key[127:0] | Yes | Yes | T4,T5,T17 | Yes | T4,T41,T59 | OUTPUT |
sram_otp_key_o[0].ack | Yes | Yes | T4,T20,T52 | Yes | T4,T20,T52 | OUTPUT |
sram_otp_key_o[1].seed_valid | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T17 | OUTPUT |
sram_otp_key_o[1].nonce[127:0] | Yes | Yes | T4,T60,T18 | Yes | T4,T5,T17 | OUTPUT |
sram_otp_key_o[1].key[127:0] | Yes | Yes | T4,T5,T17 | Yes | T4,T41,T59 | OUTPUT |
sram_otp_key_o[1].ack | Yes | Yes | T116,T117,T189 | Yes | T116,T117,T189 | OUTPUT |
sram_otp_key_o[2].seed_valid | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T17 | OUTPUT |
sram_otp_key_o[2].nonce[127:0] | Yes | Yes | T4,T60,T18 | Yes | T4,T5,T17 | OUTPUT |
sram_otp_key_o[2].key[127:0] | Yes | Yes | T4,T5,T17 | Yes | T4,T41,T59 | OUTPUT |
sram_otp_key_o[2].ack | Yes | Yes | T190,T193,T194 | Yes | T190,T193,T194 | OUTPUT |
sram_otp_key_o[3].seed_valid | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T17 | OUTPUT |
sram_otp_key_o[3].nonce[127:0] | Yes | Yes | T4,T60,T18 | Yes | T4,T5,T17 | OUTPUT |
sram_otp_key_o[3].key[127:0] | Yes | Yes | T4,T5,T17 | Yes | T4,T41,T59 | OUTPUT |
sram_otp_key_o[3].ack | No | No | No | OUTPUT | ||
otbn_otp_key_i.req | Yes | Yes | T4,T20,T52 | Yes | T4,T20,T52 | INPUT |
otbn_otp_key_o.seed_valid | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T17 | OUTPUT |
otbn_otp_key_o.nonce[63:0] | Yes | Yes | T4,T60,T18 | Yes | T4,T5,T17 | OUTPUT |
otbn_otp_key_o.key[127:0] | Yes | Yes | T4,T5,T17 | Yes | T4,T41,T59 | OUTPUT |
otbn_otp_key_o.ack | Yes | Yes | T4,T20,T52 | Yes | T4,T20,T52 | OUTPUT |
otp_broadcast_o.hw_cfg0_data.device_id[255:0] | Yes | Yes | T4,T5,T6 | Yes | T42,T21,T178 | OUTPUT |
otp_broadcast_o.hw_cfg0_data.manuf_state[17:0] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT |
otp_broadcast_o.hw_cfg0_data.manuf_state[18] | No | No | No | OUTPUT | ||
otp_broadcast_o.hw_cfg0_data.manuf_state[35:19] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT |
otp_broadcast_o.hw_cfg0_data.manuf_state[36] | No | No | No | OUTPUT | ||
otp_broadcast_o.hw_cfg0_data.manuf_state[91:37] | Yes | Yes | *T195,*T196,*T4 | Yes | T195,T196,T41 | OUTPUT |
otp_broadcast_o.hw_cfg0_data.manuf_state[92] | No | No | No | OUTPUT | ||
otp_broadcast_o.hw_cfg0_data.manuf_state[98:93] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT |
otp_broadcast_o.hw_cfg0_data.manuf_state[99] | No | No | No | OUTPUT | ||
otp_broadcast_o.hw_cfg0_data.manuf_state[107:100] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT |
otp_broadcast_o.hw_cfg0_data.manuf_state[108] | No | No | No | OUTPUT | ||
otp_broadcast_o.hw_cfg0_data.manuf_state[160:109] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT |
otp_broadcast_o.hw_cfg0_data.manuf_state[161] | No | No | No | OUTPUT | ||
otp_broadcast_o.hw_cfg0_data.manuf_state[197:162] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT |
otp_broadcast_o.hw_cfg0_data.manuf_state[198] | No | No | No | OUTPUT | ||
otp_broadcast_o.hw_cfg0_data.manuf_state[207:199] | Yes | Yes | *T196,*T195,*T197 | Yes | T196,T195,T197 | OUTPUT |
otp_broadcast_o.hw_cfg0_data.manuf_state[208] | No | No | No | OUTPUT | ||
otp_broadcast_o.hw_cfg0_data.manuf_state[249:209] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT |
otp_broadcast_o.hw_cfg0_data.manuf_state[250] | No | No | No | OUTPUT | ||
otp_broadcast_o.hw_cfg0_data.manuf_state[251] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT |
otp_broadcast_o.hw_cfg0_data.manuf_state[252] | No | No | No | OUTPUT | ||
otp_broadcast_o.hw_cfg0_data.manuf_state[255:253] | Yes | Yes | T196,T4,T5 | Yes | T196,T41,T42 | OUTPUT |
otp_broadcast_o.hw_cfg0_data.hw_cfg0_digest[63:0] | Yes | Yes | T41,T63,T64 | Yes | T6,T17,T60 | OUTPUT |
otp_broadcast_o.hw_cfg1_data.en_sram_ifetch[7:0] | Yes | Yes | T4,T5,T6 | Yes | T41,T42,T59 | OUTPUT |
otp_broadcast_o.hw_cfg1_data.en_csrng_sw_app_read[7:0] | Yes | Yes | T4,T5,T6 | Yes | T41,T42,T59 | OUTPUT |
otp_broadcast_o.hw_cfg1_data.dis_rv_dm_late_debug[7:0] | Yes | Yes | T4,T5,T6 | Yes | T41,T42,T59 | OUTPUT |
otp_broadcast_o.hw_cfg1_data.unallocated[39:0] | No | No | No | OUTPUT | ||
otp_broadcast_o.hw_cfg1_data.hw_cfg1_digest[39:0] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T191 | OUTPUT |
otp_broadcast_o.hw_cfg1_data.hw_cfg1_digest[40] | No | No | No | OUTPUT | ||
otp_broadcast_o.hw_cfg1_data.hw_cfg1_digest[63:41] | Yes | Yes | T5,T6,T17 | Yes | T41,T42,T59 | OUTPUT |
otp_broadcast_o.valid[3:0] | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T6 | OUTPUT |
otp_ext_voltage_h_io | No | No | Yes | T22,T23,T24 | INOUT | |
scan_en_i | Unreachable | Unreachable | Unreachable | INPUT | ||
scan_rst_ni | Unreachable | Unreachable | Unreachable | INPUT | ||
scanmode_i[3:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
cio_test_o[7:0] | No | No | No | OUTPUT | ||
cio_test_en_o[7:0] | Yes | Yes | T41,T42,T59 | Yes | T5,T17,T60 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 160 | 141 | 88.12 |
Total Bits | 10986 | 9361 | 85.21 |
Total Bits 0->1 | 5493 | 4695 | 85.47 |
Total Bits 1->0 | 5493 | 4666 | 84.94 |
Ports | 160 | 141 | 88.12 |
Port Bits | 10986 | 9361 | 85.21 |
Port Bits 0->1 | 5493 | 4695 | 85.47 |
Port Bits 1->0 | 5493 | 4666 | 84.94 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction | Exclude Annotation |
clk_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT | |
rst_ni | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T6 | INPUT | |
clk_edn_i | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT | |
rst_edn_ni | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T6 | INPUT | |
edn_o.edn_req | Yes | Yes | T4,T5,T17 | Yes | T4,T5,T17 | OUTPUT | |
edn_i.edn_bus[31:0] | Yes | Yes | T4,T5,T17 | Yes | T4,T5,T17 | INPUT | |
edn_i.edn_fips | No | No | Yes | T112,T114,T151 | INPUT | ||
edn_i.edn_ack | Yes | Yes | T4,T5,T17 | Yes | T4,T5,T17 | INPUT | |
core_tl_i.d_ready | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT | |
core_tl_i.a_user.data_intg[6:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT | |
core_tl_i.a_user.cmd_intg[6:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT | |
core_tl_i.a_user.instr_type[3:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT | |
core_tl_i.a_user.rsvd[4:0] | Unreachable | Unreachable | Unreachable | INPUT | |||
core_tl_i.a_data[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT | |
core_tl_i.a_mask[3:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT | |
core_tl_i.a_address[11:0] | Yes | Yes | *T76,*T77,*T78 | Yes | T76,T77,T78 | INPUT | |
core_tl_i.a_address[15:12] | Unreachable | Unreachable | Unreachable | INPUT | |||
core_tl_i.a_address[17:16] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT | |
core_tl_i.a_address[19:18] | Unreachable | Unreachable | Unreachable | INPUT | |||
core_tl_i.a_address[20] | Yes | Yes | *T4,*T5,*T6 | Yes | T4,T5,T6 | INPUT | |
core_tl_i.a_address[29:21] | Unreachable | Unreachable | Unreachable | INPUT | |||
core_tl_i.a_address[30] | Yes | Yes | *T4,*T5,*T6 | Yes | T4,T5,T6 | INPUT | |
core_tl_i.a_address[31] | Unreachable | Unreachable | Unreachable | INPUT | |||
core_tl_i.a_source[5:0] | Yes | Yes | *T1,*T79,*T80 | Yes | T1,T79,T80 | INPUT | |
core_tl_i.a_source[7:6] | Unreachable | Unreachable | Unreachable | INPUT | |||
core_tl_i.a_size[1:0] | Yes | Yes | T76,T77,T78 | Yes | T76,T77,T78 | INPUT | |
core_tl_i.a_param[2:0] | Unreachable | Unreachable | Unreachable | INPUT | |||
core_tl_i.a_opcode[2:0] | Yes | Yes | T1,T79,T81 | Yes | T1,T79,T81 | INPUT | |
core_tl_i.a_valid | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT | |
core_tl_o.a_ready | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT | |
core_tl_o.d_error | Yes | Yes | T76,T78,T152 | Yes | T76,T78,T152 | OUTPUT | |
core_tl_o.d_user.data_intg[6:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT | |
core_tl_o.d_user.rsp_intg[6:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT | |
core_tl_o.d_data[31:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT | |
core_tl_o.d_sink | Yes | Yes | T76,T77,T78 | Yes | T76,T77,T78 | OUTPUT | |
core_tl_o.d_source[5:0] | Yes | Yes | *T80,*T153,*T154 | Yes | T80,T153,T154 | OUTPUT | |
core_tl_o.d_source[7:6] | Unreachable | Unreachable | Unreachable | OUTPUT | |||
core_tl_o.d_size[1:0] | Yes | Yes | T76,T77,T78 | Yes | T76,T77,T78 | OUTPUT | |
core_tl_o.d_param[2:0] | Unreachable | Unreachable | Unreachable | OUTPUT | |||
core_tl_o.d_opcode[0] | Yes | Yes | *T155,*T113,*T156 | Yes | T155,T113,T156 | OUTPUT | |
core_tl_o.d_opcode[2:1] | Unreachable | Unreachable | Unreachable | OUTPUT | |||
core_tl_o.d_valid | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT | |
prim_tl_i.d_ready | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT | |
prim_tl_i.a_user.data_intg[6:0] | Yes | Yes | T76,T77,T78 | Yes | T76,T77,T78 | INPUT | |
prim_tl_i.a_user.cmd_intg[6:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT | |
prim_tl_i.a_user.instr_type[3:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT | |
prim_tl_i.a_user.rsvd[4:0] | Unreachable | Unreachable | Unreachable | INPUT | |||
prim_tl_i.a_data[31:0] | Yes | Yes | T76,T77,T78 | Yes | T76,T77,T78 | INPUT | |
prim_tl_i.a_mask[3:0] | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT | |
prim_tl_i.a_address[4:0] | Yes | Yes | *T76,*T77,*T78 | Yes | T76,T77,T78 | INPUT | |
prim_tl_i.a_address[14:5] | Unreachable | Unreachable | Unreachable | INPUT | |||
prim_tl_i.a_address[17:15] | Yes | Yes | *T76,*T77,*T78 | Yes | T76,T77,T78 | INPUT | |
prim_tl_i.a_address[19:18] | Unreachable | Unreachable | Unreachable | INPUT | |||
prim_tl_i.a_address[20] | Yes | Yes | *T4,*T5,*T6 | Yes | T4,T5,T6 | INPUT | |
prim_tl_i.a_address[29:21] | Unreachable | Unreachable | Unreachable | INPUT | |||
prim_tl_i.a_address[30] | Yes | Yes | *T4,*T5,*T6 | Yes | T4,T5,T6 | INPUT | |
prim_tl_i.a_address[31] | Unreachable | Unreachable | Unreachable | INPUT | |||
prim_tl_i.a_source[5:0] | Yes | Yes | *T1,*T79,*T80 | Yes | T1,T79,T80 | INPUT | |
prim_tl_i.a_source[7:6] | Unreachable | Unreachable | Unreachable | INPUT | |||
prim_tl_i.a_size[1:0] | Yes | Yes | T76,T77,T78 | Yes | T76,T77,T78 | INPUT | |
prim_tl_i.a_param[2:0] | Unreachable | Unreachable | Unreachable | INPUT | |||
prim_tl_i.a_opcode[2:0] | Yes | Yes | T1,T79,T81 | Yes | T1,T79,T81 | INPUT | |
prim_tl_i.a_valid | Yes | Yes | T76,T77,T78 | Yes | T76,T77,T78 | INPUT | |
prim_tl_o.a_ready | Yes | Yes | T5,T17,T60 | Yes | T5,T17,T60 | OUTPUT | |
prim_tl_o.d_error | Yes | Yes | T5,T17,T60 | Yes | T41,T42,T59 | OUTPUT | |
prim_tl_o.d_user.data_intg[6:0] | Yes | Yes | T76,T77,T78 | Yes | T76,T77,T78 | OUTPUT | |
prim_tl_o.d_user.rsp_intg[6:0] | Yes | Yes | T76,T77,T78 | Yes | T76,T77,T78 | OUTPUT | |
prim_tl_o.d_data[31:0] | Yes | Yes | T5,T17,T60 | Yes | T41,T42,T59 | OUTPUT | |
prim_tl_o.d_sink | Yes | Yes | T76,T77,T78 | Yes | T76,T77,T78 | OUTPUT | |
prim_tl_o.d_source[5:0] | Yes | Yes | T76,T77,T126 | Yes | T76,T77,T78 | OUTPUT | |
prim_tl_o.d_source[7:6] | Unreachable | Unreachable | Unreachable | OUTPUT | |||
prim_tl_o.d_size[1:0] | Yes | Yes | T76,T77,T78 | Yes | T76,T77,T78 | OUTPUT | |
prim_tl_o.d_param[2:0] | Unreachable | Unreachable | Unreachable | OUTPUT | |||
prim_tl_o.d_opcode[0] | Yes | Yes | *T5,*T17,*T60 | Yes | T41,T42,T59 | OUTPUT | |
prim_tl_o.d_opcode[2:1] | Unreachable | Unreachable | Unreachable | OUTPUT | |||
prim_tl_o.d_valid | Yes | Yes | T76,T77,T78 | Yes | T76,T77,T78 | OUTPUT | |
intr_otp_operation_done_o | Yes | Yes | T157,T158,T159 | Yes | T157,T158,T159 | OUTPUT | |
intr_otp_error_o | Yes | Yes | T157,T158,T159 | Yes | T157,T158,T159 | OUTPUT | |
alert_rx_i[0].ack_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT | |
alert_rx_i[0].ack_p | Yes | Yes | T55,T82,T160 | Yes | T55,T82,T160 | INPUT | |
alert_rx_i[0].ping_n | Yes | Yes | T82,T83,T84 | Yes | T82,T83,T84 | INPUT | |
alert_rx_i[0].ping_p | Yes | Yes | T82,T83,T84 | Yes | T82,T83,T84 | INPUT | |
alert_rx_i[1].ack_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT | |
alert_rx_i[1].ack_p | Yes | Yes | T42,T63,T64 | Yes | T42,T63,T64 | INPUT | |
alert_rx_i[1].ping_n | Yes | Yes | T161,T82,T83 | Yes | T82,T83,T84 | INPUT | |
alert_rx_i[1].ping_p | Yes | Yes | T82,T83,T84 | Yes | T161,T82,T83 | INPUT | |
alert_rx_i[2].ack_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT | |
alert_rx_i[2].ack_p | Yes | Yes | T162,T55,T82 | Yes | T162,T55,T82 | INPUT | |
alert_rx_i[2].ping_n | Yes | Yes | T82,T83,T84 | Yes | T82,T83,T84 | INPUT | |
alert_rx_i[2].ping_p | Yes | Yes | T82,T83,T84 | Yes | T82,T83,T84 | INPUT | |
alert_rx_i[3].ack_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT | |
alert_rx_i[3].ack_p | Yes | Yes | T163,T164,T165 | Yes | T163,T164,T165 | INPUT | |
alert_rx_i[3].ping_n | Yes | Yes | T82,T83,T84 | Yes | T82,T83,T84 | INPUT | |
alert_rx_i[3].ping_p | Yes | Yes | T82,T83,T84 | Yes | T82,T83,T84 | INPUT | |
alert_rx_i[4].ack_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT | |
alert_rx_i[4].ack_p | Yes | Yes | T55,T166,T82 | Yes | T55,T166,T82 | INPUT | |
alert_rx_i[4].ping_n | Yes | Yes | T166,T82,T83 | Yes | T166,T82,T83 | INPUT | |
alert_rx_i[4].ping_p | Yes | Yes | T166,T82,T83 | Yes | T166,T82,T83 | INPUT | |
alert_tx_o[0].alert_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT | |
alert_tx_o[0].alert_p | Yes | Yes | T55,T82,T160 | Yes | T55,T82,T160 | OUTPUT | |
alert_tx_o[1].alert_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT | |
alert_tx_o[1].alert_p | Yes | Yes | T42,T63,T64 | Yes | T42,T63,T64 | OUTPUT | |
alert_tx_o[2].alert_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT | |
alert_tx_o[2].alert_p | Yes | Yes | T162,T55,T82 | Yes | T162,T55,T82 | OUTPUT | |
alert_tx_o[3].alert_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT | |
alert_tx_o[3].alert_p | Yes | Yes | T163,T164,T165 | Yes | T163,T164,T165 | OUTPUT | |
alert_tx_o[4].alert_n | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | OUTPUT | |
alert_tx_o[4].alert_p | Yes | Yes | T55,T166,T82 | Yes | T55,T166,T82 | OUTPUT | |
obs_ctrl_i.obmen[3:0] | Excluded | Excluded | Excluded | INPUT | [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and OTP. Must be covered in vendor closed source DV. | ||
obs_ctrl_i.obmsl[3:0] | Excluded | Excluded | Excluded | INPUT | [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and OTP. Must be covered in vendor closed source DV. | ||
obs_ctrl_i.obgsl[3:0] | Excluded | Excluded | Excluded | INPUT | [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and OTP. Must be covered in vendor closed source DV. | ||
otp_obs_o[7:0] | Unreachable | Unreachable | Unreachable | OUTPUT | |||
otp_ast_pwr_seq_o.pwr_seq[1:0] | No | No | No | OUTPUT | |||
otp_ast_pwr_seq_h_i.pwr_seq_h[0] | No | No | No | INPUT | |||
otp_ast_pwr_seq_h_i.pwr_seq_h[1] | Yes | Yes | T4,T5,T6 | Yes | T41,T59,T68 | INPUT | |
pwr_otp_i.otp_init | Yes | Yes | T4,T5,T6 | Yes | T4,T5,T6 | INPUT | |
pwr_otp_o.otp_idle | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T6 | OUTPUT | |
pwr_otp_o.otp_done | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T6 | OUTPUT | |
lc_otp_vendor_test_i.ctrl[12:0] | No | No | Yes | T167,T168,T169 | INPUT | ||
lc_otp_vendor_test_i.ctrl[13] | No | No | No | INPUT | |||
lc_otp_vendor_test_i.ctrl[21:14] | No | No | Yes | T169,T168,T167 | INPUT | ||
lc_otp_vendor_test_i.ctrl[22] | No | No | No | INPUT | |||
lc_otp_vendor_test_i.ctrl[24:23] | No | No | Yes | T167,T169,T168 | INPUT | ||
lc_otp_vendor_test_i.ctrl[25] | No | No | No | INPUT | |||
lc_otp_vendor_test_i.ctrl[26] | No | No | Yes | T169 | INPUT | ||
lc_otp_vendor_test_i.ctrl[27] | No | No | No | INPUT | |||
lc_otp_vendor_test_i.ctrl[31:28] | No | No | Yes | T169,T168,T167 | INPUT | ||
lc_otp_vendor_test_o.status[31:0] | No | No | No | OUTPUT | |||
lc_otp_program_i.count[0] | No | No | No | INPUT | |||
lc_otp_program_i.count[11:1] | Yes | Yes | *T62,*T170,*T118 | Yes | T62,T170,T118 | INPUT | |
lc_otp_program_i.count[12] | No | No | No | INPUT | |||
lc_otp_program_i.count[13] | Yes | Yes | *T62,*T170,*T118 | Yes | T62,T170,T118 | INPUT | |
lc_otp_program_i.count[14] | No | No | No | INPUT | |||
lc_otp_program_i.count[20:15] | Yes | Yes | *T171,*T62,*T170 | Yes | T171,T62,T170 | INPUT | |
lc_otp_program_i.count[21] | No | No | No | INPUT | |||
lc_otp_program_i.count[22] | Yes | Yes | *T172,*T51,*T173 | Yes | T51,T173,T171 | INPUT | |
lc_otp_program_i.count[23] | No | No | No | INPUT | |||
lc_otp_program_i.count[25:24] | Yes | Yes | *T172,*T51,*T173 | Yes | T51,T173,T174 | INPUT | |
lc_otp_program_i.count[26] | No | No | No | INPUT | |||
lc_otp_program_i.count[51:27] | Yes | Yes | *T172,*T51,*T173 | Yes | T51,T173,T171 | INPUT | |
lc_otp_program_i.count[52] | No | No | No | INPUT | |||
lc_otp_program_i.count[60:53] | Yes | Yes | *T171,*T175,*T160 | Yes | T171,T175,T160 | INPUT | |
lc_otp_program_i.count[61] | No | No | No | INPUT | |||
lc_otp_program_i.count[65:62] | Yes | Yes | *T172,*T51,*T173 | Yes | T51,T173,T171 | INPUT | |
lc_otp_program_i.count[66] | No | No | No | INPUT | |||
lc_otp_program_i.count[70:67] | Yes | Yes | *T172,*T51,*T173 | Yes | T51,T173,T174 | INPUT | |
lc_otp_program_i.count[71] | No | No | No | INPUT | |||
lc_otp_program_i.count[77:72] | Yes | Yes | *T172,*T51,*T173 | Yes | T51,T173,T171 | INPUT | |
lc_otp_program_i.count[78] | No | No | No | INPUT | |||
lc_otp_program_i.count[91:79] | Yes | Yes | *T62,*T170,*T118 | Yes | T62,T170,T118 | INPUT | |
lc_otp_program_i.count[92] | No | No | No | INPUT | |||
lc_otp_program_i.count[106:93] | Yes | Yes | *T171,*T175,*T160 | Yes | T171,T175,T160 | INPUT | |
lc_otp_program_i.count[109:107] | No | No | No | INPUT | |||
lc_otp_program_i.count[110] | Yes | Yes | *T171,*T62,*T170 | Yes | T171,T62,T170 | INPUT | |
lc_otp_program_i.count[111] | No | No | No | INPUT | |||
lc_otp_program_i.count[113:112] | Yes | Yes | T171,*T62,*T170 | Yes | T171,T62,T170 | INPUT | |
lc_otp_program_i.count[114] | No | No | No | INPUT | |||
lc_otp_program_i.count[116:115] | Yes | Yes | T171,*T62,*T170 | Yes | T171,T62,T170 | INPUT | |
lc_otp_program_i.count[117] | No | No | No | INPUT | |||
lc_otp_program_i.count[118] | Yes | Yes | *T4,*T6,*T54 | Yes | T21,T51,T173 | INPUT | |
lc_otp_program_i.count[119] | No | No | No | INPUT | |||
lc_otp_program_i.count[127:120] | Yes | Yes | *T62,*T170,*T118 | Yes | T62,T170,T118 | INPUT | |
lc_otp_program_i.count[128] | No | No | No | INPUT | |||
lc_otp_program_i.count[144:129] | Yes | Yes | *T171,*T175,*T160 | Yes | T171,T175,T160 | INPUT | |
lc_otp_program_i.count[145] | No | No | No | INPUT | |||
lc_otp_program_i.count[146] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | INPUT | |
lc_otp_program_i.count[147] | No | No | No | INPUT | |||
lc_otp_program_i.count[151:148] | Yes | Yes | *T62,*T170,*T118 | Yes | T62,T170,T118 | INPUT | |
lc_otp_program_i.count[152] | No | No | No | INPUT | |||
lc_otp_program_i.count[154:153] | Yes | Yes | *T171,*T175,*T160 | Yes | T171,T175,T160 | INPUT | |
lc_otp_program_i.count[155] | No | No | No | INPUT | |||
lc_otp_program_i.count[160:156] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | INPUT | |
lc_otp_program_i.count[161] | No | No | No | INPUT | |||
lc_otp_program_i.count[165:162] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | INPUT | |
lc_otp_program_i.count[166] | No | No | No | INPUT | |||
lc_otp_program_i.count[169:167] | Yes | Yes | *T62,*T170,*T118 | Yes | T62,T170,T118 | INPUT | |
lc_otp_program_i.count[171:170] | No | No | No | INPUT | |||
lc_otp_program_i.count[177:172] | Yes | Yes | *T171,*T62,*T170 | Yes | T171,T62,T170 | INPUT | |
lc_otp_program_i.count[178] | No | No | No | INPUT | |||
lc_otp_program_i.count[180:179] | Yes | Yes | T171,T175,*T160 | Yes | T171,T175,T160 | INPUT | |
lc_otp_program_i.count[181] | No | No | No | INPUT | |||
lc_otp_program_i.count[189:182] | Yes | Yes | *T171,*T175,*T160 | Yes | T171,T175,T160 | INPUT | |
lc_otp_program_i.count[190] | No | No | No | INPUT | |||
lc_otp_program_i.count[193:191] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | INPUT | |
lc_otp_program_i.count[194] | No | No | No | INPUT | |||
lc_otp_program_i.count[196:195] | Yes | Yes | *T171,*T175,*T160 | Yes | T171,T175,T160 | INPUT | |
lc_otp_program_i.count[197] | No | No | No | INPUT | |||
lc_otp_program_i.count[212:198] | Yes | Yes | *T62,*T170,*T118 | Yes | T62,T170,T118 | INPUT | |
lc_otp_program_i.count[214:213] | No | No | No | INPUT | |||
lc_otp_program_i.count[223:215] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | INPUT | |
lc_otp_program_i.count[224] | No | No | No | INPUT | |||
lc_otp_program_i.count[229:225] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | INPUT | |
lc_otp_program_i.count[231:230] | No | No | No | INPUT | |||
lc_otp_program_i.count[239:232] | Yes | Yes | *T62,*T170,*T118 | Yes | T62,T170,T118 | INPUT | |
lc_otp_program_i.count[240] | No | No | No | INPUT | |||
lc_otp_program_i.count[242:241] | Yes | Yes | *T171,*T175,*T160 | Yes | T171,T175,T160 | INPUT | |
lc_otp_program_i.count[243] | No | No | No | INPUT | |||
lc_otp_program_i.count[245:244] | Yes | Yes | T62,T170,T118 | Yes | T62,T170,T118 | INPUT | |
lc_otp_program_i.count[247:246] | No | No | No | INPUT | |||
lc_otp_program_i.count[256:248] | Yes | Yes | *T171,*T62,*T170 | Yes | T171,T62,T170 | INPUT | |
lc_otp_program_i.count[257] | No | No | No | INPUT | |||
lc_otp_program_i.count[261:258] | Yes | Yes | *T171,*T62,*T170 | Yes | T171,T62,T170 | INPUT | |
lc_otp_program_i.count[262] | No | No | No | INPUT | |||
lc_otp_program_i.count[284:263] | Yes | Yes | *T62,*T170,*T118 | Yes | T62,T170,T118 | INPUT | |
lc_otp_program_i.count[285] | No | No | No | INPUT | |||
lc_otp_program_i.count[288:286] | Yes | Yes | *T171,*T175,*T160 | Yes | T171,T175,T160 | INPUT | |
lc_otp_program_i.count[289] | No | No | No | INPUT | |||
lc_otp_program_i.count[294:290] | Yes | Yes | *T171,*T175,*T160 | Yes | T171,T175,T160 | INPUT | |
lc_otp_program_i.count[295] | No | No | No | INPUT | |||
lc_otp_program_i.count[305:296] | Yes | Yes | *T171,*T62,*T170 | Yes | T171,T62,T170 | INPUT | |
lc_otp_program_i.count[306] | No | No | No | INPUT | |||
lc_otp_program_i.count[308:307] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | INPUT | |
lc_otp_program_i.count[309] | No | No | No | INPUT | |||
lc_otp_program_i.count[322:310] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | INPUT | |
lc_otp_program_i.count[323] | No | No | No | INPUT | |||
lc_otp_program_i.count[338:324] | Yes | Yes | *T62,*T170,*T118 | Yes | T62,T170,T118 | INPUT | |
lc_otp_program_i.count[339] | No | No | No | INPUT | |||
lc_otp_program_i.count[348:340] | Yes | Yes | *T62,*T170,*T118 | Yes | T62,T170,T118 | INPUT | |
lc_otp_program_i.count[349] | No | No | No | INPUT | |||
lc_otp_program_i.count[351:350] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | INPUT | |
lc_otp_program_i.count[352] | No | No | No | INPUT | |||
lc_otp_program_i.count[363:353] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | INPUT | |
lc_otp_program_i.count[364] | No | No | No | INPUT | |||
lc_otp_program_i.count[367:365] | Yes | Yes | *T171,*T175,*T160 | Yes | T171,T175,T160 | INPUT | |
lc_otp_program_i.count[368] | No | No | No | INPUT | |||
lc_otp_program_i.count[383:369] | Yes | Yes | T171,T175,T160 | Yes | T171,T175,T160 | INPUT | |
lc_otp_program_i.state[15:0] | Yes | Yes | *T171,*T62,*T61 | Yes | T171,T62,T170 | INPUT | |
lc_otp_program_i.state[16] | No | No | No | INPUT | |||
lc_otp_program_i.state[21:17] | Yes | Yes | *T171,*T175,*T160 | Yes | T171,T175,T160 | INPUT | |
lc_otp_program_i.state[22] | No | No | No | INPUT | |||
lc_otp_program_i.state[24:23] | Yes | Yes | *T172,*T51,*T173 | Yes | T51,T173,T171 | INPUT | |
lc_otp_program_i.state[25] | No | No | No | INPUT | |||
lc_otp_program_i.state[37:26] | Yes | Yes | *T62,*T61,*T170 | Yes | T62,T170,T118 | INPUT | |
lc_otp_program_i.state[38] | No | No | No | INPUT | |||
lc_otp_program_i.state[42:39] | Yes | Yes | T171,*T175,*T160 | Yes | T171,T175,T160 | INPUT | |
lc_otp_program_i.state[43] | No | No | No | INPUT | |||
lc_otp_program_i.state[46:44] | Yes | Yes | T62,T61,T170 | Yes | T62,T170,T118 | INPUT | |
lc_otp_program_i.state[47] | No | No | No | INPUT | |||
lc_otp_program_i.state[51:48] | Yes | Yes | *T171,*T62,*T61 | Yes | T171,T62,T170 | INPUT | |
lc_otp_program_i.state[52] | No | No | No | INPUT | |||
lc_otp_program_i.state[56:53] | Yes | Yes | *T171,T62,T61 | Yes | T171,T62,T170 | INPUT | |
lc_otp_program_i.state[57] | No | No | No | INPUT | |||
lc_otp_program_i.state[67:58] | Yes | Yes | *T62,*T61,*T170 | Yes | T62,T170,T118 | INPUT | |
lc_otp_program_i.state[68] | No | No | No | INPUT | |||
lc_otp_program_i.state[83:69] | Yes | Yes | *T171,*T62,*T61 | Yes | T171,T62,T170 | INPUT | |
lc_otp_program_i.state[84] | No | No | No | INPUT | |||
lc_otp_program_i.state[87:85] | Yes | Yes | T62,T61,*T170 | Yes | T62,T170,T118 | INPUT | |
lc_otp_program_i.state[88] | No | No | No | INPUT | |||
lc_otp_program_i.state[91:89] | Yes | Yes | *T171,T62,T61 | Yes | T171,T62,T170 | INPUT | |
lc_otp_program_i.state[92] | No | No | No | INPUT | |||
lc_otp_program_i.state[104:93] | Yes | Yes | *T62,*T61,*T170 | Yes | T62,T170,T118 | INPUT | |
lc_otp_program_i.state[105] | No | No | No | INPUT | |||
lc_otp_program_i.state[126:106] | Yes | Yes | *T171,*T62,*T61 | Yes | T171,T62,T170 | INPUT | |
lc_otp_program_i.state[127] | No | No | No | INPUT | |||
lc_otp_program_i.state[155:128] | Yes | Yes | *T62,*T61,*T170 | Yes | T62,T170,T118 | INPUT | |
lc_otp_program_i.state[156] | No | No | No | INPUT | |||
lc_otp_program_i.state[159:157] | Yes | Yes | *T171,T62,T61 | Yes | T171,T62,T170 | INPUT | |
lc_otp_program_i.state[160] | No | No | No | INPUT | |||
lc_otp_program_i.state[166:161] | Yes | Yes | *T171,*T175,*T160 | Yes | T171,T175,T160 | INPUT | |
lc_otp_program_i.state[167] | No | No | No | INPUT | |||
lc_otp_program_i.state[176:168] | Yes | Yes | *T19,*T172,*T51 | Yes | T19,T51,T173 | INPUT | |
lc_otp_program_i.state[178:177] | No | No | No | INPUT | |||
lc_otp_program_i.state[193:179] | Yes | Yes | *T19,*T172,*T51 | Yes | T19,T51,T173 | INPUT | |
lc_otp_program_i.state[194] | No | No | No | INPUT | |||
lc_otp_program_i.state[214:195] | Yes | Yes | *T62,*T61,*T170 | Yes | T62,T170,T118 | INPUT | |
lc_otp_program_i.state[215] | No | No | No | INPUT | |||
lc_otp_program_i.state[220:216] | Yes | Yes | *T171,*T175,*T160 | Yes | T171,T175,T160 | INPUT | |
lc_otp_program_i.state[221] | No | No | No | INPUT | |||
lc_otp_program_i.state[222] | Yes | Yes | *T19,*T172,*T51 | Yes | T19,T51,T173 | INPUT | |
lc_otp_program_i.state[223] | No | No | No | INPUT | |||
lc_otp_program_i.state[227:224] | Yes | Yes | *T171,*T175,*T160 | Yes | T171,T175,T160 | INPUT | |
lc_otp_program_i.state[228] | No | No | No | INPUT | |||
lc_otp_program_i.state[230:229] | Yes | Yes | *T19,*T172,*T51 | Yes | T19,T51,T173 | INPUT | |
lc_otp_program_i.state[231] | No | No | No | INPUT | |||
lc_otp_program_i.state[232] | Yes | Yes | *T171,*T62,*T61 | Yes | T171,T62,T170 | INPUT | |
lc_otp_program_i.state[233] | No | No | No | INPUT | |||
lc_otp_program_i.state[254:234] | Yes | Yes | *T19,*T172,*T51 | Yes | T19,T51,T173 | INPUT | |
lc_otp_program_i.state[255] | No | No | No | INPUT | |||
lc_otp_program_i.state[265:256] | Yes | Yes | *T4,*T19,*T52 | Yes | T19,T21,T51 | INPUT | |
lc_otp_program_i.state[268:266] | No | No | No | INPUT | |||
lc_otp_program_i.state[277:269] | Yes | Yes | *T4,*T19,*T52 | Yes | T19,T21,T51 | INPUT | |
lc_otp_program_i.state[278] | No | No | No | INPUT | |||
lc_otp_program_i.state[285:279] | Yes | Yes | *T5,*T6,*T17 | Yes | T41,T42,T59 | INPUT | |
lc_otp_program_i.state[288:286] | No | No | No | INPUT | |||
lc_otp_program_i.state[294:289] | Yes | Yes | *T4,*T6,*T19 | Yes | T19,T21,T51 | INPUT | |
lc_otp_program_i.state[295] | No | No | No | INPUT | |||
lc_otp_program_i.state[303:296] | Yes | Yes | *T4,*T6,*T19 | Yes | T19,T21,T51 | INPUT | |
lc_otp_program_i.state[304] | No | No | No | INPUT | |||
lc_otp_program_i.state[312:305] | Yes | Yes | *T171,*T175,*T160 | Yes | T171,T175,T160 | INPUT | |
lc_otp_program_i.state[313] | No | No | No | INPUT | |||
lc_otp_program_i.state[319:314] | Yes | Yes | T4,T6,T19 | Yes | T19,T21,T51 | INPUT | |
lc_otp_program_i.req | Yes | Yes | T19,T62,T61 | Yes | T19,T62,T61 | INPUT | |
lc_otp_program_o.ack | Yes | Yes | T19,T62,T61 | Yes | T19,T62,T61 | OUTPUT | |
lc_otp_program_o.err | Yes | Yes | T61,T176,T177 | Yes | T61,T176,T177 | OUTPUT | |
lc_creator_seed_sw_rw_en_i[3:0] | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T6 | INPUT | |
lc_owner_seed_sw_rw_en_i[3:0] | Unreachable | Unreachable | Unreachable | INPUT | |||
lc_seed_hw_rd_en_i[3:0] | Yes | Yes | T41,T42,T59 | Yes | T5,T17,T60 | INPUT | |
lc_dft_en_i[3:0] | Yes | Yes | T41,T42,T59 | Yes | T5,T17,T60 | INPUT | |
lc_escalate_en_i[3:0] | Yes | Yes | T42,T63,T64 | Yes | T42,T63,T64 | INPUT | |
lc_check_byp_en_i[3:0] | Yes | Yes | T19,T61,T53 | Yes | T19,T62,T61 | INPUT | |
otp_lc_data_o.rma_token[127:0] | Yes | Yes | T4,T60,T18 | Yes | T42,T64,T178 | OUTPUT | |
otp_lc_data_o.rma_token_valid[3:0] | Yes | Yes | T20,T179,T180 | Yes | T20,T155,T113 | OUTPUT | |
otp_lc_data_o.test_exit_token[127:0] | Yes | Yes | T41,T42,T19 | Yes | T4,T6,T17 | OUTPUT | |
otp_lc_data_o.test_unlock_token[127:0] | Yes | Yes | T42,T178,T155 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.test_tokens_valid[3:0] | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.secrets_valid[3:0] | Yes | Yes | T20,T179,T180 | Yes | T20,T155,T113 | OUTPUT | |
otp_lc_data_o.count[0] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[11:1] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT | |
otp_lc_data_o.count[12] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[13] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT | |
otp_lc_data_o.count[14] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[20:15] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.count[21] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[22] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.count[23] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[25:24] | Yes | Yes | *T172,*T51,*T173 | Yes | T51,T173,T174 | OUTPUT | |
otp_lc_data_o.count[26] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[51:27] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.count[52] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[60:53] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT | |
otp_lc_data_o.count[61] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[65:62] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.count[66] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[70:67] | Yes | Yes | *T172,*T51,*T173 | Yes | T51,T173,T174 | OUTPUT | |
otp_lc_data_o.count[71] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[77:72] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.count[78] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[91:79] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT | |
otp_lc_data_o.count[92] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[106:93] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT | |
otp_lc_data_o.count[109:107] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[110] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.count[111] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[113:112] | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.count[114] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[116:115] | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.count[117] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[118] | Yes | Yes | *T4,*T6,*T54 | Yes | T21,T51,T173 | OUTPUT | |
otp_lc_data_o.count[119] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[127:120] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT | |
otp_lc_data_o.count[128] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[144:129] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT | |
otp_lc_data_o.count[145] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[146] | Yes | Yes | *T53,*T183,*T184 | Yes | T19,T61,T53 | OUTPUT | |
otp_lc_data_o.count[147] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[151:148] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT | |
otp_lc_data_o.count[152] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[154:153] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT | |
otp_lc_data_o.count[155] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[160:156] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT | |
otp_lc_data_o.count[161] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[165:162] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT | |
otp_lc_data_o.count[166] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[169:167] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT | |
otp_lc_data_o.count[171:170] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[177:172] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.count[178] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[180:179] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT | |
otp_lc_data_o.count[181] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[189:182] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT | |
otp_lc_data_o.count[190] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[193:191] | Yes | Yes | *T184,T185,*T186 | Yes | T61,T53,T183 | OUTPUT | |
otp_lc_data_o.count[194] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[196:195] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT | |
otp_lc_data_o.count[197] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[212:198] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT | |
otp_lc_data_o.count[214:213] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[223:215] | Yes | Yes | *T184,*T185,*T186 | Yes | T61,T184,T185 | OUTPUT | |
otp_lc_data_o.count[224] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[229:225] | Yes | Yes | *T184,*T186,*T187 | Yes | T61,T184,T185 | OUTPUT | |
otp_lc_data_o.count[231:230] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[239:232] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT | |
otp_lc_data_o.count[240] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[242:241] | Yes | Yes | T4,T5,T6 | Yes | T41,T42,T59 | OUTPUT | |
otp_lc_data_o.count[243] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[245:244] | Yes | Yes | T62,T170,T118 | Yes | T118,T181,T182 | OUTPUT | |
otp_lc_data_o.count[247:246] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[256:248] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.count[257] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[261:258] | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.count[262] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[284:263] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT | |
otp_lc_data_o.count[285] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[288:286] | Yes | Yes | T4,T5,T6 | Yes | T41,T42,T59 | OUTPUT | |
otp_lc_data_o.count[289] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[294:290] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT | |
otp_lc_data_o.count[295] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[305:296] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.count[306] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[308:307] | Yes | Yes | *T184,*T186,*T187 | Yes | T61,T184,T186 | OUTPUT | |
otp_lc_data_o.count[309] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[322:310] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT | |
otp_lc_data_o.count[323] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[338:324] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT | |
otp_lc_data_o.count[339] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[348:340] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT | |
otp_lc_data_o.count[349] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[351:350] | Yes | Yes | *T184,*T186,*T187 | Yes | T61,T184,T186 | OUTPUT | |
otp_lc_data_o.count[352] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[363:353] | Yes | Yes | *T184,*T186,*T187 | Yes | T61,T184,T186 | OUTPUT | |
otp_lc_data_o.count[364] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[367:365] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT | |
otp_lc_data_o.count[368] | No | No | No | OUTPUT | |||
otp_lc_data_o.count[383:369] | Yes | Yes | T4,T5,T6 | Yes | T41,T42,T59 | OUTPUT | |
otp_lc_data_o.state[15:0] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.state[16] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[21:17] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT | |
otp_lc_data_o.state[22] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[24:23] | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.state[25] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[37:26] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT | |
otp_lc_data_o.state[38] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[42:39] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT | |
otp_lc_data_o.state[43] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[46:44] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT | |
otp_lc_data_o.state[47] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[51:48] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.state[52] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[56:53] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.state[57] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[67:58] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT | |
otp_lc_data_o.state[68] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[83:69] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.state[84] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[87:85] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT | |
otp_lc_data_o.state[88] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[91:89] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.state[92] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[104:93] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT | |
otp_lc_data_o.state[105] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[126:106] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.state[127] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[155:128] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT | |
otp_lc_data_o.state[156] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[159:157] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.state[160] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[166:161] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT | |
otp_lc_data_o.state[167] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[176:168] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.state[178:177] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[193:179] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.state[194] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[214:195] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T182 | OUTPUT | |
otp_lc_data_o.state[215] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[220:216] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT | |
otp_lc_data_o.state[221] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[222] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.state[223] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[227:224] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT | |
otp_lc_data_o.state[228] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[230:229] | Yes | Yes | *T19,*T172,*T51 | Yes | T19,T51,T173 | OUTPUT | |
otp_lc_data_o.state[231] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[232] | Yes | Yes | *T41,*T42,*T59 | Yes | T4,T5,T6 | OUTPUT | |
otp_lc_data_o.state[233] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[254:234] | Yes | Yes | *T19,*T172,*T51 | Yes | T19,T51,T173 | OUTPUT | |
otp_lc_data_o.state[255] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[265:256] | Yes | Yes | *T4,*T19,*T52 | Yes | T19,T21,T51 | OUTPUT | |
otp_lc_data_o.state[268:266] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[277:269] | Yes | Yes | *T41,*T42,*T59 | Yes | T5,T6,T17 | OUTPUT | |
otp_lc_data_o.state[278] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[285:279] | Yes | Yes | *T5,*T6,*T17 | Yes | T41,T42,T59 | OUTPUT | |
otp_lc_data_o.state[288:286] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[294:289] | Yes | Yes | *T41,*T42,*T59 | Yes | T5,T17,T60 | OUTPUT | |
otp_lc_data_o.state[295] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[303:296] | Yes | Yes | *T4,*T6,*T19 | Yes | T19,T21,T51 | OUTPUT | |
otp_lc_data_o.state[304] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[312:305] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT | |
otp_lc_data_o.state[313] | No | No | No | OUTPUT | |||
otp_lc_data_o.state[319:314] | Yes | Yes | T4,T6,T19 | Yes | T19,T21,T51 | OUTPUT | |
otp_lc_data_o.error | Yes | Yes | T42,T63,T64 | Yes | T42,T63,T64 | OUTPUT | |
otp_lc_data_o.valid | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T6 | OUTPUT | |
otp_keymgr_key_o.owner_seed_valid | No | No | No | OUTPUT | |||
otp_keymgr_key_o.owner_seed[255:0] | No | No | No | OUTPUT | |||
otp_keymgr_key_o.creator_seed_valid | No | No | No | OUTPUT | |||
otp_keymgr_key_o.creator_seed[255:0] | No | No | No | OUTPUT | |||
otp_keymgr_key_o.creator_root_key_share1_valid | Yes | Yes | T20,T179,T180 | Yes | T20,T155,T113 | OUTPUT | |
otp_keymgr_key_o.creator_root_key_share1[255:0] | Yes | Yes | T41,T59,T188 | Yes | T5,T60,T18 | OUTPUT | |
otp_keymgr_key_o.creator_root_key_share0_valid | Yes | Yes | T20,T179,T180 | Yes | T20,T155,T113 | OUTPUT | |
otp_keymgr_key_o.creator_root_key_share0[255:0] | Yes | Yes | T41,T42,T20 | Yes | T17,T18,T41 | OUTPUT | |
flash_otp_key_i.addr_req | Yes | Yes | T4,T5,T17 | Yes | T4,T5,T17 | INPUT | |
flash_otp_key_i.data_req | Yes | Yes | T4,T5,T17 | Yes | T4,T5,T17 | INPUT | |
flash_otp_key_o.seed_valid | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T17 | OUTPUT | |
flash_otp_key_o.rand_key[127:0] | Yes | Yes | T4,T60,T18 | Yes | T4,T5,T17 | OUTPUT | |
flash_otp_key_o.key[127:0] | Yes | Yes | T4,T5,T17 | Yes | T4,T41,T59 | OUTPUT | |
flash_otp_key_o.addr_ack | Yes | Yes | T4,T5,T17 | Yes | T4,T5,T17 | OUTPUT | |
flash_otp_key_o.data_ack | Yes | Yes | T4,T5,T17 | Yes | T4,T5,T17 | OUTPUT | |
sram_otp_key_i[0].req | Yes | Yes | T4,T20,T52 | Yes | T4,T20,T52 | INPUT | |
sram_otp_key_i[1].req | Yes | Yes | T116,T117,T189 | Yes | T116,T117,T189 | INPUT | |
sram_otp_key_i[2].req | Yes | Yes | T190,T191,T192 | Yes | T190,T191,T192 | INPUT | |
sram_otp_key_i[3].req | No | No | No | INPUT | |||
sram_otp_key_o[0].seed_valid | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T17 | OUTPUT | |
sram_otp_key_o[0].nonce[127:0] | Yes | Yes | T4,T60,T18 | Yes | T4,T5,T17 | OUTPUT | |
sram_otp_key_o[0].key[127:0] | Yes | Yes | T4,T5,T17 | Yes | T4,T41,T59 | OUTPUT | |
sram_otp_key_o[0].ack | Yes | Yes | T4,T20,T52 | Yes | T4,T20,T52 | OUTPUT | |
sram_otp_key_o[1].seed_valid | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T17 | OUTPUT | |
sram_otp_key_o[1].nonce[127:0] | Yes | Yes | T4,T60,T18 | Yes | T4,T5,T17 | OUTPUT | |
sram_otp_key_o[1].key[127:0] | Yes | Yes | T4,T5,T17 | Yes | T4,T41,T59 | OUTPUT | |
sram_otp_key_o[1].ack | Yes | Yes | T116,T117,T189 | Yes | T116,T117,T189 | OUTPUT | |
sram_otp_key_o[2].seed_valid | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T17 | OUTPUT | |
sram_otp_key_o[2].nonce[127:0] | Yes | Yes | T4,T60,T18 | Yes | T4,T5,T17 | OUTPUT | |
sram_otp_key_o[2].key[127:0] | Yes | Yes | T4,T5,T17 | Yes | T4,T41,T59 | OUTPUT | |
sram_otp_key_o[2].ack | Yes | Yes | T190,T193,T194 | Yes | T190,T193,T194 | OUTPUT | |
sram_otp_key_o[3].seed_valid | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T17 | OUTPUT | |
sram_otp_key_o[3].nonce[127:0] | Yes | Yes | T4,T60,T18 | Yes | T4,T5,T17 | OUTPUT | |
sram_otp_key_o[3].key[127:0] | Yes | Yes | T4,T5,T17 | Yes | T4,T41,T59 | OUTPUT | |
sram_otp_key_o[3].ack | No | No | No | OUTPUT | |||
otbn_otp_key_i.req | Yes | Yes | T4,T20,T52 | Yes | T4,T20,T52 | INPUT | |
otbn_otp_key_o.seed_valid | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T17 | OUTPUT | |
otbn_otp_key_o.nonce[63:0] | Yes | Yes | T4,T60,T18 | Yes | T4,T5,T17 | OUTPUT | |
otbn_otp_key_o.key[127:0] | Yes | Yes | T4,T5,T17 | Yes | T4,T41,T59 | OUTPUT | |
otbn_otp_key_o.ack | Yes | Yes | T4,T20,T52 | Yes | T4,T20,T52 | OUTPUT | |
otp_broadcast_o.hw_cfg0_data.device_id[255:0] | Yes | Yes | T4,T5,T6 | Yes | T42,T21,T178 | OUTPUT | |
otp_broadcast_o.hw_cfg0_data.manuf_state[17:0] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT | |
otp_broadcast_o.hw_cfg0_data.manuf_state[18] | No | No | No | OUTPUT | |||
otp_broadcast_o.hw_cfg0_data.manuf_state[35:19] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT | |
otp_broadcast_o.hw_cfg0_data.manuf_state[36] | No | No | No | OUTPUT | |||
otp_broadcast_o.hw_cfg0_data.manuf_state[91:37] | Yes | Yes | *T195,*T196,*T4 | Yes | T195,T196,T41 | OUTPUT | |
otp_broadcast_o.hw_cfg0_data.manuf_state[92] | No | No | No | OUTPUT | |||
otp_broadcast_o.hw_cfg0_data.manuf_state[98:93] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT | |
otp_broadcast_o.hw_cfg0_data.manuf_state[99] | No | No | No | OUTPUT | |||
otp_broadcast_o.hw_cfg0_data.manuf_state[107:100] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT | |
otp_broadcast_o.hw_cfg0_data.manuf_state[108] | No | No | No | OUTPUT | |||
otp_broadcast_o.hw_cfg0_data.manuf_state[160:109] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT | |
otp_broadcast_o.hw_cfg0_data.manuf_state[161] | No | No | No | OUTPUT | |||
otp_broadcast_o.hw_cfg0_data.manuf_state[197:162] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT | |
otp_broadcast_o.hw_cfg0_data.manuf_state[198] | No | No | No | OUTPUT | |||
otp_broadcast_o.hw_cfg0_data.manuf_state[207:199] | Yes | Yes | *T196,*T195,*T197 | Yes | T196,T195,T197 | OUTPUT | |
otp_broadcast_o.hw_cfg0_data.manuf_state[208] | No | No | No | OUTPUT | |||
otp_broadcast_o.hw_cfg0_data.manuf_state[249:209] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT | |
otp_broadcast_o.hw_cfg0_data.manuf_state[250] | No | No | No | OUTPUT | |||
otp_broadcast_o.hw_cfg0_data.manuf_state[251] | Yes | Yes | *T4,*T5,*T6 | Yes | T41,T42,T59 | OUTPUT | |
otp_broadcast_o.hw_cfg0_data.manuf_state[252] | No | No | No | OUTPUT | |||
otp_broadcast_o.hw_cfg0_data.manuf_state[255:253] | Yes | Yes | T196,T4,T5 | Yes | T196,T41,T42 | OUTPUT | |
otp_broadcast_o.hw_cfg0_data.hw_cfg0_digest[63:0] | Yes | Yes | T41,T63,T64 | Yes | T6,T17,T60 | OUTPUT | |
otp_broadcast_o.hw_cfg1_data.en_sram_ifetch[7:0] | Yes | Yes | T4,T5,T6 | Yes | T41,T42,T59 | OUTPUT | |
otp_broadcast_o.hw_cfg1_data.en_csrng_sw_app_read[7:0] | Yes | Yes | T4,T5,T6 | Yes | T41,T42,T59 | OUTPUT | |
otp_broadcast_o.hw_cfg1_data.dis_rv_dm_late_debug[7:0] | Yes | Yes | T4,T5,T6 | Yes | T41,T42,T59 | OUTPUT | |
otp_broadcast_o.hw_cfg1_data.unallocated[39:0] | No | No | No | OUTPUT | |||
otp_broadcast_o.hw_cfg1_data.hw_cfg1_digest[39:0] | Yes | Yes | *T62,*T170,*T118 | Yes | T118,T181,T191 | OUTPUT | |
otp_broadcast_o.hw_cfg1_data.hw_cfg1_digest[40] | No | No | No | OUTPUT | |||
otp_broadcast_o.hw_cfg1_data.hw_cfg1_digest[63:41] | Yes | Yes | T5,T6,T17 | Yes | T41,T42,T59 | OUTPUT | |
otp_broadcast_o.valid[3:0] | Yes | Yes | T41,T42,T59 | Yes | T4,T5,T6 | OUTPUT | |
otp_ext_voltage_h_io[0:0] | Excluded | Excluded | Excluded | INOUT | [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and OTP. Must be covered in vendor closed source DV. | ||
scan_en_i | Unreachable | Unreachable | Unreachable | INPUT | |||
scan_rst_ni | Unreachable | Unreachable | Unreachable | INPUT | |||
scanmode_i[3:0] | Unreachable | Unreachable | Unreachable | INPUT | |||
cio_test_o[7:0] | No | No | No | OUTPUT | |||
cio_test_en_o[7:0] | Yes | Yes | T41,T42,T59 | Yes | T5,T17,T60 | OUTPUT |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |