Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T190,T194
0	1	Covered	T190,T194,T305
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T190,T194,T305
1	Covered	T1,T190,T194

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T190,T194,T305
1	Covered	T1,T190,T194

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T190,T194,T305
1	1	Covered	T190,T194,T305

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T190,T194
1	0	Covered	T190,T194,T305
1	1	Covered	T190,T194,T305

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T190,T194,T305

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T190,T194
0	Covered	T190,T194,T305

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T190,T194
0	Covered	T190,T194,T305

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1028681108	1012537330	0	0
CheckNGreaterZero_A	2042	2042	0	0
GntImpliesReady_A	1028681108	8377	0	0
GntImpliesValid_A	1028681108	8377	0	0
GrantKnown_A	1028681108	1012537330	0	0
IdxKnown_A	1028681108	1012537330	0	0
IndexIsCorrect_A	1028681108	8377	0	0
NoReadyValidNoGrant_A	1028681108	0	0	0
Priority_A	1028681108	8377	0	0
ReadyAndValidImplyGrant_A	1028681108	8377	0	0
ReqAndReadyImplyGrant_A	1028681108	8377	0	0
ReqImpliesValid_A	1028681108	8377	0	0
ValidKnown_A	1028681108	1012537330	0	0
gen_data_port_assertion.DataFlow_A	1028681108	8377	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028681108	1012537330	0	0
T4	449148	449134	0	0
T5	313534	313424	0	0
T6	167968	167844	0	0
T17	423430	423314	0	0
T18	305472	305356	0	0
T19	400774	400460	0	0
T41	372776	372456	0	0
T42	553240	553020	0	0
T59	378952	378756	0	0
T60	148238	148122	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2042	2042	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T17	2	2	0	0
T18	2	2	0	0
T19	2	2	0	0
T41	2	2	0	0
T42	2	2	0	0
T59	2	2	0	0
T60	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028681108	8377	0	0
T86	1228444	0	0	0
T190	206876	2790	0	0
T194	0	2791	0	0
T217	195460	0	0	0
T229	843332	0	0	0
T230	807410	0	0	0
T270	532170	0	0	0
T305	0	2796	0	0
T308	259190	0	0	0
T309	339672	0	0	0
T310	181836	0	0	0
T311	175574	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028681108	8377	0	0
T86	1228444	0	0	0
T190	206876	2790	0	0
T194	0	2791	0	0
T217	195460	0	0	0
T229	843332	0	0	0
T230	807410	0	0	0
T270	532170	0	0	0
T305	0	2796	0	0
T308	259190	0	0	0
T309	339672	0	0	0
T310	181836	0	0	0
T311	175574	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028681108	1012537330	0	0
T4	449148	449134	0	0
T5	313534	313424	0	0
T6	167968	167844	0	0
T17	423430	423314	0	0
T18	305472	305356	0	0
T19	400774	400460	0	0
T41	372776	372456	0	0
T42	553240	553020	0	0
T59	378952	378756	0	0
T60	148238	148122	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028681108	1012537330	0	0
T4	449148	449134	0	0
T5	313534	313424	0	0
T6	167968	167844	0	0
T17	423430	423314	0	0
T18	305472	305356	0	0
T19	400774	400460	0	0
T41	372776	372456	0	0
T42	553240	553020	0	0
T59	378952	378756	0	0
T60	148238	148122	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028681108	8377	0	0
T86	1228444	0	0	0
T190	206876	2790	0	0
T194	0	2791	0	0
T217	195460	0	0	0
T229	843332	0	0	0
T230	807410	0	0	0
T270	532170	0	0	0
T305	0	2796	0	0
T308	259190	0	0	0
T309	339672	0	0	0
T310	181836	0	0	0
T311	175574	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028681108	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028681108	8377	0	0
T86	1228444	0	0	0
T190	206876	2790	0	0
T194	0	2791	0	0
T217	195460	0	0	0
T229	843332	0	0	0
T230	807410	0	0	0
T270	532170	0	0	0
T305	0	2796	0	0
T308	259190	0	0	0
T309	339672	0	0	0
T310	181836	0	0	0
T311	175574	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028681108	8377	0	0
T86	1228444	0	0	0
T190	206876	2790	0	0
T194	0	2791	0	0
T217	195460	0	0	0
T229	843332	0	0	0
T230	807410	0	0	0
T270	532170	0	0	0
T305	0	2796	0	0
T308	259190	0	0	0
T309	339672	0	0	0
T310	181836	0	0	0
T311	175574	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028681108	8377	0	0
T86	1228444	0	0	0
T190	206876	2790	0	0
T194	0	2791	0	0
T217	195460	0	0	0
T229	843332	0	0	0
T230	807410	0	0	0
T270	532170	0	0	0
T305	0	2796	0	0
T308	259190	0	0	0
T309	339672	0	0	0
T310	181836	0	0	0
T311	175574	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028681108	8377	0	0
T86	1228444	0	0	0
T190	206876	2790	0	0
T194	0	2791	0	0
T217	195460	0	0	0
T229	843332	0	0	0
T230	807410	0	0	0
T270	532170	0	0	0
T305	0	2796	0	0
T308	259190	0	0	0
T309	339672	0	0	0
T310	181836	0	0	0
T311	175574	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028681108	1012537330	0	0
T4	449148	449134	0	0
T5	313534	313424	0	0
T6	167968	167844	0	0
T17	423430	423314	0	0
T18	305472	305356	0	0
T19	400774	400460	0	0
T41	372776	372456	0	0
T42	553240	553020	0	0
T59	378952	378756	0	0
T60	148238	148122	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028681108	8377	0	0
T86	1228444	0	0	0
T190	206876	2790	0	0
T194	0	2791	0	0
T217	195460	0	0	0
T229	843332	0	0	0
T230	807410	0	0	0
T270	532170	0	0	0
T305	0	2796	0	0
T308	259190	0	0	0
T309	339672	0	0	0
T310	181836	0	0	0
T311	175574	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T190,T194
0	1	Covered	T190,T194,T305
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T190,T194,T305
1	Covered	T1,T190,T194

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T190,T194,T305
1	Covered	T1,T190,T194

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T190,T194,T305
1	1	Covered	T190,T194,T305

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T190,T194
1	0	Covered	T190,T194,T305
1	1	Covered	T190,T194,T305

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T190,T194,T305

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T190,T194
0	Covered	T190,T194,T305

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T190,T194
0	Covered	T190,T194,T305

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	514340554	506268665	0	0
CheckNGreaterZero_A	1021	1021	0	0
GntImpliesReady_A	514340554	5189	0	0
GntImpliesValid_A	514340554	5189	0	0
GrantKnown_A	514340554	506268665	0	0
IdxKnown_A	514340554	506268665	0	0
IndexIsCorrect_A	514340554	5189	0	0
NoReadyValidNoGrant_A	514340554	0	0	0
Priority_A	514340554	5189	0	0
ReadyAndValidImplyGrant_A	514340554	5189	0	0
ReqAndReadyImplyGrant_A	514340554	5189	0	0
ReqImpliesValid_A	514340554	5189	0	0
ValidKnown_A	514340554	506268665	0	0
gen_data_port_assertion.DataFlow_A	514340554	5189	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	506268665	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	5189	0	0
T86	614222	0	0	0
T190	103438	1728	0	0
T194	0	1728	0	0
T217	97730	0	0	0
T229	421666	0	0	0
T230	403705	0	0	0
T270	266085	0	0	0
T305	0	1733	0	0
T308	129595	0	0	0
T309	169836	0	0	0
T310	90918	0	0	0
T311	87787	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	5189	0	0
T86	614222	0	0	0
T190	103438	1728	0	0
T194	0	1728	0	0
T217	97730	0	0	0
T229	421666	0	0	0
T230	403705	0	0	0
T270	266085	0	0	0
T305	0	1733	0	0
T308	129595	0	0	0
T309	169836	0	0	0
T310	90918	0	0	0
T311	87787	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	506268665	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	506268665	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	5189	0	0
T86	614222	0	0	0
T190	103438	1728	0	0
T194	0	1728	0	0
T217	97730	0	0	0
T229	421666	0	0	0
T230	403705	0	0	0
T270	266085	0	0	0
T305	0	1733	0	0
T308	129595	0	0	0
T309	169836	0	0	0
T310	90918	0	0	0
T311	87787	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	5189	0	0
T86	614222	0	0	0
T190	103438	1728	0	0
T194	0	1728	0	0
T217	97730	0	0	0
T229	421666	0	0	0
T230	403705	0	0	0
T270	266085	0	0	0
T305	0	1733	0	0
T308	129595	0	0	0
T309	169836	0	0	0
T310	90918	0	0	0
T311	87787	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	5189	0	0
T86	614222	0	0	0
T190	103438	1728	0	0
T194	0	1728	0	0
T217	97730	0	0	0
T229	421666	0	0	0
T230	403705	0	0	0
T270	266085	0	0	0
T305	0	1733	0	0
T308	129595	0	0	0
T309	169836	0	0	0
T310	90918	0	0	0
T311	87787	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	5189	0	0
T86	614222	0	0	0
T190	103438	1728	0	0
T194	0	1728	0	0
T217	97730	0	0	0
T229	421666	0	0	0
T230	403705	0	0	0
T270	266085	0	0	0
T305	0	1733	0	0
T308	129595	0	0	0
T309	169836	0	0	0
T310	90918	0	0	0
T311	87787	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	5189	0	0
T86	614222	0	0	0
T190	103438	1728	0	0
T194	0	1728	0	0
T217	97730	0	0	0
T229	421666	0	0	0
T230	403705	0	0	0
T270	266085	0	0	0
T305	0	1733	0	0
T308	129595	0	0	0
T309	169836	0	0	0
T310	90918	0	0	0
T311	87787	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	506268665	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	5189	0	0
T86	614222	0	0	0
T190	103438	1728	0	0
T194	0	1728	0	0
T217	97730	0	0	0
T229	421666	0	0	0
T230	403705	0	0	0
T270	266085	0	0	0
T305	0	1733	0	0
T308	129595	0	0	0
T309	169836	0	0	0
T310	90918	0	0	0
T311	87787	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T190,T194
0	1	Covered	T190,T194,T305
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T190,T194,T305
1	Covered	T1,T190,T194

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T190,T194,T305
1	Covered	T1,T190,T194

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T190,T194,T305
1	1	Covered	T190,T194,T305

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T190,T194
1	0	Covered	T190,T194,T305
1	1	Covered	T190,T194,T305

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T190,T194,T305

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T190,T194
0	Covered	T190,T194,T305

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T190,T194
0	Covered	T190,T194,T305

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	514340554	506268665	0	0
CheckNGreaterZero_A	1021	1021	0	0
GntImpliesReady_A	514340554	3188	0	0
GntImpliesValid_A	514340554	3188	0	0
GrantKnown_A	514340554	506268665	0	0
IdxKnown_A	514340554	506268665	0	0
IndexIsCorrect_A	514340554	3188	0	0
NoReadyValidNoGrant_A	514340554	0	0	0
Priority_A	514340554	3188	0	0
ReadyAndValidImplyGrant_A	514340554	3188	0	0
ReqAndReadyImplyGrant_A	514340554	3188	0	0
ReqImpliesValid_A	514340554	3188	0	0
ValidKnown_A	514340554	506268665	0	0
gen_data_port_assertion.DataFlow_A	514340554	3188	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	506268665	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T41	1	1	0	0
T42	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	3188	0	0
T86	614222	0	0	0
T190	103438	1062	0	0
T194	0	1063	0	0
T217	97730	0	0	0
T229	421666	0	0	0
T230	403705	0	0	0
T270	266085	0	0	0
T305	0	1063	0	0
T308	129595	0	0	0
T309	169836	0	0	0
T310	90918	0	0	0
T311	87787	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	3188	0	0
T86	614222	0	0	0
T190	103438	1062	0	0
T194	0	1063	0	0
T217	97730	0	0	0
T229	421666	0	0	0
T230	403705	0	0	0
T270	266085	0	0	0
T305	0	1063	0	0
T308	129595	0	0	0
T309	169836	0	0	0
T310	90918	0	0	0
T311	87787	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	506268665	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	506268665	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	3188	0	0
T86	614222	0	0	0
T190	103438	1062	0	0
T194	0	1063	0	0
T217	97730	0	0	0
T229	421666	0	0	0
T230	403705	0	0	0
T270	266085	0	0	0
T305	0	1063	0	0
T308	129595	0	0	0
T309	169836	0	0	0
T310	90918	0	0	0
T311	87787	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	3188	0	0
T86	614222	0	0	0
T190	103438	1062	0	0
T194	0	1063	0	0
T217	97730	0	0	0
T229	421666	0	0	0
T230	403705	0	0	0
T270	266085	0	0	0
T305	0	1063	0	0
T308	129595	0	0	0
T309	169836	0	0	0
T310	90918	0	0	0
T311	87787	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	3188	0	0
T86	614222	0	0	0
T190	103438	1062	0	0
T194	0	1063	0	0
T217	97730	0	0	0
T229	421666	0	0	0
T230	403705	0	0	0
T270	266085	0	0	0
T305	0	1063	0	0
T308	129595	0	0	0
T309	169836	0	0	0
T310	90918	0	0	0
T311	87787	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	3188	0	0
T86	614222	0	0	0
T190	103438	1062	0	0
T194	0	1063	0	0
T217	97730	0	0	0
T229	421666	0	0	0
T230	403705	0	0	0
T270	266085	0	0	0
T305	0	1063	0	0
T308	129595	0	0	0
T309	169836	0	0	0
T310	90918	0	0	0
T311	87787	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	3188	0	0
T86	614222	0	0	0
T190	103438	1062	0	0
T194	0	1063	0	0
T217	97730	0	0	0
T229	421666	0	0	0
T230	403705	0	0	0
T270	266085	0	0	0
T305	0	1063	0	0
T308	129595	0	0	0
T309	169836	0	0	0
T310	90918	0	0	0
T311	87787	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	506268665	0	0
T4	224574	224567	0	0
T5	156767	156712	0	0
T6	83984	83922	0	0
T17	211715	211657	0	0
T18	152736	152678	0	0
T19	200387	200230	0	0
T41	186388	186228	0	0
T42	276620	276510	0	0
T59	189476	189378	0	0
T60	74119	74061	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514340554	3188	0	0
T86	614222	0	0	0
T190	103438	1062	0	0
T194	0	1063	0	0
T217	97730	0	0	0
T229	421666	0	0	0
T230	403705	0	0	0
T270	266085	0	0	0
T305	0	1063	0	0
T308	129595	0	0	0
T309	169836	0	0	0
T310	90918	0	0	0
T311	87787	0	0	0