| T738 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1857008996 |
|
|
Jul 21 07:55:43 PM PDT 24 |
Jul 21 08:00:56 PM PDT 24 |
3169973236 ps |
| T451 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2758995840 |
|
|
Jul 21 07:32:53 PM PDT 24 |
Jul 21 08:38:12 PM PDT 24 |
17685697112 ps |
| T953 |
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1330691455 |
|
|
Jul 21 07:54:54 PM PDT 24 |
Jul 21 09:40:21 PM PDT 24 |
26799315064 ps |
| T954 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1813541401 |
|
|
Jul 21 07:30:29 PM PDT 24 |
Jul 21 07:41:54 PM PDT 24 |
4449318488 ps |
| T955 |
/workspace/coverage/default/2.chip_sw_example_rom.2618867870 |
|
|
Jul 21 07:41:54 PM PDT 24 |
Jul 21 07:44:18 PM PDT 24 |
2678130054 ps |
| T956 |
/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1276159693 |
|
|
Jul 21 07:38:44 PM PDT 24 |
Jul 21 07:48:21 PM PDT 24 |
4584350550 ps |
| T957 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2398854754 |
|
|
Jul 21 07:37:26 PM PDT 24 |
Jul 21 08:26:35 PM PDT 24 |
31120055000 ps |
| T226 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.2803669122 |
|
|
Jul 21 07:44:12 PM PDT 24 |
Jul 21 09:11:02 PM PDT 24 |
49238775816 ps |
| T227 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2975471731 |
|
|
Jul 21 07:30:26 PM PDT 24 |
Jul 21 09:08:45 PM PDT 24 |
50866125905 ps |
| T958 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.2324667718 |
|
|
Jul 21 07:44:12 PM PDT 24 |
Jul 21 08:02:30 PM PDT 24 |
8262609575 ps |
| T959 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.3050645296 |
|
|
Jul 21 07:37:23 PM PDT 24 |
Jul 21 09:12:49 PM PDT 24 |
21989587287 ps |
| T960 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.125108305 |
|
|
Jul 21 07:33:21 PM PDT 24 |
Jul 21 07:40:10 PM PDT 24 |
3928423240 ps |
| T717 |
/workspace/coverage/default/4.chip_tap_straps_dev.2113946598 |
|
|
Jul 21 07:52:14 PM PDT 24 |
Jul 21 08:04:05 PM PDT 24 |
8564219291 ps |
| T961 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.220158611 |
|
|
Jul 21 07:28:27 PM PDT 24 |
Jul 21 07:38:35 PM PDT 24 |
4081579380 ps |
| T962 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3003888545 |
|
|
Jul 21 07:31:42 PM PDT 24 |
Jul 21 07:39:12 PM PDT 24 |
6568062088 ps |
| T365 |
/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.3601688927 |
|
|
Jul 21 07:45:29 PM PDT 24 |
Jul 21 08:15:11 PM PDT 24 |
10738475787 ps |
| T237 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.643534066 |
|
|
Jul 21 07:59:06 PM PDT 24 |
Jul 21 08:12:23 PM PDT 24 |
6012976300 ps |
| T259 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx.1259443856 |
|
|
Jul 21 07:33:59 PM PDT 24 |
Jul 21 07:46:25 PM PDT 24 |
4523199228 ps |
| T151 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.820742836 |
|
|
Jul 21 08:00:20 PM PDT 24 |
Jul 21 08:06:12 PM PDT 24 |
3710582210 ps |
| T260 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2895997690 |
|
|
Jul 21 07:53:52 PM PDT 24 |
Jul 21 08:00:34 PM PDT 24 |
3999488552 ps |
| T209 |
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3558792410 |
|
|
Jul 21 07:52:43 PM PDT 24 |
Jul 21 08:23:49 PM PDT 24 |
8028289832 ps |
| T261 |
/workspace/coverage/default/1.rom_keymgr_functest.470280177 |
|
|
Jul 21 07:41:25 PM PDT 24 |
Jul 21 07:50:53 PM PDT 24 |
5245743576 ps |
| T262 |
/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.3435135125 |
|
|
Jul 21 07:42:54 PM PDT 24 |
Jul 21 07:46:32 PM PDT 24 |
2492575092 ps |
| T263 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter.4158057572 |
|
|
Jul 21 07:48:56 PM PDT 24 |
Jul 21 07:52:36 PM PDT 24 |
2667271286 ps |
| T264 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.2914361143 |
|
|
Jul 21 07:32:24 PM PDT 24 |
Jul 21 07:54:45 PM PDT 24 |
9095337860 ps |
| T265 |
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3042365181 |
|
|
Jul 21 07:58:11 PM PDT 24 |
Jul 21 08:02:57 PM PDT 24 |
3317249016 ps |
| T963 |
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.243314623 |
|
|
Jul 21 07:54:20 PM PDT 24 |
Jul 21 08:01:57 PM PDT 24 |
6141174928 ps |
| T267 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2233305760 |
|
|
Jul 21 07:37:20 PM PDT 24 |
Jul 21 08:34:25 PM PDT 24 |
14952735554 ps |
| T964 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1539871411 |
|
|
Jul 21 07:32:22 PM PDT 24 |
Jul 21 07:56:20 PM PDT 24 |
14504532082 ps |
| T754 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.2234235152 |
|
|
Jul 21 08:01:51 PM PDT 24 |
Jul 21 08:11:21 PM PDT 24 |
5595620422 ps |
| T965 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.3702227168 |
|
|
Jul 21 07:28:13 PM PDT 24 |
Jul 21 07:39:17 PM PDT 24 |
3902357126 ps |
| T48 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.795432634 |
|
|
Jul 21 07:38:19 PM PDT 24 |
Jul 21 07:46:25 PM PDT 24 |
6073089448 ps |
| T177 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.816262077 |
|
|
Jul 21 07:29:31 PM PDT 24 |
Jul 21 09:03:49 PM PDT 24 |
44913079992 ps |
| T966 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.3284841241 |
|
|
Jul 21 07:33:43 PM PDT 24 |
Jul 21 07:48:20 PM PDT 24 |
5895091422 ps |
| T967 |
/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.15786663 |
|
|
Jul 21 07:54:14 PM PDT 24 |
Jul 21 08:03:12 PM PDT 24 |
3203985248 ps |
| T968 |
/workspace/coverage/default/1.chip_sw_aes_entropy.222702405 |
|
|
Jul 21 07:36:12 PM PDT 24 |
Jul 21 07:39:40 PM PDT 24 |
2723783780 ps |
| T734 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3816335438 |
|
|
Jul 21 08:01:07 PM PDT 24 |
Jul 21 08:07:01 PM PDT 24 |
3173538568 ps |
| T762 |
/workspace/coverage/default/0.chip_sw_ast_clk_outputs.1694088125 |
|
|
Jul 21 07:30:16 PM PDT 24 |
Jul 21 07:52:08 PM PDT 24 |
7640395178 ps |
| T246 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.4200891612 |
|
|
Jul 21 07:41:36 PM PDT 24 |
Jul 21 07:49:42 PM PDT 24 |
4488540520 ps |
| T268 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.612746541 |
|
|
Jul 21 07:41:27 PM PDT 24 |
Jul 21 08:43:51 PM PDT 24 |
14323312916 ps |
| T969 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.431156417 |
|
|
Jul 21 07:39:36 PM PDT 24 |
Jul 21 07:47:09 PM PDT 24 |
3260503466 ps |
| T970 |
/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3157018725 |
|
|
Jul 21 07:50:59 PM PDT 24 |
Jul 21 07:56:03 PM PDT 24 |
3034836628 ps |
| T971 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1789397292 |
|
|
Jul 21 07:29:31 PM PDT 24 |
Jul 21 07:48:27 PM PDT 24 |
6006196310 ps |
| T825 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.3346053020 |
|
|
Jul 21 07:55:27 PM PDT 24 |
Jul 21 08:04:50 PM PDT 24 |
6014575864 ps |
| T243 |
/workspace/coverage/default/36.chip_sw_all_escalation_resets.4022343187 |
|
|
Jul 21 07:56:26 PM PDT 24 |
Jul 21 08:07:17 PM PDT 24 |
5509255650 ps |
| T269 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.108380260 |
|
|
Jul 21 07:35:23 PM PDT 24 |
Jul 21 07:37:20 PM PDT 24 |
2231710260 ps |
| T290 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.3309177166 |
|
|
Jul 21 07:31:07 PM PDT 24 |
Jul 21 08:04:15 PM PDT 24 |
9870364836 ps |
| T197 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2418344293 |
|
|
Jul 21 07:31:50 PM PDT 24 |
Jul 21 07:41:44 PM PDT 24 |
5144266911 ps |
| T291 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.2658033785 |
|
|
Jul 21 07:35:59 PM PDT 24 |
Jul 21 07:56:22 PM PDT 24 |
5651476243 ps |
| T83 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2716659610 |
|
|
Jul 21 07:32:39 PM PDT 24 |
Jul 21 07:56:19 PM PDT 24 |
13028500136 ps |
| T98 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3221266945 |
|
|
Jul 21 07:32:37 PM PDT 24 |
Jul 21 08:02:18 PM PDT 24 |
19841662718 ps |
| T292 |
/workspace/coverage/default/2.chip_sw_edn_kat.2068265707 |
|
|
Jul 21 07:48:48 PM PDT 24 |
Jul 21 07:59:30 PM PDT 24 |
3284329592 ps |
| T293 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1524023305 |
|
|
Jul 21 07:53:58 PM PDT 24 |
Jul 21 08:01:04 PM PDT 24 |
4086893252 ps |
| T294 |
/workspace/coverage/default/0.chip_sw_edn_kat.3184442634 |
|
|
Jul 21 07:29:03 PM PDT 24 |
Jul 21 07:41:35 PM PDT 24 |
3574981210 ps |
| T972 |
/workspace/coverage/default/0.rom_e2e_static_critical.466103055 |
|
|
Jul 21 07:36:03 PM PDT 24 |
Jul 21 09:08:25 PM PDT 24 |
16996250214 ps |
| T371 |
/workspace/coverage/default/81.chip_sw_all_escalation_resets.2511582679 |
|
|
Jul 21 08:01:49 PM PDT 24 |
Jul 21 08:10:50 PM PDT 24 |
5523986152 ps |
| T973 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.936050701 |
|
|
Jul 21 07:45:13 PM PDT 24 |
Jul 21 07:54:08 PM PDT 24 |
6624894760 ps |
| T26 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.971177493 |
|
|
Jul 21 07:30:13 PM PDT 24 |
Jul 21 07:42:36 PM PDT 24 |
4748772153 ps |
| T325 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.2668922826 |
|
|
Jul 21 07:40:43 PM PDT 24 |
Jul 21 07:57:12 PM PDT 24 |
5922392350 ps |
| T193 |
/workspace/coverage/default/1.chip_sw_inject_scramble_seed.3628680868 |
|
|
Jul 21 07:31:41 PM PDT 24 |
Jul 21 10:52:07 PM PDT 24 |
64338748720 ps |
| T398 |
/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3259489429 |
|
|
Jul 21 07:46:47 PM PDT 24 |
Jul 21 07:59:09 PM PDT 24 |
5514392867 ps |
| T129 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2341583476 |
|
|
Jul 21 07:52:22 PM PDT 24 |
Jul 21 08:06:55 PM PDT 24 |
5361385146 ps |
| T31 |
/workspace/coverage/default/0.chip_sw_usbdev_config_host.4152790076 |
|
|
Jul 21 07:29:28 PM PDT 24 |
Jul 21 08:04:38 PM PDT 24 |
7659345356 ps |
| T80 |
/workspace/coverage/default/1.chip_jtag_mem_access.719105818 |
|
|
Jul 21 07:31:15 PM PDT 24 |
Jul 21 08:00:19 PM PDT 24 |
14117793160 ps |
| T974 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.3017331941 |
|
|
Jul 21 07:40:25 PM PDT 24 |
Jul 21 09:42:29 PM PDT 24 |
28544709928 ps |
| T975 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3556230830 |
|
|
Jul 21 07:33:25 PM PDT 24 |
Jul 21 07:53:01 PM PDT 24 |
6277638920 ps |
| T976 |
/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.3887243702 |
|
|
Jul 21 07:55:26 PM PDT 24 |
Jul 21 08:55:24 PM PDT 24 |
14969197784 ps |
| T977 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2043748168 |
|
|
Jul 21 07:53:25 PM PDT 24 |
Jul 21 08:12:20 PM PDT 24 |
10228054529 ps |
| T449 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3772229176 |
|
|
Jul 21 07:34:45 PM PDT 24 |
Jul 21 07:50:26 PM PDT 24 |
6999560144 ps |
| T229 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.177834629 |
|
|
Jul 21 07:36:35 PM PDT 24 |
Jul 21 09:08:18 PM PDT 24 |
47571010086 ps |
| T978 |
/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.2550506181 |
|
|
Jul 21 07:36:21 PM PDT 24 |
Jul 21 07:42:29 PM PDT 24 |
6790139360 ps |
| T7 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3303878469 |
|
|
Jul 21 07:50:31 PM PDT 24 |
Jul 21 07:56:53 PM PDT 24 |
4245869952 ps |
| T160 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.1811943610 |
|
|
Jul 21 07:49:26 PM PDT 24 |
Jul 21 07:56:33 PM PDT 24 |
4529083080 ps |
| T270 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.4012127198 |
|
|
Jul 21 07:37:23 PM PDT 24 |
Jul 21 08:45:15 PM PDT 24 |
14831558136 ps |
| T255 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_rma.544443158 |
|
|
Jul 21 07:34:12 PM PDT 24 |
Jul 21 08:11:38 PM PDT 24 |
27766945860 ps |
| T435 |
/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.1113026261 |
|
|
Jul 21 07:55:30 PM PDT 24 |
Jul 21 08:04:22 PM PDT 24 |
3970064730 ps |
| T126 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.472470418 |
|
|
Jul 21 07:48:04 PM PDT 24 |
Jul 21 08:03:13 PM PDT 24 |
6424086780 ps |
| T327 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1201863116 |
|
|
Jul 21 07:30:26 PM PDT 24 |
Jul 21 07:47:34 PM PDT 24 |
5765211472 ps |
| T436 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.2057117474 |
|
|
Jul 21 07:53:28 PM PDT 24 |
Jul 21 08:39:33 PM PDT 24 |
13065311358 ps |
| T322 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.1308889159 |
|
|
Jul 21 07:49:58 PM PDT 24 |
Jul 21 08:03:50 PM PDT 24 |
4630610386 ps |
| T437 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.1779050701 |
|
|
Jul 21 07:35:15 PM PDT 24 |
Jul 21 07:41:55 PM PDT 24 |
2903883045 ps |
| T758 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.379623746 |
|
|
Jul 21 07:57:46 PM PDT 24 |
Jul 21 08:13:22 PM PDT 24 |
6606091340 ps |
| T711 |
/workspace/coverage/default/6.chip_sw_all_escalation_resets.1908140269 |
|
|
Jul 21 07:55:22 PM PDT 24 |
Jul 21 08:08:47 PM PDT 24 |
4283698230 ps |
| T979 |
/workspace/coverage/default/0.chip_sw_uart_smoketest.1950551028 |
|
|
Jul 21 07:35:18 PM PDT 24 |
Jul 21 07:40:38 PM PDT 24 |
3063832766 ps |
| T168 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2133437236 |
|
|
Jul 21 07:30:16 PM PDT 24 |
Jul 21 07:33:14 PM PDT 24 |
3263197633 ps |
| T980 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod.947970521 |
|
|
Jul 21 07:45:11 PM PDT 24 |
Jul 21 08:55:46 PM PDT 24 |
16067272395 ps |
| T981 |
/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1875075453 |
|
|
Jul 21 07:51:28 PM PDT 24 |
Jul 21 07:55:42 PM PDT 24 |
2241528490 ps |
| T982 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.4170422476 |
|
|
Jul 21 07:35:09 PM PDT 24 |
Jul 21 08:15:11 PM PDT 24 |
28982139368 ps |
| T356 |
/workspace/coverage/default/1.chip_sw_pattgen_ios.3045807638 |
|
|
Jul 21 07:35:00 PM PDT 24 |
Jul 21 07:40:51 PM PDT 24 |
3606874350 ps |
| T983 |
/workspace/coverage/default/0.chip_sw_edn_sw_mode.8096484 |
|
|
Jul 21 07:31:21 PM PDT 24 |
Jul 21 07:53:20 PM PDT 24 |
6792508744 ps |
| T230 |
/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.2526367904 |
|
|
Jul 21 07:40:33 PM PDT 24 |
Jul 21 08:15:28 PM PDT 24 |
20041855670 ps |
| T984 |
/workspace/coverage/default/0.chip_sw_otbn_smoketest.2772912265 |
|
|
Jul 21 07:35:13 PM PDT 24 |
Jul 21 07:53:35 PM PDT 24 |
5468033420 ps |
| T763 |
/workspace/coverage/default/2.chip_sw_ast_clk_outputs.3522161250 |
|
|
Jul 21 07:48:54 PM PDT 24 |
Jul 21 08:03:47 PM PDT 24 |
7099300192 ps |
| T777 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3918664598 |
|
|
Jul 21 08:01:11 PM PDT 24 |
Jul 21 08:09:43 PM PDT 24 |
4020537418 ps |
| T985 |
/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.838505791 |
|
|
Jul 21 07:52:27 PM PDT 24 |
Jul 21 07:56:27 PM PDT 24 |
2268369108 ps |
| T986 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.937886341 |
|
|
Jul 21 07:37:30 PM PDT 24 |
Jul 21 09:22:54 PM PDT 24 |
23412026796 ps |
| T987 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3866373579 |
|
|
Jul 21 07:31:51 PM PDT 24 |
Jul 21 07:35:01 PM PDT 24 |
3096524806 ps |
| T279 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.1446408895 |
|
|
Jul 21 07:32:01 PM PDT 24 |
Jul 21 07:40:15 PM PDT 24 |
3185638088 ps |
| T988 |
/workspace/coverage/default/1.chip_sw_hmac_multistream.3740020432 |
|
|
Jul 21 07:36:06 PM PDT 24 |
Jul 21 08:01:28 PM PDT 24 |
7053628984 ps |
| T989 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.4136843500 |
|
|
Jul 21 07:51:48 PM PDT 24 |
Jul 21 08:02:15 PM PDT 24 |
4367347534 ps |
| T171 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3607117787 |
|
|
Jul 21 07:50:20 PM PDT 24 |
Jul 21 08:03:29 PM PDT 24 |
4896223765 ps |
| T990 |
/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.3976739845 |
|
|
Jul 21 07:53:07 PM PDT 24 |
Jul 21 08:50:25 PM PDT 24 |
15712494408 ps |
| T991 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.3198847151 |
|
|
Jul 21 07:54:45 PM PDT 24 |
Jul 21 09:06:09 PM PDT 24 |
15382389240 ps |
| T341 |
/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.158270941 |
|
|
Jul 21 07:46:34 PM PDT 24 |
Jul 21 07:56:47 PM PDT 24 |
4356545332 ps |
| T992 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2053950369 |
|
|
Jul 21 07:32:37 PM PDT 24 |
Jul 21 07:39:53 PM PDT 24 |
2960028112 ps |
| T993 |
/workspace/coverage/default/4.chip_tap_straps_testunlock0.1075718084 |
|
|
Jul 21 07:52:45 PM PDT 24 |
Jul 21 07:57:05 PM PDT 24 |
3597972943 ps |
| T994 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.974658092 |
|
|
Jul 21 07:49:20 PM PDT 24 |
Jul 21 08:01:03 PM PDT 24 |
4980976490 ps |
| T995 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.308982286 |
|
|
Jul 21 07:40:12 PM PDT 24 |
Jul 21 08:42:09 PM PDT 24 |
14789634570 ps |
| T996 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.1162745414 |
|
|
Jul 21 07:43:17 PM PDT 24 |
Jul 21 07:54:40 PM PDT 24 |
4091728740 ps |
| T155 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2621768653 |
|
|
Jul 21 07:44:35 PM PDT 24 |
Jul 21 07:46:38 PM PDT 24 |
2156931382 ps |
| T99 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.147568157 |
|
|
Jul 21 07:32:41 PM PDT 24 |
Jul 21 07:39:45 PM PDT 24 |
7522779590 ps |
| T997 |
/workspace/coverage/default/2.chip_sw_aes_entropy.3057616809 |
|
|
Jul 21 07:46:23 PM PDT 24 |
Jul 21 07:50:55 PM PDT 24 |
3020919120 ps |
| T446 |
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2451546874 |
|
|
Jul 21 07:59:02 PM PDT 24 |
Jul 21 08:05:02 PM PDT 24 |
3296973738 ps |
| T998 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2088202652 |
|
|
Jul 21 07:48:22 PM PDT 24 |
Jul 21 08:00:58 PM PDT 24 |
3963187144 ps |
| T999 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.2063262170 |
|
|
Jul 21 07:45:52 PM PDT 24 |
Jul 21 08:16:45 PM PDT 24 |
7850321610 ps |
| T242 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.598862827 |
|
|
Jul 21 07:40:09 PM PDT 24 |
Jul 21 07:51:44 PM PDT 24 |
4820092634 ps |
| T720 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1746338923 |
|
|
Jul 21 07:45:32 PM PDT 24 |
Jul 21 07:47:23 PM PDT 24 |
2466673862 ps |
| T350 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.821250588 |
|
|
Jul 21 07:29:47 PM PDT 24 |
Jul 21 07:41:32 PM PDT 24 |
3947134529 ps |
| T1000 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3339883432 |
|
|
Jul 21 07:40:19 PM PDT 24 |
Jul 21 07:46:24 PM PDT 24 |
4441606360 ps |
| T332 |
/workspace/coverage/default/1.chip_sw_entropy_src_csrng.46717062 |
|
|
Jul 21 07:36:22 PM PDT 24 |
Jul 21 08:06:27 PM PDT 24 |
7016575572 ps |
| T1001 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1033910326 |
|
|
Jul 21 07:45:06 PM PDT 24 |
Jul 21 07:52:33 PM PDT 24 |
3466056128 ps |
| T768 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1095481019 |
|
|
Jul 21 08:04:13 PM PDT 24 |
Jul 21 08:12:59 PM PDT 24 |
3752085140 ps |
| T1002 |
/workspace/coverage/default/1.chip_sw_ast_clk_outputs.4231145473 |
|
|
Jul 21 07:38:39 PM PDT 24 |
Jul 21 07:58:18 PM PDT 24 |
8137422588 ps |
| T826 |
/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3330951453 |
|
|
Jul 21 08:04:19 PM PDT 24 |
Jul 21 08:11:38 PM PDT 24 |
3976412336 ps |
| T1003 |
/workspace/coverage/default/2.rom_e2e_asm_init_dev.496580875 |
|
|
Jul 21 07:55:40 PM PDT 24 |
Jul 21 08:59:18 PM PDT 24 |
16062920568 ps |
| T34 |
/workspace/coverage/default/1.chip_sw_gpio.747217713 |
|
|
Jul 21 07:33:31 PM PDT 24 |
Jul 21 07:42:16 PM PDT 24 |
3415261740 ps |
| T1004 |
/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3618195921 |
|
|
Jul 21 07:30:22 PM PDT 24 |
Jul 21 07:37:51 PM PDT 24 |
5189344404 ps |
| T1005 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod.1785047200 |
|
|
Jul 21 07:36:04 PM PDT 24 |
Jul 21 08:46:59 PM PDT 24 |
15691733160 ps |
| T368 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3737653856 |
|
|
Jul 21 07:40:31 PM PDT 24 |
Jul 21 07:52:35 PM PDT 24 |
4713001215 ps |
| T1006 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.3539563759 |
|
|
Jul 21 07:42:47 PM PDT 24 |
Jul 21 08:23:26 PM PDT 24 |
9520679160 ps |
| T1007 |
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.1759687934 |
|
|
Jul 21 07:53:04 PM PDT 24 |
Jul 21 08:02:55 PM PDT 24 |
6347859966 ps |
| T251 |
/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1033671342 |
|
|
Jul 21 07:30:41 PM PDT 24 |
Jul 21 07:34:24 PM PDT 24 |
2874564644 ps |
| T333 |
/workspace/coverage/default/2.chip_sw_entropy_src_csrng.2383098929 |
|
|
Jul 21 07:51:29 PM PDT 24 |
Jul 21 08:15:24 PM PDT 24 |
6590102454 ps |
| T1008 |
/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.2890173959 |
|
|
Jul 21 07:54:46 PM PDT 24 |
Jul 21 08:14:25 PM PDT 24 |
10803023765 ps |
| T1009 |
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.4033841376 |
|
|
Jul 21 07:53:28 PM PDT 24 |
Jul 21 08:05:48 PM PDT 24 |
4773041514 ps |
| T1010 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.2638946822 |
|
|
Jul 21 07:44:39 PM PDT 24 |
Jul 21 08:01:34 PM PDT 24 |
6021056815 ps |
| T1011 |
/workspace/coverage/default/2.chip_sw_example_concurrency.1786390126 |
|
|
Jul 21 07:42:33 PM PDT 24 |
Jul 21 07:46:50 PM PDT 24 |
2649905468 ps |
| T778 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.4057303630 |
|
|
Jul 21 08:00:58 PM PDT 24 |
Jul 21 08:08:04 PM PDT 24 |
4018034528 ps |
| T1012 |
/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.201242530 |
|
|
Jul 21 08:00:00 PM PDT 24 |
Jul 21 08:07:06 PM PDT 24 |
3322149800 ps |
| T1013 |
/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2631847838 |
|
|
Jul 21 07:30:35 PM PDT 24 |
Jul 21 07:36:41 PM PDT 24 |
6375276020 ps |
| T1014 |
/workspace/coverage/default/0.chip_sw_otbn_randomness.3819042037 |
|
|
Jul 21 07:33:22 PM PDT 24 |
Jul 21 07:48:38 PM PDT 24 |
6190110544 ps |
| T247 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.4011939207 |
|
|
Jul 21 07:33:35 PM PDT 24 |
Jul 21 07:38:46 PM PDT 24 |
2659468674 ps |
| T1015 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2741636788 |
|
|
Jul 21 07:46:22 PM PDT 24 |
Jul 21 08:01:12 PM PDT 24 |
4441568170 ps |
| T84 |
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1079136495 |
|
|
Jul 21 07:59:58 PM PDT 24 |
Jul 21 08:07:22 PM PDT 24 |
3721548100 ps |
| T15 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.2372090535 |
|
|
Jul 21 07:31:24 PM PDT 24 |
Jul 21 07:35:59 PM PDT 24 |
3083461694 ps |
| T91 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.894514103 |
|
|
Jul 21 07:54:02 PM PDT 24 |
Jul 21 08:04:56 PM PDT 24 |
5285811812 ps |
| T92 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.2337978752 |
|
|
Jul 21 07:30:03 PM PDT 24 |
Jul 21 07:56:09 PM PDT 24 |
9055906094 ps |
| T93 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.2766485863 |
|
|
Jul 21 07:31:31 PM PDT 24 |
Jul 21 07:42:16 PM PDT 24 |
3336658600 ps |
| T94 |
/workspace/coverage/default/1.rom_e2e_asm_init_dev.1235752988 |
|
|
Jul 21 07:45:46 PM PDT 24 |
Jul 21 08:47:58 PM PDT 24 |
15681869927 ps |
| T95 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.3347952409 |
|
|
Jul 21 07:37:34 PM PDT 24 |
Jul 21 07:54:47 PM PDT 24 |
5601674904 ps |
| T96 |
/workspace/coverage/default/2.chip_tap_straps_prod.3982703968 |
|
|
Jul 21 07:48:59 PM PDT 24 |
Jul 21 07:51:18 PM PDT 24 |
3001859209 ps |
| T97 |
/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1956791389 |
|
|
Jul 21 07:48:26 PM PDT 24 |
Jul 21 08:01:51 PM PDT 24 |
7872118271 ps |
| T14 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.395751531 |
|
|
Jul 21 07:42:50 PM PDT 24 |
Jul 21 07:50:50 PM PDT 24 |
6336448740 ps |
| T423 |
/workspace/coverage/default/1.chip_sw_power_idle_load.721773231 |
|
|
Jul 21 07:41:27 PM PDT 24 |
Jul 21 07:52:09 PM PDT 24 |
4042270114 ps |
| T345 |
/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.453562847 |
|
|
Jul 21 07:39:13 PM PDT 24 |
Jul 21 07:45:29 PM PDT 24 |
3221299444 ps |
| T424 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.149371898 |
|
|
Jul 21 07:31:15 PM PDT 24 |
Jul 21 07:50:27 PM PDT 24 |
7625335280 ps |
| T425 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.2023329179 |
|
|
Jul 21 07:44:51 PM PDT 24 |
Jul 21 08:49:34 PM PDT 24 |
15445925856 ps |
| T362 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.2195880899 |
|
|
Jul 21 07:57:22 PM PDT 24 |
Jul 21 08:08:28 PM PDT 24 |
4767668900 ps |
| T426 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2687320416 |
|
|
Jul 21 07:34:25 PM PDT 24 |
Jul 21 07:36:08 PM PDT 24 |
1768996388 ps |
| T427 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.2931048607 |
|
|
Jul 21 07:59:58 PM PDT 24 |
Jul 21 08:10:31 PM PDT 24 |
4917127006 ps |
| T136 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2101839580 |
|
|
Jul 21 07:46:06 PM PDT 24 |
Jul 21 07:55:20 PM PDT 24 |
6318078230 ps |
| T304 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.1035736904 |
|
|
Jul 21 08:01:50 PM PDT 24 |
Jul 21 08:11:49 PM PDT 24 |
5598994378 ps |
| T1016 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.757667722 |
|
|
Jul 21 07:30:06 PM PDT 24 |
Jul 21 07:40:36 PM PDT 24 |
4919201350 ps |
| T1017 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter.107736751 |
|
|
Jul 21 07:34:28 PM PDT 24 |
Jul 21 07:38:22 PM PDT 24 |
3209729332 ps |
| T271 |
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.2165620867 |
|
|
Jul 21 07:53:39 PM PDT 24 |
Jul 21 08:07:50 PM PDT 24 |
5680386360 ps |
| T194 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2202018698 |
|
|
Jul 21 07:43:15 PM PDT 24 |
Jul 21 11:34:09 PM PDT 24 |
79225832654 ps |
| T273 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3681056076 |
|
|
Jul 21 07:31:49 PM PDT 24 |
Jul 21 07:52:57 PM PDT 24 |
7959305162 ps |
| T274 |
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.424011790 |
|
|
Jul 21 07:57:11 PM PDT 24 |
Jul 21 08:03:51 PM PDT 24 |
4192430440 ps |
| T275 |
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3851498984 |
|
|
Jul 21 07:53:25 PM PDT 24 |
Jul 21 08:07:20 PM PDT 24 |
11924034655 ps |
| T276 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.2829886429 |
|
|
Jul 21 07:34:39 PM PDT 24 |
Jul 21 07:38:31 PM PDT 24 |
2999329672 ps |
| T277 |
/workspace/coverage/default/86.chip_sw_all_escalation_resets.2690934839 |
|
|
Jul 21 08:01:42 PM PDT 24 |
Jul 21 08:10:05 PM PDT 24 |
5098515834 ps |
| T146 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.1821943701 |
|
|
Jul 21 07:40:27 PM PDT 24 |
Jul 21 07:51:15 PM PDT 24 |
4009335724 ps |
| T8 |
/workspace/coverage/default/2.chip_jtag_csr_rw.4231856950 |
|
|
Jul 21 07:41:48 PM PDT 24 |
Jul 21 08:21:47 PM PDT 24 |
20970093548 ps |
| T238 |
/workspace/coverage/default/93.chip_sw_all_escalation_resets.2382297579 |
|
|
Jul 21 08:02:15 PM PDT 24 |
Jul 21 08:10:14 PM PDT 24 |
4977329268 ps |
| T419 |
/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.4063752286 |
|
|
Jul 21 07:32:46 PM PDT 24 |
Jul 21 07:40:20 PM PDT 24 |
5427321420 ps |
| T420 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.331539663 |
|
|
Jul 21 07:32:22 PM PDT 24 |
Jul 21 07:46:32 PM PDT 24 |
5382477052 ps |
| T110 |
/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.3412040102 |
|
|
Jul 21 07:51:23 PM PDT 24 |
Jul 21 08:52:43 PM PDT 24 |
25387933182 ps |
| T81 |
/workspace/coverage/default/0.chip_jtag_mem_access.713958140 |
|
|
Jul 21 07:22:37 PM PDT 24 |
Jul 21 07:43:13 PM PDT 24 |
13817879195 ps |
| T90 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.152514780 |
|
|
Jul 21 08:00:51 PM PDT 24 |
Jul 21 08:11:15 PM PDT 24 |
4516154960 ps |
| T421 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.851860060 |
|
|
Jul 21 07:48:55 PM PDT 24 |
Jul 21 08:00:21 PM PDT 24 |
8186693484 ps |
| T422 |
/workspace/coverage/default/91.chip_sw_all_escalation_resets.530644439 |
|
|
Jul 21 08:03:58 PM PDT 24 |
Jul 21 08:13:58 PM PDT 24 |
4459007400 ps |
| T72 |
/workspace/coverage/default/0.chip_sw_usbdev_pullup.4129947386 |
|
|
Jul 21 07:31:19 PM PDT 24 |
Jul 21 07:36:52 PM PDT 24 |
3248318080 ps |
| T1018 |
/workspace/coverage/default/1.chip_sw_example_rom.1068475836 |
|
|
Jul 21 07:32:08 PM PDT 24 |
Jul 21 07:34:18 PM PDT 24 |
2407172002 ps |
| T1019 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4287265362 |
|
|
Jul 21 07:51:00 PM PDT 24 |
Jul 21 08:57:13 PM PDT 24 |
24803573256 ps |
| T1020 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2240765743 |
|
|
Jul 21 07:30:29 PM PDT 24 |
Jul 21 07:42:07 PM PDT 24 |
5688493808 ps |
| T1021 |
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2667555023 |
|
|
Jul 21 07:52:40 PM PDT 24 |
Jul 21 07:59:51 PM PDT 24 |
6033022106 ps |
| T85 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2680238015 |
|
|
Jul 21 07:47:45 PM PDT 24 |
Jul 21 08:13:26 PM PDT 24 |
13913443600 ps |
| T800 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.3729776464 |
|
|
Jul 21 07:56:35 PM PDT 24 |
Jul 21 08:08:06 PM PDT 24 |
4719867752 ps |
| T1022 |
/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.1043951038 |
|
|
Jul 21 07:41:47 PM PDT 24 |
Jul 21 07:51:37 PM PDT 24 |
3511889540 ps |
| T87 |
/workspace/coverage/default/2.chip_sw_gpio_smoketest.904653029 |
|
|
Jul 21 07:51:53 PM PDT 24 |
Jul 21 07:58:22 PM PDT 24 |
3195061055 ps |
| T1023 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.1633301388 |
|
|
Jul 21 07:32:07 PM PDT 24 |
Jul 21 07:35:50 PM PDT 24 |
2484978270 ps |
| T248 |
/workspace/coverage/default/1.chip_sw_plic_sw_irq.55190685 |
|
|
Jul 21 07:36:20 PM PDT 24 |
Jul 21 07:40:53 PM PDT 24 |
3015501100 ps |
| T721 |
/workspace/coverage/default/1.rom_volatile_raw_unlock.4133885021 |
|
|
Jul 21 07:43:24 PM PDT 24 |
Jul 21 07:45:29 PM PDT 24 |
3134559535 ps |
| T169 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3880140560 |
|
|
Jul 21 07:44:04 PM PDT 24 |
Jul 21 07:46:57 PM PDT 24 |
2914777638 ps |
| T1024 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2794422602 |
|
|
Jul 21 07:35:06 PM PDT 24 |
Jul 21 07:58:30 PM PDT 24 |
13311835117 ps |
| T1025 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.1003127583 |
|
|
Jul 21 07:32:52 PM PDT 24 |
Jul 21 07:41:48 PM PDT 24 |
6926419160 ps |
| T1026 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.850375914 |
|
|
Jul 21 07:34:47 PM PDT 24 |
Jul 21 08:41:40 PM PDT 24 |
17836269430 ps |
| T764 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.3037788783 |
|
|
Jul 21 07:56:15 PM PDT 24 |
Jul 21 08:09:30 PM PDT 24 |
5261386720 ps |
| T1027 |
/workspace/coverage/default/0.chip_sw_alert_handler_entropy.1301852416 |
|
|
Jul 21 07:32:13 PM PDT 24 |
Jul 21 07:37:18 PM PDT 24 |
3030199436 ps |
| T1028 |
/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.779726838 |
|
|
Jul 21 07:30:20 PM PDT 24 |
Jul 21 07:54:19 PM PDT 24 |
11081702905 ps |
| T198 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2830715677 |
|
|
Jul 21 07:45:55 PM PDT 24 |
Jul 21 07:53:42 PM PDT 24 |
4145645887 ps |
| T1029 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3721358413 |
|
|
Jul 21 07:45:42 PM PDT 24 |
Jul 21 08:03:15 PM PDT 24 |
12040126909 ps |
| T199 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.1175998750 |
|
|
Jul 21 07:45:54 PM PDT 24 |
Jul 21 08:18:10 PM PDT 24 |
24545422408 ps |
| T280 |
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.119174720 |
|
|
Jul 21 07:53:48 PM PDT 24 |
Jul 21 08:05:01 PM PDT 24 |
4897930540 ps |
| T759 |
/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2369412463 |
|
|
Jul 21 07:31:07 PM PDT 24 |
Jul 21 07:43:05 PM PDT 24 |
5660570764 ps |
| T803 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1153889543 |
|
|
Jul 21 08:01:21 PM PDT 24 |
Jul 21 08:07:47 PM PDT 24 |
3585642672 ps |
| T450 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2543882091 |
|
|
Jul 21 07:35:27 PM PDT 24 |
Jul 21 07:55:02 PM PDT 24 |
6932011521 ps |
| T1030 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.935982310 |
|
|
Jul 21 07:37:49 PM PDT 24 |
Jul 21 07:49:12 PM PDT 24 |
4998540496 ps |
| T181 |
/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3241719499 |
|
|
Jul 21 07:32:21 PM PDT 24 |
Jul 21 07:38:13 PM PDT 24 |
3753439552 ps |
| T1031 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.2863929592 |
|
|
Jul 21 07:48:07 PM PDT 24 |
Jul 21 07:52:40 PM PDT 24 |
3136237390 ps |
| T716 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2376443865 |
|
|
Jul 21 07:33:25 PM PDT 24 |
Jul 21 07:45:42 PM PDT 24 |
5657714699 ps |
| T818 |
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.141973970 |
|
|
Jul 21 07:59:20 PM PDT 24 |
Jul 21 08:06:34 PM PDT 24 |
4104928888 ps |
| T1032 |
/workspace/coverage/default/0.chip_tap_straps_testunlock0.3661855234 |
|
|
Jul 21 07:29:46 PM PDT 24 |
Jul 21 07:34:05 PM PDT 24 |
2721619877 ps |
| T1033 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.284475733 |
|
|
Jul 21 07:33:21 PM PDT 24 |
Jul 21 08:34:07 PM PDT 24 |
18571327064 ps |
| T137 |
/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.461193405 |
|
|
Jul 21 07:35:00 PM PDT 24 |
Jul 21 07:44:02 PM PDT 24 |
8917543089 ps |
| T147 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.2396252080 |
|
|
Jul 21 07:49:30 PM PDT 24 |
Jul 21 07:58:24 PM PDT 24 |
3965321476 ps |
| T366 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.2593414791 |
|
|
Jul 21 07:34:53 PM PDT 24 |
Jul 21 07:41:44 PM PDT 24 |
3509067580 ps |
| T200 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.839022293 |
|
|
Jul 21 07:45:46 PM PDT 24 |
Jul 21 07:50:38 PM PDT 24 |
2527601822 ps |
| T792 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.278183186 |
|
|
Jul 21 07:59:29 PM PDT 24 |
Jul 21 08:11:19 PM PDT 24 |
5993452130 ps |
| T130 |
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.4153984968 |
|
|
Jul 21 07:57:08 PM PDT 24 |
Jul 21 08:11:04 PM PDT 24 |
5646016388 ps |
| T1034 |
/workspace/coverage/default/2.chip_sw_power_sleep_load.3099578211 |
|
|
Jul 21 07:50:21 PM PDT 24 |
Jul 21 08:00:02 PM PDT 24 |
9987063228 ps |
| T414 |
/workspace/coverage/default/2.chip_sw_kmac_app_rom.305141679 |
|
|
Jul 21 07:47:56 PM PDT 24 |
Jul 21 07:52:03 PM PDT 24 |
2868121324 ps |
| T1035 |
/workspace/coverage/default/2.chip_sw_aes_idle.3730801135 |
|
|
Jul 21 07:47:06 PM PDT 24 |
Jul 21 07:51:22 PM PDT 24 |
2883024680 ps |
| T331 |
/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.2675829679 |
|
|
Jul 21 07:44:45 PM PDT 24 |
Jul 21 08:12:47 PM PDT 24 |
10456271640 ps |
| T1036 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3826960889 |
|
|
Jul 21 07:32:07 PM PDT 24 |
Jul 21 07:42:05 PM PDT 24 |
3347300648 ps |
| T201 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2217776160 |
|
|
Jul 21 07:34:46 PM PDT 24 |
Jul 21 08:08:36 PM PDT 24 |
21216639416 ps |
| T1037 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3135975047 |
|
|
Jul 21 07:45:31 PM PDT 24 |
Jul 21 08:09:46 PM PDT 24 |
10722777885 ps |
| T1038 |
/workspace/coverage/default/0.chip_sw_example_flash.2649675217 |
|
|
Jul 21 07:30:09 PM PDT 24 |
Jul 21 07:34:35 PM PDT 24 |
2859128364 ps |
| T1039 |
/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.2904075595 |
|
|
Jul 21 08:03:11 PM PDT 24 |
Jul 21 08:44:38 PM PDT 24 |
13563081784 ps |
| T1040 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.1327344496 |
|
|
Jul 21 07:31:21 PM PDT 24 |
Jul 21 07:40:52 PM PDT 24 |
5085231732 ps |
| T62 |
/workspace/coverage/default/0.chip_sw_alert_test.3352261014 |
|
|
Jul 21 07:31:28 PM PDT 24 |
Jul 21 07:36:23 PM PDT 24 |
3446003268 ps |
| T1041 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.907492838 |
|
|
Jul 21 07:37:27 PM PDT 24 |
Jul 21 08:45:19 PM PDT 24 |
15933228574 ps |
| T1042 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3188093428 |
|
|
Jul 21 07:49:34 PM PDT 24 |
Jul 21 07:54:49 PM PDT 24 |
3144650494 ps |
| T821 |
/workspace/coverage/default/9.chip_sw_all_escalation_resets.3059485635 |
|
|
Jul 21 07:56:42 PM PDT 24 |
Jul 21 08:08:18 PM PDT 24 |
3788029232 ps |
| T1043 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.3671082668 |
|
|
Jul 21 07:39:23 PM PDT 24 |
Jul 21 08:11:16 PM PDT 24 |
8467914498 ps |
| T1044 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3967826631 |
|
|
Jul 21 07:53:10 PM PDT 24 |
Jul 21 08:01:41 PM PDT 24 |
7045510338 ps |
| T797 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.760936290 |
|
|
Jul 21 07:55:45 PM PDT 24 |
Jul 21 08:08:47 PM PDT 24 |
4753344948 ps |
| T1045 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.447151494 |
|
|
Jul 21 07:33:39 PM PDT 24 |
Jul 21 08:00:24 PM PDT 24 |
7406547784 ps |
| T723 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.4290921354 |
|
|
Jul 21 07:46:39 PM PDT 24 |
Jul 21 07:51:09 PM PDT 24 |
3631966430 ps |
| T157 |
/workspace/coverage/default/87.chip_sw_all_escalation_resets.1091562998 |
|
|
Jul 21 08:00:57 PM PDT 24 |
Jul 21 08:11:08 PM PDT 24 |
5599456400 ps |
| T1046 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.43453567 |
|
|
Jul 21 07:32:18 PM PDT 24 |
Jul 21 07:40:34 PM PDT 24 |
6121121632 ps |
| T1047 |
/workspace/coverage/default/2.chip_sw_kmac_idle.188815153 |
|
|
Jul 21 07:53:23 PM PDT 24 |
Jul 21 07:57:52 PM PDT 24 |
2430583824 ps |
| T779 |
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.4285751667 |
|
|
Jul 21 07:58:44 PM PDT 24 |
Jul 21 08:06:15 PM PDT 24 |
3571553584 ps |
| T1048 |
/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.2731129660 |
|
|
Jul 21 07:45:49 PM PDT 24 |
Jul 21 07:57:55 PM PDT 24 |
5360771048 ps |
| T1049 |
/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.415505511 |
|
|
Jul 21 07:33:51 PM PDT 24 |
Jul 21 07:39:39 PM PDT 24 |
3149589567 ps |
| T154 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2589432849 |
|
|
Jul 21 07:33:34 PM PDT 24 |
Jul 21 07:35:19 PM PDT 24 |
2259339353 ps |
| T1050 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.3403029768 |
|
|
Jul 21 07:45:01 PM PDT 24 |
Jul 21 08:43:01 PM PDT 24 |
14519708970 ps |
| T1051 |
/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.1147430546 |
|
|
Jul 21 07:53:06 PM PDT 24 |
Jul 21 08:00:37 PM PDT 24 |
3572249500 ps |
| T1052 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.3516934341 |
|
|
Jul 21 07:35:16 PM PDT 24 |
Jul 21 07:44:21 PM PDT 24 |
5321776489 ps |
| T816 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.1112696237 |
|
|
Jul 21 07:57:21 PM PDT 24 |
Jul 21 08:08:50 PM PDT 24 |
4787674348 ps |