| T790 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.1647446952 |
|
|
Jul 21 08:00:30 PM PDT 24 |
Jul 21 08:12:02 PM PDT 24 |
6153630872 ps |
| T1053 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.226076062 |
|
|
Jul 21 07:30:09 PM PDT 24 |
Jul 21 07:35:23 PM PDT 24 |
2883813818 ps |
| T1054 |
/workspace/coverage/default/0.chip_sw_hmac_multistream.3148796162 |
|
|
Jul 21 07:30:58 PM PDT 24 |
Jul 21 07:57:59 PM PDT 24 |
6516057188 ps |
| T1055 |
/workspace/coverage/default/1.chip_sw_example_concurrency.881902932 |
|
|
Jul 21 07:36:53 PM PDT 24 |
Jul 21 07:40:35 PM PDT 24 |
2704605176 ps |
| T791 |
/workspace/coverage/default/7.chip_sw_all_escalation_resets.1154338730 |
|
|
Jul 21 07:53:28 PM PDT 24 |
Jul 21 08:04:13 PM PDT 24 |
4485646486 ps |
| T52 |
/workspace/coverage/default/2.chip_sw_spi_device_tpm.2322677253 |
|
|
Jul 21 07:45:40 PM PDT 24 |
Jul 21 07:53:24 PM PDT 24 |
3421989765 ps |
| T202 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3792005284 |
|
|
Jul 21 07:30:04 PM PDT 24 |
Jul 21 07:34:01 PM PDT 24 |
2817198359 ps |
| T1056 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2011070092 |
|
|
Jul 21 07:32:37 PM PDT 24 |
Jul 21 07:41:55 PM PDT 24 |
5261129860 ps |
| T1057 |
/workspace/coverage/default/1.rom_e2e_smoke.2317296751 |
|
|
Jul 21 07:44:26 PM PDT 24 |
Jul 21 08:52:41 PM PDT 24 |
15140324636 ps |
| T1058 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3405068690 |
|
|
Jul 21 07:47:25 PM PDT 24 |
Jul 21 07:52:43 PM PDT 24 |
2972751844 ps |
| T703 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.2427064789 |
|
|
Jul 21 07:51:40 PM PDT 24 |
Jul 21 11:21:35 PM PDT 24 |
96897044706 ps |
| T44 |
/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2009704328 |
|
|
Jul 21 07:29:44 PM PDT 24 |
Jul 21 07:34:38 PM PDT 24 |
2476334840 ps |
| T1059 |
/workspace/coverage/default/1.chip_sw_uart_smoketest.970709226 |
|
|
Jul 21 07:43:40 PM PDT 24 |
Jul 21 07:48:04 PM PDT 24 |
3440661668 ps |
| T1060 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.491784127 |
|
|
Jul 21 07:34:31 PM PDT 24 |
Jul 21 07:47:37 PM PDT 24 |
4834764948 ps |
| T752 |
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.172589994 |
|
|
Jul 21 07:57:51 PM PDT 24 |
Jul 21 08:06:09 PM PDT 24 |
4136096000 ps |
| T793 |
/workspace/coverage/default/45.chip_sw_all_escalation_resets.711426412 |
|
|
Jul 21 07:57:37 PM PDT 24 |
Jul 21 08:08:22 PM PDT 24 |
4780955276 ps |
| T175 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.4190513528 |
|
|
Jul 21 07:31:19 PM PDT 24 |
Jul 21 07:35:30 PM PDT 24 |
2379979148 ps |
| T1061 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.957669108 |
|
|
Jul 21 07:35:02 PM PDT 24 |
Jul 21 07:46:03 PM PDT 24 |
5259035983 ps |
| T1062 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2981001961 |
|
|
Jul 21 07:36:49 PM PDT 24 |
Jul 21 08:41:44 PM PDT 24 |
13375151017 ps |
| T1063 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.2332803929 |
|
|
Jul 21 07:47:16 PM PDT 24 |
Jul 21 08:06:18 PM PDT 24 |
7557622690 ps |
| T363 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1856924863 |
|
|
Jul 21 07:35:57 PM PDT 24 |
Jul 21 07:47:19 PM PDT 24 |
19283494470 ps |
| T780 |
/workspace/coverage/default/74.chip_sw_all_escalation_resets.2728703642 |
|
|
Jul 21 08:00:33 PM PDT 24 |
Jul 21 08:12:00 PM PDT 24 |
5663732158 ps |
| T1064 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.1316940345 |
|
|
Jul 21 07:49:07 PM PDT 24 |
Jul 21 08:01:01 PM PDT 24 |
4348253990 ps |
| T1065 |
/workspace/coverage/default/2.chip_sw_edn_auto_mode.1293637469 |
|
|
Jul 21 07:49:44 PM PDT 24 |
Jul 21 08:07:53 PM PDT 24 |
4581292016 ps |
| T232 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2821016995 |
|
|
Jul 21 07:31:08 PM PDT 24 |
Jul 21 09:18:06 PM PDT 24 |
48073171790 ps |
| T1066 |
/workspace/coverage/default/1.chip_sw_gpio_smoketest.1578061101 |
|
|
Jul 21 07:41:53 PM PDT 24 |
Jul 21 07:46:58 PM PDT 24 |
2442753433 ps |
| T750 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.305381721 |
|
|
Jul 21 08:01:00 PM PDT 24 |
Jul 21 08:17:24 PM PDT 24 |
5609265528 ps |
| T698 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.1167716543 |
|
|
Jul 21 07:31:10 PM PDT 24 |
Jul 21 07:38:34 PM PDT 24 |
2774335734 ps |
| T832 |
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.102193753 |
|
|
Jul 21 07:56:14 PM PDT 24 |
Jul 21 08:05:11 PM PDT 24 |
3273565160 ps |
| T1067 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.3313529511 |
|
|
Jul 21 07:29:35 PM PDT 24 |
Jul 21 07:35:15 PM PDT 24 |
3919690596 ps |
| T1068 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1356537462 |
|
|
Jul 21 07:41:49 PM PDT 24 |
Jul 21 07:45:14 PM PDT 24 |
2797800474 ps |
| T32 |
/workspace/coverage/default/0.chip_sw_usbdev_setuprx.3709689295 |
|
|
Jul 21 07:28:48 PM PDT 24 |
Jul 21 07:40:09 PM PDT 24 |
4459673584 ps |
| T1069 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3726412212 |
|
|
Jul 21 07:48:18 PM PDT 24 |
Jul 21 08:26:20 PM PDT 24 |
8997538360 ps |
| T1070 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1344525934 |
|
|
Jul 21 07:38:26 PM PDT 24 |
Jul 21 07:52:37 PM PDT 24 |
7372859088 ps |
| T100 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2339887756 |
|
|
Jul 21 07:39:56 PM PDT 24 |
Jul 21 07:47:02 PM PDT 24 |
7163322560 ps |
| T1071 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.172956406 |
|
|
Jul 21 07:44:12 PM PDT 24 |
Jul 21 07:54:18 PM PDT 24 |
5524249506 ps |
| T1072 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3470138758 |
|
|
Jul 21 07:35:30 PM PDT 24 |
Jul 21 07:46:15 PM PDT 24 |
7432120296 ps |
| T215 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3768692138 |
|
|
Jul 21 07:45:36 PM PDT 24 |
Jul 21 08:41:38 PM PDT 24 |
20335124770 ps |
| T1073 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.1713663379 |
|
|
Jul 21 07:37:12 PM PDT 24 |
Jul 21 08:39:01 PM PDT 24 |
15342468364 ps |
| T401 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1081631149 |
|
|
Jul 21 07:37:52 PM PDT 24 |
Jul 21 09:33:40 PM PDT 24 |
24022921092 ps |
| T1074 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3160049977 |
|
|
Jul 21 07:51:34 PM PDT 24 |
Jul 21 08:11:09 PM PDT 24 |
7061027866 ps |
| T1075 |
/workspace/coverage/default/1.chip_sw_kmac_idle.2088788120 |
|
|
Jul 21 07:37:06 PM PDT 24 |
Jul 21 07:41:02 PM PDT 24 |
2439582000 ps |
| T342 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.29429226 |
|
|
Jul 21 07:46:19 PM PDT 24 |
Jul 21 08:01:17 PM PDT 24 |
5350259110 ps |
| T1076 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.447504512 |
|
|
Jul 21 07:40:22 PM PDT 24 |
Jul 21 07:45:17 PM PDT 24 |
2644998865 ps |
| T1077 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.552558620 |
|
|
Jul 21 07:43:22 PM PDT 24 |
Jul 21 08:03:09 PM PDT 24 |
7573739752 ps |
| T1078 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1454756423 |
|
|
Jul 21 07:30:35 PM PDT 24 |
Jul 21 07:40:43 PM PDT 24 |
7802008778 ps |
| T805 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3700129095 |
|
|
Jul 21 07:30:31 PM PDT 24 |
Jul 21 07:37:16 PM PDT 24 |
4275243294 ps |
| T722 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.2482522649 |
|
|
Jul 21 07:34:59 PM PDT 24 |
Jul 21 07:37:58 PM PDT 24 |
3379405793 ps |
| T134 |
/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.2098867375 |
|
|
Jul 21 07:30:18 PM PDT 24 |
Jul 21 08:21:53 PM PDT 24 |
20415960542 ps |
| T176 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.309445942 |
|
|
Jul 21 07:39:18 PM PDT 24 |
Jul 21 07:42:31 PM PDT 24 |
3051251228 ps |
| T233 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3972471800 |
|
|
Jul 21 07:35:29 PM PDT 24 |
Jul 21 07:44:15 PM PDT 24 |
4393958080 ps |
| T195 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2116438323 |
|
|
Jul 21 07:43:19 PM PDT 24 |
Jul 21 10:35:16 PM PDT 24 |
58654589969 ps |
| T1079 |
/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.800561028 |
|
|
Jul 21 08:03:00 PM PDT 24 |
Jul 21 08:28:03 PM PDT 24 |
7686622680 ps |
| T1080 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1988951376 |
|
|
Jul 21 07:31:13 PM PDT 24 |
Jul 21 07:43:55 PM PDT 24 |
4075518758 ps |
| T765 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.194024320 |
|
|
Jul 21 08:03:01 PM PDT 24 |
Jul 21 08:15:04 PM PDT 24 |
4829538644 ps |
| T1081 |
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2843825860 |
|
|
Jul 21 07:53:41 PM PDT 24 |
Jul 21 09:33:50 PM PDT 24 |
23975725602 ps |
| T1082 |
/workspace/coverage/default/51.chip_sw_all_escalation_resets.54476309 |
|
|
Jul 21 07:58:30 PM PDT 24 |
Jul 21 08:08:43 PM PDT 24 |
5615004460 ps |
| T807 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.3798830940 |
|
|
Jul 21 08:04:33 PM PDT 24 |
Jul 21 08:18:05 PM PDT 24 |
4851055354 ps |
| T1083 |
/workspace/coverage/default/0.rom_e2e_asm_init_rma.422196840 |
|
|
Jul 21 07:38:47 PM PDT 24 |
Jul 21 08:53:11 PM PDT 24 |
14863206287 ps |
| T1084 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1386968840 |
|
|
Jul 21 07:29:39 PM PDT 24 |
Jul 21 08:04:17 PM PDT 24 |
31226723836 ps |
| T239 |
/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.428583429 |
|
|
Jul 21 07:36:15 PM PDT 24 |
Jul 21 07:47:52 PM PDT 24 |
6571794408 ps |
| T1085 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2811796426 |
|
|
Jul 21 07:44:41 PM PDT 24 |
Jul 21 07:58:42 PM PDT 24 |
4992730070 ps |
| T700 |
/workspace/coverage/default/2.chip_sw_edn_boot_mode.3108887240 |
|
|
Jul 21 07:46:17 PM PDT 24 |
Jul 21 07:57:19 PM PDT 24 |
2924112190 ps |
| T1086 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.2531631885 |
|
|
Jul 21 08:01:18 PM PDT 24 |
Jul 21 08:12:42 PM PDT 24 |
5954626194 ps |
| T1087 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1062483992 |
|
|
Jul 21 07:42:03 PM PDT 24 |
Jul 21 07:47:03 PM PDT 24 |
3536554440 ps |
| T1088 |
/workspace/coverage/default/2.chip_tap_straps_rma.3917738421 |
|
|
Jul 21 07:49:31 PM PDT 24 |
Jul 21 07:57:08 PM PDT 24 |
4827707607 ps |
| T751 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3179266597 |
|
|
Jul 21 07:58:15 PM PDT 24 |
Jul 21 08:06:19 PM PDT 24 |
3459876070 ps |
| T281 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.508127526 |
|
|
Jul 21 07:49:32 PM PDT 24 |
Jul 21 07:59:27 PM PDT 24 |
5394770128 ps |
| T755 |
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.278515350 |
|
|
Jul 21 07:52:46 PM PDT 24 |
Jul 21 08:00:02 PM PDT 24 |
3900670706 ps |
| T1089 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2899891415 |
|
|
Jul 21 07:49:31 PM PDT 24 |
Jul 21 07:56:28 PM PDT 24 |
3776015930 ps |
| T372 |
/workspace/coverage/default/84.chip_sw_all_escalation_resets.3501365899 |
|
|
Jul 21 08:01:57 PM PDT 24 |
Jul 21 08:11:30 PM PDT 24 |
4494035496 ps |
| T1090 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.380379892 |
|
|
Jul 21 07:45:08 PM PDT 24 |
Jul 21 07:49:35 PM PDT 24 |
3356153042 ps |
| T1091 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.4126183883 |
|
|
Jul 21 07:37:50 PM PDT 24 |
Jul 21 09:10:12 PM PDT 24 |
47760060982 ps |
| T1092 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.2316669038 |
|
|
Jul 21 07:30:49 PM PDT 24 |
Jul 21 07:37:23 PM PDT 24 |
4583959816 ps |
| T1093 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1120902238 |
|
|
Jul 21 07:56:32 PM PDT 24 |
Jul 21 08:05:16 PM PDT 24 |
4455339646 ps |
| T535 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3919972475 |
|
|
Jul 21 07:46:02 PM PDT 24 |
Jul 21 08:01:46 PM PDT 24 |
4808101000 ps |
| T1094 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.3204590215 |
|
|
Jul 21 07:34:30 PM PDT 24 |
Jul 21 07:56:41 PM PDT 24 |
7765801000 ps |
| T1095 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.150665936 |
|
|
Jul 21 07:30:25 PM PDT 24 |
Jul 21 07:47:12 PM PDT 24 |
5804214680 ps |
| T761 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1224138209 |
|
|
Jul 21 07:57:29 PM PDT 24 |
Jul 21 08:03:41 PM PDT 24 |
3492297320 ps |
| T1096 |
/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.247052157 |
|
|
Jul 21 07:36:58 PM PDT 24 |
Jul 21 07:41:16 PM PDT 24 |
3280418456 ps |
| T1097 |
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.191682634 |
|
|
Jul 21 07:44:34 PM PDT 24 |
Jul 21 07:53:53 PM PDT 24 |
3503286158 ps |
| T21 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1722606060 |
|
|
Jul 21 07:42:33 PM PDT 24 |
Jul 21 07:48:46 PM PDT 24 |
3187457096 ps |
| T1098 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.3823979676 |
|
|
Jul 21 07:46:11 PM PDT 24 |
Jul 21 07:59:21 PM PDT 24 |
5506334260 ps |
| T746 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.339237534 |
|
|
Jul 21 08:01:52 PM PDT 24 |
Jul 21 08:09:24 PM PDT 24 |
4152345298 ps |
| T1099 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1955759393 |
|
|
Jul 21 07:56:19 PM PDT 24 |
Jul 21 08:02:40 PM PDT 24 |
3719911604 ps |
| T1100 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.3734136148 |
|
|
Jul 21 07:43:25 PM PDT 24 |
Jul 21 07:47:45 PM PDT 24 |
2843578180 ps |
| T1101 |
/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.3111386309 |
|
|
Jul 21 07:33:02 PM PDT 24 |
Jul 21 07:37:09 PM PDT 24 |
3230366320 ps |
| T86 |
/workspace/coverage/default/0.chip_jtag_csr_rw.411178698 |
|
|
Jul 21 07:22:32 PM PDT 24 |
Jul 21 08:02:42 PM PDT 24 |
20241484746 ps |
| T1102 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.1823787500 |
|
|
Jul 21 07:49:50 PM PDT 24 |
Jul 21 07:54:10 PM PDT 24 |
2736833247 ps |
| T282 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3446945822 |
|
|
Jul 21 07:37:04 PM PDT 24 |
Jul 21 07:50:37 PM PDT 24 |
5913908290 ps |
| T1103 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.1245986073 |
|
|
Jul 21 07:34:50 PM PDT 24 |
Jul 21 11:36:12 PM PDT 24 |
78985248475 ps |
| T1104 |
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1906836775 |
|
|
Jul 21 07:58:07 PM PDT 24 |
Jul 21 08:04:25 PM PDT 24 |
4185939944 ps |
| T1105 |
/workspace/coverage/default/3.chip_tap_straps_prod.549266908 |
|
|
Jul 21 07:51:30 PM PDT 24 |
Jul 21 07:55:06 PM PDT 24 |
2839952891 ps |
| T1106 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.2994684410 |
|
|
Jul 21 07:49:09 PM PDT 24 |
Jul 21 07:59:01 PM PDT 24 |
6698649000 ps |
| T1107 |
/workspace/coverage/default/2.chip_sw_flash_crash_alert.2365286008 |
|
|
Jul 21 07:51:37 PM PDT 24 |
Jul 21 08:05:55 PM PDT 24 |
6696341322 ps |
| T415 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1148406133 |
|
|
Jul 21 07:40:27 PM PDT 24 |
Jul 21 08:18:27 PM PDT 24 |
25673985504 ps |
| T823 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.2830900847 |
|
|
Jul 21 07:57:49 PM PDT 24 |
Jul 21 08:10:31 PM PDT 24 |
4914721816 ps |
| T1108 |
/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.3804083054 |
|
|
Jul 21 07:43:04 PM PDT 24 |
Jul 21 07:49:42 PM PDT 24 |
3589035600 ps |
| T1109 |
/workspace/coverage/default/2.chip_sw_otbn_randomness.658859043 |
|
|
Jul 21 07:45:46 PM PDT 24 |
Jul 21 08:01:02 PM PDT 24 |
5851952320 ps |
| T1110 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.465223848 |
|
|
Jul 21 07:37:35 PM PDT 24 |
Jul 21 09:00:09 PM PDT 24 |
15247507384 ps |
| T1111 |
/workspace/coverage/default/2.rom_keymgr_functest.886530962 |
|
|
Jul 21 07:51:30 PM PDT 24 |
Jul 21 07:58:32 PM PDT 24 |
3878418584 ps |
| T1112 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.1871119881 |
|
|
Jul 21 07:57:46 PM PDT 24 |
Jul 21 08:08:27 PM PDT 24 |
5629590452 ps |
| T794 |
/workspace/coverage/default/41.chip_sw_all_escalation_resets.4119870984 |
|
|
Jul 21 07:58:44 PM PDT 24 |
Jul 21 08:09:02 PM PDT 24 |
4419283872 ps |
| T1113 |
/workspace/coverage/default/1.chip_sw_csrng_smoketest.1751693342 |
|
|
Jul 21 07:42:06 PM PDT 24 |
Jul 21 07:45:41 PM PDT 24 |
2416520386 ps |
| T1114 |
/workspace/coverage/default/2.chip_sw_csrng_kat_test.3709384737 |
|
|
Jul 21 07:46:13 PM PDT 24 |
Jul 21 07:50:58 PM PDT 24 |
2857123952 ps |
| T1115 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.2119890633 |
|
|
Jul 21 07:38:58 PM PDT 24 |
Jul 21 08:26:46 PM PDT 24 |
10872841197 ps |
| T704 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3868431771 |
|
|
Jul 21 07:33:20 PM PDT 24 |
Jul 22 01:24:19 AM PDT 24 |
150416586370 ps |
| T775 |
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.4031827061 |
|
|
Jul 21 08:02:04 PM PDT 24 |
Jul 21 08:09:20 PM PDT 24 |
4120071664 ps |
| T831 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.3342906445 |
|
|
Jul 21 07:54:47 PM PDT 24 |
Jul 21 08:08:22 PM PDT 24 |
4377311760 ps |
| T1116 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access.981195847 |
|
|
Jul 21 07:34:23 PM PDT 24 |
Jul 21 07:52:09 PM PDT 24 |
6138689864 ps |
| T1117 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.4243577655 |
|
|
Jul 21 07:29:22 PM PDT 24 |
Jul 21 07:35:56 PM PDT 24 |
3903933992 ps |
| T1118 |
/workspace/coverage/default/0.chip_sw_aes_enc.1443728556 |
|
|
Jul 21 07:30:58 PM PDT 24 |
Jul 21 07:37:18 PM PDT 24 |
3329375056 ps |
| T1119 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.534107487 |
|
|
Jul 21 07:29:05 PM PDT 24 |
Jul 21 07:33:25 PM PDT 24 |
3211322402 ps |
| T1120 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.3440086701 |
|
|
Jul 21 07:46:31 PM PDT 24 |
Jul 21 07:58:02 PM PDT 24 |
4494985852 ps |
| T1121 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1582052765 |
|
|
Jul 21 07:37:36 PM PDT 24 |
Jul 21 07:42:37 PM PDT 24 |
3065606312 ps |
| T1122 |
/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.398018137 |
|
|
Jul 21 07:46:25 PM PDT 24 |
Jul 21 08:33:14 PM PDT 24 |
11257747883 ps |
| T1123 |
/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1827928705 |
|
|
Jul 21 07:55:13 PM PDT 24 |
Jul 21 07:58:16 PM PDT 24 |
2433793942 ps |
| T1124 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1578724936 |
|
|
Jul 21 07:36:56 PM PDT 24 |
Jul 21 08:03:54 PM PDT 24 |
8077695772 ps |
| T796 |
/workspace/coverage/default/70.chip_sw_all_escalation_resets.306818002 |
|
|
Jul 21 08:01:52 PM PDT 24 |
Jul 21 08:10:49 PM PDT 24 |
4875149720 ps |
| T776 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.2481860336 |
|
|
Jul 21 07:56:14 PM PDT 24 |
Jul 21 08:04:34 PM PDT 24 |
4604058700 ps |
| T228 |
/workspace/coverage/default/2.chip_sw_flash_init.2105029948 |
|
|
Jul 21 07:43:30 PM PDT 24 |
Jul 21 08:17:38 PM PDT 24 |
25350007081 ps |
| T1125 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2704636701 |
|
|
Jul 21 07:36:30 PM PDT 24 |
Jul 21 08:32:41 PM PDT 24 |
10994807320 ps |
| T354 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.4244412981 |
|
|
Jul 21 07:45:43 PM PDT 24 |
Jul 21 07:58:36 PM PDT 24 |
4019427736 ps |
| T1126 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3796838779 |
|
|
Jul 21 07:45:07 PM PDT 24 |
Jul 21 08:05:39 PM PDT 24 |
8409684864 ps |
| T1127 |
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2867675187 |
|
|
Jul 21 07:54:24 PM PDT 24 |
Jul 21 08:22:32 PM PDT 24 |
8761961354 ps |
| T753 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.94936853 |
|
|
Jul 21 07:55:16 PM PDT 24 |
Jul 21 08:04:25 PM PDT 24 |
4456797324 ps |
| T1128 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.2872368183 |
|
|
Jul 21 07:32:20 PM PDT 24 |
Jul 21 07:47:42 PM PDT 24 |
10281992374 ps |
| T813 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.3880772347 |
|
|
Jul 21 07:54:14 PM PDT 24 |
Jul 21 07:59:55 PM PDT 24 |
3591524264 ps |
| T804 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.4099863479 |
|
|
Jul 21 07:59:00 PM PDT 24 |
Jul 21 08:11:34 PM PDT 24 |
6118140184 ps |
| T1129 |
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3513822056 |
|
|
Jul 21 07:54:37 PM PDT 24 |
Jul 21 09:36:47 PM PDT 24 |
28074930600 ps |
| T1130 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.148683289 |
|
|
Jul 21 07:35:36 PM PDT 24 |
Jul 21 07:43:39 PM PDT 24 |
7517360468 ps |
| T1131 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2874007455 |
|
|
Jul 21 07:49:08 PM PDT 24 |
Jul 21 07:54:45 PM PDT 24 |
3323779464 ps |
| T439 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_dev.2970017066 |
|
|
Jul 21 07:34:25 PM PDT 24 |
Jul 21 08:21:54 PM PDT 24 |
27451951481 ps |
| T1132 |
/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1386879659 |
|
|
Jul 21 07:37:30 PM PDT 24 |
Jul 21 07:42:25 PM PDT 24 |
3452720840 ps |
| T817 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3584231387 |
|
|
Jul 21 07:35:41 PM PDT 24 |
Jul 21 07:42:07 PM PDT 24 |
3328042784 ps |
| T189 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3977339362 |
|
|
Jul 21 07:34:50 PM PDT 24 |
Jul 21 07:44:07 PM PDT 24 |
4328297394 ps |
| T306 |
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2763766206 |
|
|
Jul 21 07:59:43 PM PDT 24 |
Jul 21 08:06:43 PM PDT 24 |
3754791904 ps |
| T309 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.818208462 |
|
|
Jul 21 07:31:29 PM PDT 24 |
Jul 21 07:36:23 PM PDT 24 |
3651880389 ps |
| T310 |
/workspace/coverage/default/0.rom_keymgr_functest.3896451860 |
|
|
Jul 21 07:36:39 PM PDT 24 |
Jul 21 07:49:36 PM PDT 24 |
5465339788 ps |
| T311 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.192908366 |
|
|
Jul 21 07:42:06 PM PDT 24 |
Jul 21 07:52:06 PM PDT 24 |
5969763172 ps |
| T312 |
/workspace/coverage/default/1.chip_sw_csrng_kat_test.3182170360 |
|
|
Jul 21 07:35:59 PM PDT 24 |
Jul 21 07:40:02 PM PDT 24 |
3018521564 ps |
| T313 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2315672890 |
|
|
Jul 21 07:59:48 PM PDT 24 |
Jul 21 08:04:45 PM PDT 24 |
3653788288 ps |
| T314 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.1308225656 |
|
|
Jul 21 07:46:11 PM PDT 24 |
Jul 21 08:07:46 PM PDT 24 |
5601942920 ps |
| T315 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2420147552 |
|
|
Jul 21 07:59:48 PM PDT 24 |
Jul 21 08:07:42 PM PDT 24 |
3768109608 ps |
| T316 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.1147282441 |
|
|
Jul 21 07:44:04 PM PDT 24 |
Jul 21 08:02:05 PM PDT 24 |
6644351471 ps |
| T317 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2784105267 |
|
|
Jul 21 07:56:06 PM PDT 24 |
Jul 21 08:02:26 PM PDT 24 |
3585932100 ps |
| T367 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3642612180 |
|
|
Jul 21 07:50:39 PM PDT 24 |
Jul 21 07:59:06 PM PDT 24 |
5350370725 ps |
| T724 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3488755512 |
|
|
Jul 21 07:30:08 PM PDT 24 |
Jul 21 07:35:03 PM PDT 24 |
3639400328 ps |
| T1133 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.4126552366 |
|
|
Jul 21 07:35:36 PM PDT 24 |
Jul 21 07:40:05 PM PDT 24 |
3052373352 ps |
| T1134 |
/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.4114226324 |
|
|
Jul 21 07:51:51 PM PDT 24 |
Jul 21 07:59:30 PM PDT 24 |
6732998236 ps |
| T1135 |
/workspace/coverage/default/0.chip_sw_usbdev_stream.1999372466 |
|
|
Jul 21 07:29:19 PM PDT 24 |
Jul 21 08:52:51 PM PDT 24 |
19101818102 ps |
| T788 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1527777373 |
|
|
Jul 21 07:55:07 PM PDT 24 |
Jul 21 08:01:29 PM PDT 24 |
3996637820 ps |
| T1136 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3575203298 |
|
|
Jul 21 07:52:35 PM PDT 24 |
Jul 21 08:00:28 PM PDT 24 |
4262357462 ps |
| T1137 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.2620895312 |
|
|
Jul 21 07:30:32 PM PDT 24 |
Jul 21 07:47:36 PM PDT 24 |
4939078684 ps |
| T1138 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.4044823151 |
|
|
Jul 21 07:50:09 PM PDT 24 |
Jul 21 08:08:00 PM PDT 24 |
5474041934 ps |
| T701 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.1520141888 |
|
|
Jul 21 07:38:19 PM PDT 24 |
Jul 21 07:48:46 PM PDT 24 |
3033691878 ps |
| T1139 |
/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1947814659 |
|
|
Jul 21 07:30:59 PM PDT 24 |
Jul 21 07:35:17 PM PDT 24 |
2929518136 ps |
| T1140 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.685476545 |
|
|
Jul 21 07:36:05 PM PDT 24 |
Jul 21 08:50:07 PM PDT 24 |
14780177780 ps |
| T1141 |
/workspace/coverage/default/2.chip_sw_example_flash.3520824630 |
|
|
Jul 21 07:42:46 PM PDT 24 |
Jul 21 07:47:03 PM PDT 24 |
3505045818 ps |
| T1142 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1817617340 |
|
|
Jul 21 07:38:03 PM PDT 24 |
Jul 21 09:23:34 PM PDT 24 |
23383062027 ps |
| T1143 |
/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2192172478 |
|
|
Jul 21 07:45:32 PM PDT 24 |
Jul 21 08:56:12 PM PDT 24 |
14292217524 ps |
| T1144 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1749638375 |
|
|
Jul 21 07:34:56 PM PDT 24 |
Jul 21 07:58:23 PM PDT 24 |
8191889480 ps |
| T1145 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.970148214 |
|
|
Jul 21 07:36:26 PM PDT 24 |
Jul 21 08:11:51 PM PDT 24 |
8939586732 ps |
| T1146 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.3607764480 |
|
|
Jul 21 07:38:18 PM PDT 24 |
Jul 21 08:44:36 PM PDT 24 |
15390501462 ps |
| T1147 |
/workspace/coverage/default/2.chip_tap_straps_testunlock0.3402293660 |
|
|
Jul 21 07:48:24 PM PDT 24 |
Jul 21 08:00:22 PM PDT 24 |
6152462995 ps |
| T1148 |
/workspace/coverage/default/1.chip_sw_kmac_app_rom.3892391973 |
|
|
Jul 21 07:36:44 PM PDT 24 |
Jul 21 07:40:18 PM PDT 24 |
2836443444 ps |
| T192 |
/workspace/coverage/default/1.chip_jtag_csr_rw.1557201451 |
|
|
Jul 21 07:30:50 PM PDT 24 |
Jul 21 07:49:42 PM PDT 24 |
12392260977 ps |
| T283 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1488950865 |
|
|
Jul 21 07:32:46 PM PDT 24 |
Jul 21 07:44:00 PM PDT 24 |
5465851773 ps |
| T1149 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.636867687 |
|
|
Jul 21 07:36:56 PM PDT 24 |
Jul 21 09:15:07 PM PDT 24 |
23642627388 ps |
| T1150 |
/workspace/coverage/default/2.chip_sw_alert_handler_entropy.1192070471 |
|
|
Jul 21 07:46:48 PM PDT 24 |
Jul 21 07:50:54 PM PDT 24 |
3463721350 ps |
| T378 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.57692537 |
|
|
Jul 21 07:38:09 PM PDT 24 |
Jul 21 07:54:10 PM PDT 24 |
6224659932 ps |
| T1151 |
/workspace/coverage/default/2.rom_e2e_shutdown_output.722574328 |
|
|
Jul 21 07:54:58 PM PDT 24 |
Jul 21 09:01:49 PM PDT 24 |
23360960719 ps |
| T1152 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2598373472 |
|
|
Jul 21 07:36:11 PM PDT 24 |
Jul 21 07:44:50 PM PDT 24 |
7233676648 ps |
| T1153 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3298213047 |
|
|
Jul 21 07:39:51 PM PDT 24 |
Jul 21 09:00:05 PM PDT 24 |
14888487046 ps |
| T302 |
/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1623264007 |
|
|
Jul 21 07:37:59 PM PDT 24 |
Jul 21 07:45:18 PM PDT 24 |
5266642748 ps |
| T1154 |
/workspace/coverage/default/79.chip_sw_all_escalation_resets.221759422 |
|
|
Jul 21 08:01:46 PM PDT 24 |
Jul 21 08:11:59 PM PDT 24 |
4355581762 ps |
| T1155 |
/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.2775508268 |
|
|
Jul 21 07:55:45 PM PDT 24 |
Jul 21 08:20:38 PM PDT 24 |
7547156556 ps |
| T45 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1757311728 |
|
|
Jul 21 07:44:01 PM PDT 24 |
Jul 21 07:48:58 PM PDT 24 |
3110082638 ps |
| T12 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.2062629796 |
|
|
Jul 21 07:39:30 PM PDT 24 |
Jul 21 07:45:11 PM PDT 24 |
3349472440 ps |
| T1156 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1296038097 |
|
|
Jul 21 07:34:15 PM PDT 24 |
Jul 21 07:47:15 PM PDT 24 |
4263254634 ps |
| T828 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.82657703 |
|
|
Jul 21 07:53:33 PM PDT 24 |
Jul 21 07:59:57 PM PDT 24 |
4012393756 ps |
| T244 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.1859829809 |
|
|
Jul 21 07:29:53 PM PDT 24 |
Jul 21 07:41:06 PM PDT 24 |
4948208840 ps |
| T1157 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.3059013384 |
|
|
Jul 21 07:33:32 PM PDT 24 |
Jul 21 07:38:49 PM PDT 24 |
3491339614 ps |
| T785 |
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2378747866 |
|
|
Jul 21 07:59:07 PM PDT 24 |
Jul 21 08:05:38 PM PDT 24 |
3236861148 ps |
| T1158 |
/workspace/coverage/default/0.chip_sw_inject_scramble_seed.357552789 |
|
|
Jul 21 07:29:31 PM PDT 24 |
Jul 21 10:53:40 PM PDT 24 |
64321326571 ps |
| T1159 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1381907154 |
|
|
Jul 21 07:38:30 PM PDT 24 |
Jul 21 09:08:45 PM PDT 24 |
17148821733 ps |
| T1160 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.1482467303 |
|
|
Jul 21 07:30:06 PM PDT 24 |
Jul 21 07:35:45 PM PDT 24 |
3377852780 ps |
| T833 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.1854254313 |
|
|
Jul 21 08:01:23 PM PDT 24 |
Jul 21 08:12:09 PM PDT 24 |
5879578200 ps |
| T1161 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3415315226 |
|
|
Jul 21 07:37:13 PM PDT 24 |
Jul 21 08:55:12 PM PDT 24 |
15163073765 ps |
| T1162 |
/workspace/coverage/default/2.chip_sw_rv_timer_irq.2249897279 |
|
|
Jul 21 07:47:23 PM PDT 24 |
Jul 21 07:51:44 PM PDT 24 |
2885052984 ps |
| T1163 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.2439924518 |
|
|
Jul 21 07:54:31 PM PDT 24 |
Jul 21 09:10:51 PM PDT 24 |
14506097286 ps |
| T1164 |
/workspace/coverage/default/2.chip_tap_straps_dev.3355884070 |
|
|
Jul 21 07:51:04 PM PDT 24 |
Jul 21 07:56:31 PM PDT 24 |
3789971558 ps |
| T1165 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.606336163 |
|
|
Jul 21 07:50:59 PM PDT 24 |
Jul 21 07:57:16 PM PDT 24 |
2534791486 ps |
| T1166 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.341396346 |
|
|
Jul 21 07:48:32 PM PDT 24 |
Jul 21 08:03:57 PM PDT 24 |
6895603970 ps |
| T824 |
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1918286258 |
|
|
Jul 21 08:01:01 PM PDT 24 |
Jul 21 08:07:10 PM PDT 24 |
3633668930 ps |
| T1167 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.4168928728 |
|
|
Jul 21 07:32:31 PM PDT 24 |
Jul 21 08:27:10 PM PDT 24 |
28341957895 ps |
| T1168 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.339605182 |
|
|
Jul 21 07:38:21 PM PDT 24 |
Jul 21 07:45:22 PM PDT 24 |
2890802513 ps |
| T809 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2383620433 |
|
|
Jul 21 08:00:27 PM PDT 24 |
Jul 21 08:06:16 PM PDT 24 |
3206109948 ps |
| T1169 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3103365220 |
|
|
Jul 21 07:33:39 PM PDT 24 |
Jul 21 07:35:41 PM PDT 24 |
2430501267 ps |
| T1170 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1730698289 |
|
|
Jul 21 07:33:29 PM PDT 24 |
Jul 21 07:44:42 PM PDT 24 |
5534812270 ps |
| T786 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.234125485 |
|
|
Jul 21 07:52:22 PM PDT 24 |
Jul 21 08:04:40 PM PDT 24 |
4209897130 ps |
| T1171 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3273816442 |
|
|
Jul 21 07:46:26 PM PDT 24 |
Jul 21 07:54:16 PM PDT 24 |
4698306080 ps |
| T772 |
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.223963750 |
|
|
Jul 21 07:56:54 PM PDT 24 |
Jul 21 08:04:44 PM PDT 24 |
3515914648 ps |
| T1172 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.319912712 |
|
|
Jul 21 07:31:26 PM PDT 24 |
Jul 21 07:54:12 PM PDT 24 |
5589661752 ps |
| T329 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3161973006 |
|
|
Jul 21 07:37:45 PM PDT 24 |
Jul 21 08:14:01 PM PDT 24 |
11651915778 ps |
| T1173 |
/workspace/coverage/default/0.chip_sw_aes_smoketest.604871353 |
|
|
Jul 21 07:36:35 PM PDT 24 |
Jul 21 07:40:22 PM PDT 24 |
2455771256 ps |
| T190 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.318816819 |
|
|
Jul 21 07:45:49 PM PDT 24 |
Jul 21 07:57:02 PM PDT 24 |
4621968497 ps |
| T1174 |
/workspace/coverage/default/1.chip_sw_hmac_enc.1904442836 |
|
|
Jul 21 07:37:30 PM PDT 24 |
Jul 21 07:42:46 PM PDT 24 |
3240558946 ps |
| T1175 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access.423396568 |
|
|
Jul 21 07:29:56 PM PDT 24 |
Jul 21 07:47:32 PM PDT 24 |
5493416100 ps |
| T1176 |
/workspace/coverage/default/1.chip_sw_rv_timer_irq.577796524 |
|
|
Jul 21 07:33:58 PM PDT 24 |
Jul 21 07:37:33 PM PDT 24 |
2474137224 ps |
| T1177 |
/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.4111184935 |
|
|
Jul 21 07:35:57 PM PDT 24 |
Jul 21 08:33:57 PM PDT 24 |
11187724840 ps |
| T1178 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.77424911 |
|
|
Jul 21 07:33:52 PM PDT 24 |
Jul 21 07:38:14 PM PDT 24 |
3189885033 ps |
| T536 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.1937641054 |
|
|
Jul 21 07:34:58 PM PDT 24 |
Jul 21 07:49:29 PM PDT 24 |
4742853880 ps |
| T773 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1816040948 |
|
|
Jul 21 08:01:42 PM PDT 24 |
Jul 21 08:07:30 PM PDT 24 |
3616833784 ps |
| T295 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.62562143 |
|
|
Jul 21 07:40:04 PM PDT 24 |
Jul 21 07:44:40 PM PDT 24 |
2944603788 ps |
| T1179 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod.2140750140 |
|
|
Jul 21 07:59:27 PM PDT 24 |
Jul 21 08:51:44 PM PDT 24 |
15440008553 ps |
| T1180 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.34371279 |
|
|
Jul 21 07:34:02 PM PDT 24 |
Jul 21 07:40:47 PM PDT 24 |
3548902800 ps |
| T806 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.3080133230 |
|
|
Jul 21 07:57:28 PM PDT 24 |
Jul 21 08:11:40 PM PDT 24 |
5479950298 ps |
| T1181 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.961177942 |
|
|
Jul 21 07:42:01 PM PDT 24 |
Jul 21 07:47:02 PM PDT 24 |
3405761016 ps |
| T781 |
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1077474727 |
|
|
Jul 21 07:59:52 PM PDT 24 |
Jul 21 08:06:49 PM PDT 24 |
3964360712 ps |
| T1182 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.3350093727 |
|
|
Jul 21 07:44:11 PM PDT 24 |
Jul 21 07:57:31 PM PDT 24 |
4609159376 ps |
| T1183 |
/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.1224222928 |
|
|
Jul 21 07:51:25 PM PDT 24 |
Jul 21 08:16:58 PM PDT 24 |
8876552992 ps |
| T1184 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.1912151454 |
|
|
Jul 21 07:31:06 PM PDT 24 |
Jul 21 07:49:47 PM PDT 24 |
5652590917 ps |
| T1185 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3327650712 |
|
|
Jul 21 07:34:55 PM PDT 24 |
Jul 21 08:38:18 PM PDT 24 |
21019704192 ps |
| T1186 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter.568901515 |
|
|
Jul 21 07:37:34 PM PDT 24 |
Jul 21 07:40:36 PM PDT 24 |
2845479304 ps |
| T344 |
/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.1700769069 |
|
|
Jul 21 07:34:01 PM PDT 24 |
Jul 21 07:42:24 PM PDT 24 |
3845160492 ps |
| T1187 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2219954500 |
|
|
Jul 21 07:44:33 PM PDT 24 |
Jul 21 08:04:48 PM PDT 24 |
7092046244 ps |
| T22 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.832827059 |
|
|
Jul 21 07:34:08 PM PDT 24 |
Jul 21 07:39:19 PM PDT 24 |
2823234733 ps |
| T834 |
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3943851143 |
|
|
Jul 21 07:55:23 PM PDT 24 |
Jul 21 08:03:29 PM PDT 24 |
3870045884 ps |
| T820 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.1256498361 |
|
|
Jul 21 07:55:18 PM PDT 24 |
Jul 21 08:04:31 PM PDT 24 |
4654575628 ps |
| T1188 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2669260830 |
|
|
Jul 21 07:35:24 PM PDT 24 |
Jul 21 07:42:52 PM PDT 24 |
3047279088 ps |
| T1189 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.750806193 |
|
|
Jul 21 07:34:22 PM PDT 24 |
Jul 21 07:52:08 PM PDT 24 |
8158659898 ps |
| T1190 |
/workspace/coverage/default/2.chip_sw_aes_enc.1887181703 |
|
|
Jul 21 07:46:20 PM PDT 24 |
Jul 21 07:50:31 PM PDT 24 |
2400398344 ps |
| T1191 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2957140435 |
|
|
Jul 21 07:35:48 PM PDT 24 |
Jul 21 07:43:48 PM PDT 24 |
5101684708 ps |
| T1192 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.2565320256 |
|
|
Jul 21 07:32:33 PM PDT 24 |
Jul 21 07:59:30 PM PDT 24 |
8494412976 ps |
| T1193 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1213758467 |
|
|
Jul 21 07:38:22 PM PDT 24 |
Jul 21 07:52:02 PM PDT 24 |
4784499548 ps |
| T336 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3282091765 |
|
|
Jul 21 07:43:38 PM PDT 24 |
Jul 21 07:57:58 PM PDT 24 |
4901818752 ps |
| T1194 |
/workspace/coverage/default/2.chip_sw_alert_handler_escalation.401928232 |
|
|
Jul 21 07:50:27 PM PDT 24 |
Jul 21 08:03:18 PM PDT 24 |
6106215626 ps |
| T1195 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.247158015 |
|
|
Jul 21 07:31:45 PM PDT 24 |
Jul 21 07:35:06 PM PDT 24 |
1892720368 ps |
| T301 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1171881619 |
|
|
Jul 21 07:34:10 PM PDT 24 |
Jul 21 07:53:35 PM PDT 24 |
10702179967 ps |
| T712 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.1938455384 |
|
|
Jul 21 07:57:53 PM PDT 24 |
Jul 21 08:08:53 PM PDT 24 |
5044385096 ps |
| T1196 |
/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.408060912 |
|
|
Jul 21 07:35:06 PM PDT 24 |
Jul 21 07:48:44 PM PDT 24 |
4558521564 ps |
| T760 |
/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1823023670 |
|
|
Jul 21 07:43:20 PM PDT 24 |
Jul 21 07:56:00 PM PDT 24 |
5471324210 ps |
| T1197 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.95098499 |
|
|
Jul 21 07:57:32 PM PDT 24 |
Jul 21 08:07:38 PM PDT 24 |
5448241588 ps |
| T1198 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3785181704 |
|
|
Jul 21 07:37:16 PM PDT 24 |
Jul 21 09:04:41 PM PDT 24 |
18775573000 ps |
| T1199 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.745399438 |
|
|
Jul 21 07:53:28 PM PDT 24 |
Jul 21 07:59:05 PM PDT 24 |
3012622056 ps |
| T1200 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3296630036 |
|
|
Jul 21 07:31:19 PM PDT 24 |
Jul 21 07:52:15 PM PDT 24 |
7241322692 ps |
| T795 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2509828635 |
|
|
Jul 21 07:57:24 PM PDT 24 |
Jul 21 08:06:39 PM PDT 24 |
4296555414 ps |
| T23 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3625299350 |
|
|
Jul 21 07:31:16 PM PDT 24 |
Jul 21 07:37:23 PM PDT 24 |
2786539450 ps |
| T1201 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.3241103252 |
|
|
Jul 21 07:45:32 PM PDT 24 |
Jul 21 08:51:00 PM PDT 24 |
16713339856 ps |