| T1202 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.683789616 |
|
|
Jul 21 07:30:28 PM PDT 24 |
Jul 21 07:37:26 PM PDT 24 |
6069720914 ps |
| T1203 |
/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.202835583 |
|
|
Jul 21 07:36:41 PM PDT 24 |
Jul 21 07:42:35 PM PDT 24 |
2833946329 ps |
| T1204 |
/workspace/coverage/default/1.chip_sw_alert_handler_escalation.1922691344 |
|
|
Jul 21 07:37:05 PM PDT 24 |
Jul 21 07:48:06 PM PDT 24 |
6109679314 ps |
| T1205 |
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3918520979 |
|
|
Jul 21 08:03:07 PM PDT 24 |
Jul 21 08:10:31 PM PDT 24 |
3941464088 ps |
| T1206 |
/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.930723034 |
|
|
Jul 21 07:37:20 PM PDT 24 |
Jul 21 08:19:19 PM PDT 24 |
24506215314 ps |
| T737 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.4269413555 |
|
|
Jul 21 07:30:24 PM PDT 24 |
Jul 21 07:44:24 PM PDT 24 |
4683515640 ps |
| T1207 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.861027393 |
|
|
Jul 21 07:39:36 PM PDT 24 |
Jul 21 08:49:52 PM PDT 24 |
15282444560 ps |
| T774 |
/workspace/coverage/default/58.chip_sw_all_escalation_resets.2716255498 |
|
|
Jul 21 08:00:31 PM PDT 24 |
Jul 21 08:12:32 PM PDT 24 |
5555422920 ps |
| T1208 |
/workspace/coverage/default/1.chip_tap_straps_prod.3770810095 |
|
|
Jul 21 07:39:19 PM PDT 24 |
Jul 21 08:07:14 PM PDT 24 |
14431350507 ps |
| T1209 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.563952175 |
|
|
Jul 21 07:49:33 PM PDT 24 |
Jul 21 07:54:09 PM PDT 24 |
3121115960 ps |
| T1210 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.3772871147 |
|
|
Jul 21 07:48:04 PM PDT 24 |
Jul 21 08:17:42 PM PDT 24 |
8013711160 ps |
| T257 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.3825561079 |
|
|
Jul 21 07:46:14 PM PDT 24 |
Jul 21 07:57:50 PM PDT 24 |
7459097080 ps |
| T1211 |
/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.3738016267 |
|
|
Jul 21 07:48:37 PM PDT 24 |
Jul 21 07:52:43 PM PDT 24 |
2911160604 ps |
| T1212 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3350964848 |
|
|
Jul 21 07:36:03 PM PDT 24 |
Jul 21 07:54:00 PM PDT 24 |
7728114526 ps |
| T829 |
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2638560720 |
|
|
Jul 21 08:00:26 PM PDT 24 |
Jul 21 08:07:36 PM PDT 24 |
3449305152 ps |
| T1213 |
/workspace/coverage/default/2.rom_volatile_raw_unlock.813643104 |
|
|
Jul 21 07:51:27 PM PDT 24 |
Jul 21 07:53:25 PM PDT 24 |
2423988667 ps |
| T1214 |
/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.746004059 |
|
|
Jul 21 07:30:43 PM PDT 24 |
Jul 21 07:46:09 PM PDT 24 |
6311149404 ps |
| T357 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3501684854 |
|
|
Jul 21 07:30:05 PM PDT 24 |
Jul 21 07:42:09 PM PDT 24 |
4613158645 ps |
| T1215 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1247811698 |
|
|
Jul 21 07:31:29 PM PDT 24 |
Jul 21 07:53:20 PM PDT 24 |
10881960211 ps |
| T1216 |
/workspace/coverage/default/1.chip_sw_flash_init.1245013334 |
|
|
Jul 21 07:38:42 PM PDT 24 |
Jul 21 08:18:35 PM PDT 24 |
19604666440 ps |
| T1217 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.885758843 |
|
|
Jul 21 07:31:37 PM PDT 24 |
Jul 21 07:53:22 PM PDT 24 |
7028821570 ps |
| T1218 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2560970704 |
|
|
Jul 21 07:52:48 PM PDT 24 |
Jul 21 08:06:12 PM PDT 24 |
4264830408 ps |
| T303 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1479117892 |
|
|
Jul 21 07:33:06 PM PDT 24 |
Jul 21 07:43:50 PM PDT 24 |
4967351028 ps |
| T1219 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.3804979353 |
|
|
Jul 21 07:34:15 PM PDT 24 |
Jul 21 07:44:46 PM PDT 24 |
6342348970 ps |
| T1220 |
/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1371907592 |
|
|
Jul 21 07:45:58 PM PDT 24 |
Jul 21 07:57:32 PM PDT 24 |
19158383240 ps |
| T1221 |
/workspace/coverage/default/63.chip_sw_all_escalation_resets.2382288520 |
|
|
Jul 21 07:59:56 PM PDT 24 |
Jul 21 08:10:51 PM PDT 24 |
4936506540 ps |
| T1222 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1421938389 |
|
|
Jul 21 07:54:19 PM PDT 24 |
Jul 21 08:36:32 PM PDT 24 |
12957051600 ps |
| T1223 |
/workspace/coverage/default/0.chip_sw_coremark.2284159949 |
|
|
Jul 21 07:33:21 PM PDT 24 |
Jul 21 11:35:52 PM PDT 24 |
72259783900 ps |
| T1224 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3032708882 |
|
|
Jul 21 07:40:42 PM PDT 24 |
Jul 21 08:02:24 PM PDT 24 |
5416645100 ps |
| T1225 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.3138280828 |
|
|
Jul 21 07:36:18 PM PDT 24 |
Jul 21 07:39:52 PM PDT 24 |
2432163384 ps |
| T1226 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.320003881 |
|
|
Jul 21 07:46:23 PM PDT 24 |
Jul 21 09:03:24 PM PDT 24 |
18095403910 ps |
| T1227 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.3842975193 |
|
|
Jul 21 07:37:44 PM PDT 24 |
Jul 21 07:47:55 PM PDT 24 |
5398989114 ps |
| T429 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1198994258 |
|
|
Jul 21 07:49:41 PM PDT 24 |
Jul 21 07:56:45 PM PDT 24 |
7601448244 ps |
| T1228 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.4168756926 |
|
|
Jul 21 07:52:45 PM PDT 24 |
Jul 21 08:00:45 PM PDT 24 |
3049360120 ps |
| T1229 |
/workspace/coverage/default/1.chip_sw_edn_kat.3895910585 |
|
|
Jul 21 07:35:10 PM PDT 24 |
Jul 21 07:45:28 PM PDT 24 |
3080650440 ps |
| T1230 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4252019328 |
|
|
Jul 21 07:29:31 PM PDT 24 |
Jul 21 07:58:53 PM PDT 24 |
21220110118 ps |
| T1231 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.395524286 |
|
|
Jul 21 07:54:29 PM PDT 24 |
Jul 21 08:04:45 PM PDT 24 |
5351783744 ps |
| T1232 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.4190514740 |
|
|
Jul 21 07:45:24 PM PDT 24 |
Jul 21 07:56:36 PM PDT 24 |
5373593052 ps |
| T1233 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.652929101 |
|
|
Jul 21 07:46:00 PM PDT 24 |
Jul 21 09:11:48 PM PDT 24 |
47837169324 ps |
| T1234 |
/workspace/coverage/default/1.rom_e2e_asm_init_rma.13643207 |
|
|
Jul 21 07:45:55 PM PDT 24 |
Jul 21 08:55:19 PM PDT 24 |
14961444172 ps |
| T1235 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.1003970503 |
|
|
Jul 21 07:30:19 PM PDT 24 |
Jul 21 08:02:06 PM PDT 24 |
7791764472 ps |
| T376 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2473738111 |
|
|
Jul 21 07:51:02 PM PDT 24 |
Jul 21 07:58:19 PM PDT 24 |
5223143176 ps |
| T749 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.2078046660 |
|
|
Jul 21 07:42:33 PM PDT 24 |
Jul 21 07:54:07 PM PDT 24 |
4547248008 ps |
| T1236 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.2341943372 |
|
|
Jul 21 07:51:36 PM PDT 24 |
Jul 21 07:55:46 PM PDT 24 |
3226857976 ps |
| T1237 |
/workspace/coverage/default/2.rom_e2e_asm_init_rma.4137290085 |
|
|
Jul 21 07:55:24 PM PDT 24 |
Jul 21 08:45:55 PM PDT 24 |
14652376065 ps |
| T1238 |
/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2746131305 |
|
|
Jul 21 07:56:51 PM PDT 24 |
Jul 21 08:04:21 PM PDT 24 |
4160175710 ps |
| T1239 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2543662636 |
|
|
Jul 21 07:45:06 PM PDT 24 |
Jul 21 07:53:47 PM PDT 24 |
7873945272 ps |
| T222 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.3760286728 |
|
|
Jul 21 07:37:22 PM PDT 24 |
Jul 21 08:12:26 PM PDT 24 |
8966042388 ps |
| T811 |
/workspace/coverage/default/96.chip_sw_all_escalation_resets.1386204137 |
|
|
Jul 21 08:02:58 PM PDT 24 |
Jul 21 08:14:00 PM PDT 24 |
5500184160 ps |
| T377 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2026788479 |
|
|
Jul 21 07:40:15 PM PDT 24 |
Jul 21 07:45:29 PM PDT 24 |
4885570880 ps |
| T1240 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3434895790 |
|
|
Jul 21 07:32:56 PM PDT 24 |
Jul 21 08:45:11 PM PDT 24 |
25605777031 ps |
| T801 |
/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.864587921 |
|
|
Jul 21 07:57:09 PM PDT 24 |
Jul 21 08:04:02 PM PDT 24 |
3481785088 ps |
| T430 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.238523454 |
|
|
Jul 21 07:49:31 PM PDT 24 |
Jul 21 08:12:24 PM PDT 24 |
24408402710 ps |
| T1241 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1647631062 |
|
|
Jul 21 07:49:32 PM PDT 24 |
Jul 21 08:32:59 PM PDT 24 |
26671337906 ps |
| T1242 |
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3120717055 |
|
|
Jul 21 07:52:36 PM PDT 24 |
Jul 21 08:40:09 PM PDT 24 |
13621556348 ps |
| T802 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.4051414795 |
|
|
Jul 21 07:54:17 PM PDT 24 |
Jul 21 08:04:13 PM PDT 24 |
5274607896 ps |
| T819 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1344903496 |
|
|
Jul 21 07:59:46 PM PDT 24 |
Jul 21 08:07:22 PM PDT 24 |
3795547858 ps |
| T234 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.3368546452 |
|
|
Jul 21 07:35:51 PM PDT 24 |
Jul 21 09:04:44 PM PDT 24 |
49659298178 ps |
| T395 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1532601888 |
|
|
Jul 21 07:37:36 PM PDT 24 |
Jul 21 07:51:18 PM PDT 24 |
4466928060 ps |
| T223 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1410782174 |
|
|
Jul 21 07:31:28 PM PDT 24 |
Jul 21 08:10:11 PM PDT 24 |
9098464976 ps |
| T1243 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1108357252 |
|
|
Jul 21 07:28:33 PM PDT 24 |
Jul 21 08:17:24 PM PDT 24 |
13111212880 ps |
| T1244 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3902737706 |
|
|
Jul 21 07:34:20 PM PDT 24 |
Jul 21 07:48:12 PM PDT 24 |
5959039176 ps |
| T1245 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1332227414 |
|
|
Jul 21 07:48:57 PM PDT 24 |
Jul 21 08:11:46 PM PDT 24 |
13163137312 ps |
| T258 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3659859554 |
|
|
Jul 21 07:30:58 PM PDT 24 |
Jul 21 07:42:18 PM PDT 24 |
6208669446 ps |
| T1246 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2604187658 |
|
|
Jul 21 07:37:55 PM PDT 24 |
Jul 21 08:42:22 PM PDT 24 |
14493427928 ps |
| T379 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3922160950 |
|
|
Jul 21 08:00:30 PM PDT 24 |
Jul 21 08:07:18 PM PDT 24 |
3537502300 ps |
| T782 |
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2063394473 |
|
|
Jul 21 07:58:03 PM PDT 24 |
Jul 21 08:05:04 PM PDT 24 |
3412312582 ps |
| T1247 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3738586422 |
|
|
Jul 21 07:40:27 PM PDT 24 |
Jul 21 08:13:43 PM PDT 24 |
7898141468 ps |
| T1248 |
/workspace/coverage/default/2.chip_sw_aes_masking_off.3191289784 |
|
|
Jul 21 07:45:47 PM PDT 24 |
Jul 21 07:51:49 PM PDT 24 |
3467054158 ps |
| T739 |
/workspace/coverage/default/2.chip_sw_pattgen_ios.2852529738 |
|
|
Jul 21 07:46:36 PM PDT 24 |
Jul 21 07:50:54 PM PDT 24 |
3088028720 ps |
| T1249 |
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1418330783 |
|
|
Jul 21 07:57:56 PM PDT 24 |
Jul 21 08:04:21 PM PDT 24 |
3904733104 ps |
| T1250 |
/workspace/coverage/default/2.rom_e2e_self_hash.2325682563 |
|
|
Jul 21 07:55:06 PM PDT 24 |
Jul 21 10:01:09 PM PDT 24 |
26032653934 ps |
| T1251 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2350376042 |
|
|
Jul 21 07:49:06 PM PDT 24 |
Jul 21 08:20:48 PM PDT 24 |
11630011490 ps |
| T1252 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2893007056 |
|
|
Jul 21 07:38:48 PM PDT 24 |
Jul 21 08:56:38 PM PDT 24 |
15143287056 ps |
| T1253 |
/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.3993440305 |
|
|
Jul 21 07:34:18 PM PDT 24 |
Jul 21 07:44:21 PM PDT 24 |
8115235905 ps |
| T1254 |
/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.4288840426 |
|
|
Jul 21 07:55:12 PM PDT 24 |
Jul 21 08:14:41 PM PDT 24 |
13973999776 ps |
| T1255 |
/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.18129366 |
|
|
Jul 21 07:34:01 PM PDT 24 |
Jul 21 07:37:01 PM PDT 24 |
2971874064 ps |
| T815 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.1530624554 |
|
|
Jul 21 08:00:07 PM PDT 24 |
Jul 21 08:11:28 PM PDT 24 |
5465387686 ps |
| T1256 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3982141119 |
|
|
Jul 21 07:58:04 PM PDT 24 |
Jul 21 08:05:04 PM PDT 24 |
4108150152 ps |
| T1257 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.109081657 |
|
|
Jul 21 07:55:52 PM PDT 24 |
Jul 21 08:04:25 PM PDT 24 |
5387902712 ps |
| T1258 |
/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.777277060 |
|
|
Jul 21 07:56:17 PM PDT 24 |
Jul 21 08:16:49 PM PDT 24 |
10146988766 ps |
| T1259 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.27274542 |
|
|
Jul 21 07:35:37 PM PDT 24 |
Jul 21 07:44:16 PM PDT 24 |
4365312960 ps |
| T835 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1859725286 |
|
|
Jul 21 07:55:45 PM PDT 24 |
Jul 21 08:02:40 PM PDT 24 |
3585604548 ps |
| T1260 |
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.2244272794 |
|
|
Jul 21 07:52:36 PM PDT 24 |
Jul 21 08:48:10 PM PDT 24 |
13062753304 ps |
| T747 |
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1179206306 |
|
|
Jul 21 08:01:22 PM PDT 24 |
Jul 21 08:07:36 PM PDT 24 |
3472695264 ps |
| T9 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3434631139 |
|
|
Jul 21 07:32:53 PM PDT 24 |
Jul 21 07:42:32 PM PDT 24 |
4839692520 ps |
| T1261 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2540094283 |
|
|
Jul 21 07:39:55 PM PDT 24 |
Jul 21 08:09:03 PM PDT 24 |
9327736230 ps |
| T1262 |
/workspace/coverage/default/0.rom_e2e_self_hash.719660949 |
|
|
Jul 21 07:38:15 PM PDT 24 |
Jul 21 09:20:41 PM PDT 24 |
26074815720 ps |
| T1263 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.3367984048 |
|
|
Jul 21 07:47:10 PM PDT 24 |
Jul 21 07:55:31 PM PDT 24 |
4730880800 ps |
| T1264 |
/workspace/coverage/default/2.chip_sw_hmac_smoketest.1633521374 |
|
|
Jul 21 07:52:03 PM PDT 24 |
Jul 21 07:58:18 PM PDT 24 |
3795126488 ps |
| T296 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.974464286 |
|
|
Jul 21 07:49:57 PM PDT 24 |
Jul 21 07:53:29 PM PDT 24 |
2611436326 ps |
| T1265 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.1052944160 |
|
|
Jul 21 07:32:47 PM PDT 24 |
Jul 21 07:43:56 PM PDT 24 |
10180965736 ps |
| T1266 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1195646786 |
|
|
Jul 21 07:36:01 PM PDT 24 |
Jul 21 07:45:27 PM PDT 24 |
7788722424 ps |
| T1267 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.1655883623 |
|
|
Jul 21 07:54:38 PM PDT 24 |
Jul 21 08:47:13 PM PDT 24 |
15238691100 ps |
| T1268 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.1298534707 |
|
|
Jul 21 07:47:50 PM PDT 24 |
Jul 21 07:53:34 PM PDT 24 |
2975245224 ps |
| T1269 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.499777697 |
|
|
Jul 21 07:51:20 PM PDT 24 |
Jul 21 07:54:32 PM PDT 24 |
2780979150 ps |
| T307 |
/workspace/coverage/default/3.chip_sw_all_escalation_resets.3987935852 |
|
|
Jul 21 07:51:39 PM PDT 24 |
Jul 21 08:01:46 PM PDT 24 |
4424362164 ps |
| T343 |
/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.859833242 |
|
|
Jul 21 07:28:39 PM PDT 24 |
Jul 21 07:37:51 PM PDT 24 |
3779496948 ps |
| T770 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2693932160 |
|
|
Jul 21 07:57:40 PM PDT 24 |
Jul 21 08:04:32 PM PDT 24 |
3774928032 ps |
| T224 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.149225691 |
|
|
Jul 21 07:32:38 PM PDT 24 |
Jul 21 08:41:40 PM PDT 24 |
12977826486 ps |
| T346 |
/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.541895175 |
|
|
Jul 21 07:48:54 PM PDT 24 |
Jul 21 07:56:13 PM PDT 24 |
4241300240 ps |
| T1270 |
/workspace/coverage/default/2.chip_sw_example_manufacturer.3983002627 |
|
|
Jul 21 07:44:00 PM PDT 24 |
Jul 21 07:47:29 PM PDT 24 |
2940337920 ps |
| T1271 |
/workspace/coverage/default/1.chip_sw_edn_auto_mode.1709991442 |
|
|
Jul 21 07:37:26 PM PDT 24 |
Jul 21 07:56:48 PM PDT 24 |
5363335272 ps |
| T1272 |
/workspace/coverage/default/4.chip_tap_straps_prod.1924461827 |
|
|
Jul 21 07:53:08 PM PDT 24 |
Jul 21 08:02:33 PM PDT 24 |
5603101798 ps |
| T13 |
/workspace/coverage/default/0.chip_sw_sleep_pin_retention.841100090 |
|
|
Jul 21 07:29:34 PM PDT 24 |
Jul 21 07:36:32 PM PDT 24 |
4125045500 ps |
| T1273 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1966463255 |
|
|
Jul 21 07:49:46 PM PDT 24 |
Jul 21 07:54:54 PM PDT 24 |
3581548470 ps |
| T1274 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1667658558 |
|
|
Jul 21 07:40:18 PM PDT 24 |
Jul 21 08:01:18 PM PDT 24 |
6912773068 ps |
| T1275 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.4200455274 |
|
|
Jul 21 08:07:47 PM PDT 24 |
Jul 21 08:18:38 PM PDT 24 |
6290663650 ps |
| T1276 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.1541597582 |
|
|
Jul 21 07:56:46 PM PDT 24 |
Jul 21 08:09:28 PM PDT 24 |
6123920598 ps |
| T810 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3957412733 |
|
|
Jul 21 07:56:41 PM PDT 24 |
Jul 21 08:03:04 PM PDT 24 |
3786714502 ps |
| T1277 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2627634511 |
|
|
Jul 21 07:38:12 PM PDT 24 |
Jul 21 07:49:49 PM PDT 24 |
3900239704 ps |
| T1278 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.751337644 |
|
|
Jul 21 07:48:40 PM PDT 24 |
Jul 21 07:58:35 PM PDT 24 |
4674766954 ps |
| T63 |
/workspace/coverage/default/2.chip_sw_alert_test.2426012488 |
|
|
Jul 21 07:45:49 PM PDT 24 |
Jul 21 07:51:51 PM PDT 24 |
3208936904 ps |
| T1279 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2797921066 |
|
|
Jul 21 07:30:25 PM PDT 24 |
Jul 21 07:38:50 PM PDT 24 |
6956160904 ps |
| T156 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2275895427 |
|
|
Jul 21 07:30:14 PM PDT 24 |
Jul 21 07:35:35 PM PDT 24 |
2810339277 ps |
| T161 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1864071886 |
|
|
Jul 21 07:29:55 PM PDT 24 |
Jul 21 07:41:07 PM PDT 24 |
5563891674 ps |
| T787 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.716202907 |
|
|
Jul 21 08:01:50 PM PDT 24 |
Jul 21 08:07:09 PM PDT 24 |
3574796662 ps |
| T1280 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2556437383 |
|
|
Jul 21 07:29:33 PM PDT 24 |
Jul 21 07:36:50 PM PDT 24 |
3904631250 ps |
| T337 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1195413743 |
|
|
Jul 21 07:32:34 PM PDT 24 |
Jul 21 07:48:04 PM PDT 24 |
5123829324 ps |
| T1281 |
/workspace/coverage/default/0.chip_sw_aon_timer_irq.4091801466 |
|
|
Jul 21 07:30:14 PM PDT 24 |
Jul 21 07:36:47 PM PDT 24 |
4076038916 ps |
| T1282 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2996827171 |
|
|
Jul 21 07:45:47 PM PDT 24 |
Jul 21 08:38:22 PM PDT 24 |
33927183890 ps |
| T1283 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.2957834796 |
|
|
Jul 21 07:35:37 PM PDT 24 |
Jul 21 07:49:13 PM PDT 24 |
4403062920 ps |
| T789 |
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.653094314 |
|
|
Jul 21 07:59:10 PM PDT 24 |
Jul 21 08:06:42 PM PDT 24 |
4419417184 ps |
| T64 |
/workspace/coverage/default/1.chip_sw_alert_test.2043354107 |
|
|
Jul 21 07:36:51 PM PDT 24 |
Jul 21 07:42:10 PM PDT 24 |
3008001840 ps |
| T1284 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.3916441109 |
|
|
Jul 21 07:31:03 PM PDT 24 |
Jul 21 07:38:01 PM PDT 24 |
4911151958 ps |
| T1285 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.4261097478 |
|
|
Jul 21 07:54:33 PM PDT 24 |
Jul 21 08:23:39 PM PDT 24 |
8940930684 ps |
| T1286 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2256388811 |
|
|
Jul 21 07:52:32 PM PDT 24 |
Jul 21 08:04:56 PM PDT 24 |
4404704884 ps |
| T1287 |
/workspace/coverage/default/0.chip_sw_example_manufacturer.3902781443 |
|
|
Jul 21 07:32:19 PM PDT 24 |
Jul 21 07:37:16 PM PDT 24 |
3431162368 ps |
| T783 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.996104994 |
|
|
Jul 21 08:02:05 PM PDT 24 |
Jul 21 08:14:51 PM PDT 24 |
5579719560 ps |
| T1288 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.1324104470 |
|
|
Jul 21 07:34:34 PM PDT 24 |
Jul 21 08:01:48 PM PDT 24 |
6493173520 ps |
| T1289 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.3852799363 |
|
|
Jul 21 07:29:50 PM PDT 24 |
Jul 21 07:34:01 PM PDT 24 |
3064183372 ps |
| T1290 |
/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.1432611260 |
|
|
Jul 21 07:59:25 PM PDT 24 |
Jul 21 08:07:55 PM PDT 24 |
4230721794 ps |
| T1291 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1795276699 |
|
|
Jul 21 07:34:51 PM PDT 24 |
Jul 21 07:43:02 PM PDT 24 |
4561005582 ps |
| T231 |
/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.324911371 |
|
|
Jul 21 07:48:56 PM PDT 24 |
Jul 21 08:17:02 PM PDT 24 |
22748254040 ps |
| T830 |
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3124389821 |
|
|
Jul 21 07:59:22 PM PDT 24 |
Jul 21 08:05:33 PM PDT 24 |
4130556872 ps |
| T297 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3027866483 |
|
|
Jul 21 07:32:09 PM PDT 24 |
Jul 21 07:37:11 PM PDT 24 |
2306868564 ps |
| T808 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.1459727454 |
|
|
Jul 21 08:00:53 PM PDT 24 |
Jul 21 08:11:22 PM PDT 24 |
6013077646 ps |
| T1292 |
/workspace/coverage/default/1.chip_sw_flash_crash_alert.1267957791 |
|
|
Jul 21 07:41:50 PM PDT 24 |
Jul 21 07:50:50 PM PDT 24 |
5451954788 ps |
| T1293 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4019240377 |
|
|
Jul 21 07:43:50 PM PDT 24 |
Jul 21 08:16:47 PM PDT 24 |
13173225151 ps |
| T1294 |
/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.949666314 |
|
|
Jul 21 07:34:47 PM PDT 24 |
Jul 21 07:43:31 PM PDT 24 |
4394198552 ps |
| T1295 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4252633363 |
|
|
Jul 21 07:34:57 PM PDT 24 |
Jul 21 07:54:06 PM PDT 24 |
16369858099 ps |
| T434 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.4002672399 |
|
|
Jul 21 07:40:34 PM PDT 24 |
Jul 21 07:50:30 PM PDT 24 |
5397792560 ps |
| T131 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2368180783 |
|
|
Jul 21 07:37:07 PM PDT 24 |
Jul 21 07:46:43 PM PDT 24 |
5304174260 ps |
| T1296 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.323858141 |
|
|
Jul 21 07:30:57 PM PDT 24 |
Jul 21 07:35:35 PM PDT 24 |
2913528397 ps |
| T1297 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.889336575 |
|
|
Jul 21 07:53:06 PM PDT 24 |
Jul 21 08:01:06 PM PDT 24 |
5440720200 ps |
| T1298 |
/workspace/coverage/default/0.chip_sw_csrng_kat_test.4033290083 |
|
|
Jul 21 07:33:26 PM PDT 24 |
Jul 21 07:38:10 PM PDT 24 |
3468553344 ps |
| T1299 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.82086885 |
|
|
Jul 21 07:52:21 PM PDT 24 |
Jul 21 08:03:01 PM PDT 24 |
3603639080 ps |
| T328 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.3544713801 |
|
|
Jul 21 07:52:09 PM PDT 24 |
Jul 21 08:12:08 PM PDT 24 |
5995445720 ps |
| T1300 |
/workspace/coverage/default/0.rom_e2e_asm_init_dev.1549689838 |
|
|
Jul 21 07:36:24 PM PDT 24 |
Jul 21 08:43:11 PM PDT 24 |
14975281532 ps |
| T1301 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.4267965870 |
|
|
Jul 21 07:30:30 PM PDT 24 |
Jul 21 11:19:48 PM PDT 24 |
77695274015 ps |
| T812 |
/workspace/coverage/default/62.chip_sw_all_escalation_resets.12834612 |
|
|
Jul 21 07:59:57 PM PDT 24 |
Jul 21 08:12:59 PM PDT 24 |
5837481200 ps |
| T1302 |
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.815490367 |
|
|
Jul 21 07:54:38 PM PDT 24 |
Jul 21 08:05:20 PM PDT 24 |
5355661307 ps |
| T158 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.2943541022 |
|
|
Jul 21 08:01:43 PM PDT 24 |
Jul 21 08:13:27 PM PDT 24 |
4861425916 ps |
| T718 |
/workspace/coverage/default/1.chip_tap_straps_dev.3952705173 |
|
|
Jul 21 07:39:59 PM PDT 24 |
Jul 21 08:06:35 PM PDT 24 |
13258555752 ps |
| T1303 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2567832248 |
|
|
Jul 21 07:29:54 PM PDT 24 |
Jul 21 07:31:58 PM PDT 24 |
2650150346 ps |
| T1304 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.237102189 |
|
|
Jul 21 07:48:58 PM PDT 24 |
Jul 21 07:58:32 PM PDT 24 |
5189966214 ps |
| T1305 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3936286731 |
|
|
Jul 21 07:51:41 PM PDT 24 |
Jul 21 08:19:54 PM PDT 24 |
13996380720 ps |
| T1306 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access.1181346722 |
|
|
Jul 21 07:45:04 PM PDT 24 |
Jul 21 08:03:38 PM PDT 24 |
5499589976 ps |
| T1307 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.3308874305 |
|
|
Jul 21 07:51:45 PM PDT 24 |
Jul 21 08:04:14 PM PDT 24 |
4458833232 ps |
| T1308 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.25038403 |
|
|
Jul 21 07:28:48 PM PDT 24 |
Jul 21 07:31:14 PM PDT 24 |
2850974919 ps |
| T1309 |
/workspace/coverage/default/2.chip_sw_plic_sw_irq.3560567995 |
|
|
Jul 21 07:50:29 PM PDT 24 |
Jul 21 07:55:10 PM PDT 24 |
3043978558 ps |
| T1310 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.931446751 |
|
|
Jul 21 07:46:11 PM PDT 24 |
Jul 21 08:22:01 PM PDT 24 |
8475104616 ps |
| T1311 |
/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.1174704132 |
|
|
Jul 21 07:33:15 PM PDT 24 |
Jul 21 07:38:42 PM PDT 24 |
3458740610 ps |
| T1312 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1419830469 |
|
|
Jul 21 07:48:10 PM PDT 24 |
Jul 21 08:23:15 PM PDT 24 |
9519604696 ps |
| T1313 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2072516040 |
|
|
Jul 21 07:38:22 PM PDT 24 |
Jul 21 08:42:29 PM PDT 24 |
14693632125 ps |
| T402 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2411169082 |
|
|
Jul 21 07:33:01 PM PDT 24 |
Jul 21 07:36:46 PM PDT 24 |
2586462246 ps |
| T1314 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.1585622265 |
|
|
Jul 21 07:44:10 PM PDT 24 |
Jul 21 08:14:46 PM PDT 24 |
20661442218 ps |
| T1315 |
/workspace/coverage/default/0.chip_sw_csrng_smoketest.3133371803 |
|
|
Jul 21 07:31:50 PM PDT 24 |
Jul 21 07:38:02 PM PDT 24 |
3488987704 ps |
| T380 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.709493071 |
|
|
Jul 21 07:54:39 PM PDT 24 |
Jul 21 08:08:44 PM PDT 24 |
5506108504 ps |
| T272 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.549627740 |
|
|
Jul 21 07:31:24 PM PDT 24 |
Jul 21 07:47:11 PM PDT 24 |
5142042482 ps |
| T1316 |
/workspace/coverage/default/1.chip_sw_kmac_entropy.2086317272 |
|
|
Jul 21 07:35:05 PM PDT 24 |
Jul 21 07:40:17 PM PDT 24 |
3047307008 ps |
| T1317 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.2248442058 |
|
|
Jul 21 07:32:54 PM PDT 24 |
Jul 21 08:32:58 PM PDT 24 |
24115496779 ps |
| T191 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through.405125219 |
|
|
Jul 21 07:28:59 PM PDT 24 |
Jul 21 07:41:35 PM PDT 24 |
7275363791 ps |
| T1318 |
/workspace/coverage/default/1.chip_sw_aes_enc.565911498 |
|
|
Jul 21 07:36:37 PM PDT 24 |
Jul 21 07:39:58 PM PDT 24 |
2973601120 ps |
| T73 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3241475310 |
|
|
Jul 21 07:29:35 PM PDT 24 |
Jul 21 07:37:40 PM PDT 24 |
3804614120 ps |
| T836 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2773901155 |
|
|
Jul 21 08:01:39 PM PDT 24 |
Jul 21 08:09:08 PM PDT 24 |
4465701524 ps |
| T741 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_rma.2929243387 |
|
|
Jul 21 07:32:33 PM PDT 24 |
Jul 21 08:05:47 PM PDT 24 |
10682688160 ps |
| T827 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3169929119 |
|
|
Jul 21 08:00:16 PM PDT 24 |
Jul 21 08:06:49 PM PDT 24 |
3182986616 ps |
| T1319 |
/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.2132789468 |
|
|
Jul 21 07:33:11 PM PDT 24 |
Jul 21 07:37:07 PM PDT 24 |
2151308848 ps |
| T1320 |
/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.321483839 |
|
|
Jul 21 07:53:01 PM PDT 24 |
Jul 21 07:56:08 PM PDT 24 |
2915820784 ps |
| T1321 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.1254825841 |
|
|
Jul 21 08:04:18 PM PDT 24 |
Jul 21 08:15:43 PM PDT 24 |
4397123452 ps |
| T1322 |
/workspace/coverage/default/0.rom_e2e_shutdown_output.1514403692 |
|
|
Jul 21 07:41:04 PM PDT 24 |
Jul 21 08:46:31 PM PDT 24 |
29806131020 ps |
| T822 |
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.802587547 |
|
|
Jul 21 08:00:29 PM PDT 24 |
Jul 21 08:05:57 PM PDT 24 |
3845913032 ps |
| T1323 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1839106138 |
|
|
Jul 21 07:40:58 PM PDT 24 |
Jul 21 07:52:47 PM PDT 24 |
4759608890 ps |
| T1324 |
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2789006982 |
|
|
Jul 21 07:57:18 PM PDT 24 |
Jul 21 08:05:40 PM PDT 24 |
3850541120 ps |
| T1325 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.3663876866 |
|
|
Jul 21 07:36:18 PM PDT 24 |
Jul 21 07:53:41 PM PDT 24 |
7315054680 ps |
| T1326 |
/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.846321863 |
|
|
Jul 21 07:43:27 PM PDT 24 |
Jul 21 08:08:55 PM PDT 24 |
8285935280 ps |
| T338 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.2188249707 |
|
|
Jul 21 07:31:36 PM PDT 24 |
Jul 21 07:45:34 PM PDT 24 |
4648832326 ps |
| T1327 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3164433321 |
|
|
Jul 21 07:33:15 PM PDT 24 |
Jul 21 07:52:41 PM PDT 24 |
7501869060 ps |
| T1328 |
/workspace/coverage/default/0.chip_sw_kmac_smoketest.3066266462 |
|
|
Jul 21 07:33:27 PM PDT 24 |
Jul 21 07:37:40 PM PDT 24 |
2918328876 ps |
| T1329 |
/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.531389394 |
|
|
Jul 21 07:30:18 PM PDT 24 |
Jul 21 07:38:31 PM PDT 24 |
3750313360 ps |
| T440 |
/workspace/coverage/default/2.chip_jtag_mem_access.3116615228 |
|
|
Jul 21 07:41:49 PM PDT 24 |
Jul 21 08:05:00 PM PDT 24 |
14265631885 ps |
| T1330 |
/workspace/coverage/default/0.chip_tap_straps_dev.1435619785 |
|
|
Jul 21 07:30:29 PM PDT 24 |
Jul 21 07:56:10 PM PDT 24 |
14799498422 ps |
| T1331 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.2851308357 |
|
|
Jul 21 07:56:37 PM PDT 24 |
Jul 21 08:08:45 PM PDT 24 |
6030675440 ps |
| T225 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1177393920 |
|
|
Jul 21 07:48:18 PM PDT 24 |
Jul 21 08:56:03 PM PDT 24 |
15143498340 ps |
| T308 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2884125707 |
|
|
Jul 21 08:01:08 PM PDT 24 |
Jul 21 08:08:48 PM PDT 24 |
4059680184 ps |
| T1332 |
/workspace/coverage/default/2.chip_sw_kmac_entropy.3738749718 |
|
|
Jul 21 07:45:07 PM PDT 24 |
Jul 21 07:49:35 PM PDT 24 |
2984794000 ps |
| T1333 |
/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.1257384998 |
|
|
Jul 21 07:53:52 PM PDT 24 |
Jul 21 08:11:57 PM PDT 24 |
10004732260 ps |
| T1334 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.4139262429 |
|
|
Jul 21 07:41:50 PM PDT 24 |
Jul 21 07:49:07 PM PDT 24 |
4819833352 ps |
| T1335 |
/workspace/coverage/default/0.chip_sw_aes_idle.3715708576 |
|
|
Jul 21 07:29:34 PM PDT 24 |
Jul 21 07:32:54 PM PDT 24 |
2458763500 ps |
| T1336 |
/workspace/coverage/default/0.chip_sw_flash_init.1137799346 |
|
|
Jul 21 07:29:24 PM PDT 24 |
Jul 21 08:04:58 PM PDT 24 |
17544918419 ps |
| T1337 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.1155486514 |
|
|
Jul 21 07:31:47 PM PDT 24 |
Jul 21 09:13:08 PM PDT 24 |
49245849773 ps |
| T1338 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.2809372779 |
|
|
Jul 21 07:50:15 PM PDT 24 |
Jul 21 07:54:07 PM PDT 24 |
3071919730 ps |
| T256 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.3304429206 |
|
|
Jul 21 07:33:52 PM PDT 24 |
Jul 21 08:11:45 PM PDT 24 |
10908326482 ps |
| T1339 |
/workspace/coverage/default/2.rom_e2e_smoke.3050470170 |
|
|
Jul 21 07:55:53 PM PDT 24 |
Jul 21 08:59:11 PM PDT 24 |
15441249356 ps |
| T1340 |
/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2386779018 |
|
|
Jul 21 07:42:16 PM PDT 24 |
Jul 21 07:46:19 PM PDT 24 |
2885919464 ps |
| T1341 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3965549186 |
|
|
Jul 21 07:41:32 PM PDT 24 |
Jul 21 09:18:25 PM PDT 24 |
23820478976 ps |
| T1342 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.669561312 |
|
|
Jul 21 07:30:32 PM PDT 24 |
Jul 21 07:38:25 PM PDT 24 |
5732757320 ps |
| T1343 |
/workspace/coverage/default/0.chip_tap_straps_prod.1016137431 |
|
|
Jul 21 07:30:16 PM PDT 24 |
Jul 21 07:33:02 PM PDT 24 |
3220323265 ps |
| T1344 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.4192125504 |
|
|
Jul 21 07:30:02 PM PDT 24 |
Jul 21 07:40:52 PM PDT 24 |
5308153041 ps |
| T1345 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.4253283360 |
|
|
Jul 21 07:43:07 PM PDT 24 |
Jul 21 07:54:09 PM PDT 24 |
5214780680 ps |
| T1346 |
/workspace/coverage/default/0.chip_sw_hmac_enc.1092546380 |
|
|
Jul 21 07:30:22 PM PDT 24 |
Jul 21 07:36:35 PM PDT 24 |
3378685496 ps |
| T1347 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3246338173 |
|
|
Jul 21 07:49:18 PM PDT 24 |
Jul 21 08:00:57 PM PDT 24 |
5115526248 ps |
| T1348 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.1690712783 |
|
|
Jul 21 07:29:26 PM PDT 24 |
Jul 21 08:59:01 PM PDT 24 |
22303009060 ps |
| T1349 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.1755504078 |
|
|
Jul 21 07:33:02 PM PDT 24 |
Jul 21 10:44:01 PM PDT 24 |
58775527212 ps |
| T1350 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.3757704133 |
|
|
Jul 21 08:01:57 PM PDT 24 |
Jul 21 08:16:20 PM PDT 24 |
5660752416 ps |
| T1351 |
/workspace/coverage/default/1.chip_sw_example_flash.530412762 |
|
|
Jul 21 07:33:45 PM PDT 24 |
Jul 21 07:37:42 PM PDT 24 |
2644828852 ps |
| T1352 |
/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.4292285827 |
|
|
Jul 21 07:30:55 PM PDT 24 |
Jul 21 10:33:56 PM PDT 24 |
59518050125 ps |
| T1353 |
/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.2301493367 |
|
|
Jul 21 07:36:08 PM PDT 24 |
Jul 21 07:42:15 PM PDT 24 |
3560912900 ps |
| T1354 |
/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.765949836 |
|
|
Jul 21 07:46:56 PM PDT 24 |
Jul 21 11:06:53 PM PDT 24 |
256104224640 ps |
| T1355 |
/workspace/coverage/default/2.chip_sw_hmac_enc_idle.1721396120 |
|
|
Jul 21 07:47:30 PM PDT 24 |
Jul 21 07:52:12 PM PDT 24 |
2781054650 ps |
| T1356 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1643815083 |
|
|
Jul 21 07:29:24 PM PDT 24 |
Jul 21 07:42:00 PM PDT 24 |
9320419888 ps |
| T1357 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.594758680 |
|
|
Jul 21 07:28:29 PM PDT 24 |
Jul 21 07:40:13 PM PDT 24 |
19381350996 ps |
| T340 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.4139589779 |
|
|
Jul 21 07:36:29 PM PDT 24 |
Jul 21 07:51:45 PM PDT 24 |
5536996342 ps |
| T1358 |
/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.3862229995 |
|
|
Jul 21 07:31:08 PM PDT 24 |
Jul 21 07:34:53 PM PDT 24 |
3441644670 ps |
| T1359 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.1385435627 |
|
|
Jul 21 08:00:23 PM PDT 24 |
Jul 21 08:11:22 PM PDT 24 |
4795713260 ps |
| T178 |
/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.319170268 |
|
|
Jul 21 07:43:41 PM PDT 24 |
Jul 21 09:10:59 PM PDT 24 |
44348615200 ps |
| T1360 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2411865570 |
|
|
Jul 21 07:28:37 PM PDT 24 |
Jul 21 07:39:21 PM PDT 24 |
3928788120 ps |
| T355 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.1846948416 |
|
|
Jul 21 07:46:08 PM PDT 24 |
Jul 21 07:57:41 PM PDT 24 |
5013983064 ps |
| T1361 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1919036853 |
|
|
Jul 21 07:39:47 PM PDT 24 |
Jul 21 08:41:51 PM PDT 24 |
14978228165 ps |
| T1362 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.2229866910 |
|
|
Jul 21 07:45:13 PM PDT 24 |
Jul 21 08:59:11 PM PDT 24 |
15568138739 ps |
| T49 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2650813639 |
|
|
Jul 21 07:45:11 PM PDT 24 |
Jul 21 07:53:44 PM PDT 24 |
6525779686 ps |
| T347 |
/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2053043196 |
|
|
Jul 21 07:30:40 PM PDT 24 |
Jul 21 07:37:41 PM PDT 24 |
3586141324 ps |
| T397 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1137187115 |
|
|
Jul 21 07:34:51 PM PDT 24 |
Jul 21 07:50:37 PM PDT 24 |
5081884130 ps |
| T1363 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.670503316 |
|
|
Jul 21 07:57:13 PM PDT 24 |
Jul 21 08:07:47 PM PDT 24 |
5762207792 ps |
| T798 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.3586726799 |
|
|
Jul 21 08:00:00 PM PDT 24 |
Jul 21 08:08:54 PM PDT 24 |
5061858280 ps |
| T1364 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.1117114558 |
|
|
Jul 21 07:35:35 PM PDT 24 |
Jul 21 07:39:47 PM PDT 24 |
3100177576 ps |
| T1365 |
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2955384342 |
|
|
Jul 21 07:53:35 PM PDT 24 |
Jul 21 09:02:15 PM PDT 24 |
17660579162 ps |
| T748 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.3844305261 |
|
|
Jul 21 07:59:59 PM PDT 24 |
Jul 21 08:13:36 PM PDT 24 |
4240948968 ps |
| T1366 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.3028931901 |
|
|
Jul 21 07:34:46 PM PDT 24 |
Jul 21 07:42:59 PM PDT 24 |
3888875990 ps |
| T35 |
/workspace/coverage/default/0.chip_sw_gpio.1049917369 |
|
|
Jul 21 07:29:28 PM PDT 24 |
Jul 21 07:39:12 PM PDT 24 |
3643229597 ps |
| T1367 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.3856080363 |
|
|
Jul 21 08:02:20 PM PDT 24 |
Jul 21 08:11:42 PM PDT 24 |
5422382724 ps |
| T159 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.846314045 |
|
|
Jul 21 07:31:00 PM PDT 24 |
Jul 21 07:41:03 PM PDT 24 |
5611884322 ps |
| T719 |
/workspace/coverage/default/3.chip_tap_straps_dev.3900487155 |
|
|
Jul 21 07:51:59 PM PDT 24 |
Jul 21 08:13:17 PM PDT 24 |
10478604721 ps |
| T1368 |
/workspace/coverage/default/1.chip_sival_flash_info_access.1507488139 |
|
|
Jul 21 07:33:36 PM PDT 24 |
Jul 21 07:38:49 PM PDT 24 |
3631763900 ps |
| T799 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.3689328282 |
|
|
Jul 21 08:00:10 PM PDT 24 |
Jul 21 08:12:47 PM PDT 24 |
5789047956 ps |
| T1369 |
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2612880580 |
|
|
Jul 21 08:02:29 PM PDT 24 |
Jul 21 08:09:33 PM PDT 24 |
3922473726 ps |
| T1370 |
/workspace/coverage/default/0.chip_sw_gpio_smoketest.3079169999 |
|
|
Jul 21 07:33:14 PM PDT 24 |
Jul 21 07:38:03 PM PDT 24 |
3341572094 ps |
| T771 |
/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1599085645 |
|
|
Jul 21 07:59:55 PM PDT 24 |
Jul 21 08:06:29 PM PDT 24 |
3909198862 ps |
| T1371 |
/workspace/coverage/default/1.chip_sw_alert_handler_entropy.1239532308 |
|
|
Jul 21 07:33:44 PM PDT 24 |
Jul 21 07:37:50 PM PDT 24 |
2997207195 ps |