Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3925620	1			T75	23467		T76	56		T77	62
values[2]	774203	1			T75	4279		T76	20		T77	48
values[3]	94975	1			T75	144		T76	1		T81	3
values[4]	50441	1			T75	110		T313	16		T130	262
values[5]	34172	1			T75	42		T313	21		T130	150
values[6]	26878	1			T75	45		T313	24		T130	97
values[7]	22002	1			T75	43		T313	16		T130	82
values[8]	19523	1			T75	41		T313	11		T130	87
values[9]	17572	1			T75	28		T313	4		T130	69
values[10]	16248	1			T75	49		T313	9		T130	72
values[11]	15180	1			T75	36		T313	7		T130	59
values[12]	14372	1			T75	21		T313	11		T130	28
values[13]	14111	1			T75	17		T313	6		T130	28
values[14]	13695	1			T75	37		T313	17		T130	16
values[15]	13050	1			T75	45		T313	12		T130	10
values[16]	12600	1			T75	38		T313	20		T130	9
values[17]	12369	1			T75	24		T313	24		T130	8
values[18]	11980	1			T75	30		T313	10		T130	9
values[19]	11384	1			T75	31		T313	21		T130	9
values[20]	11126	1			T75	25		T313	24		T130	15
values[21]	10907	1			T75	29		T313	29		T130	11
values[22]	10475	1			T75	34		T313	21		T130	15
values[23]	9973	1			T75	25		T313	7		T130	14
values[24]	9972	1			T75	22		T313	13		T130	11
values[25]	9839	1			T75	23		T313	11		T130	9
values[26]	9337	1			T75	26		T313	18		T130	14
values[27]	8967	1			T75	24		T313	4		T130	7
values[28]	8672	1			T75	35		T313	2		T130	12
values[29]	8010	1			T75	35		T313	1		T130	6
values[30]	7361	1			T75	22		T313	1		T130	9
values[31]	6672	1			T75	9		T313	1		T130	8
values[32]	5916	1			T75	5		T313	2		T130	9
values[33]	5482	1			T75	10		T313	6		T130	15
values[34]	5161	1			T75	7		T313	7		T130	12
values[35]	4915	1			T75	5		T313	3		T130	11
values[36]	4575	1			T75	6		T313	2		T130	14
values[37]	4274	1			T75	5		T313	2		T130	14
values[38]	4168	1			T75	11		T130	8		T765	6
values[39]	3801	1			T75	12		T130	9		T765	6
values[40]	3634	1			T75	5		T130	5		T765	6
values[41]	3481	1			T75	10		T130	5		T765	6
values[42]	3375	1			T75	8		T130	4		T765	6
values[43]	3393	1			T75	13		T130	6		T765	6
values[44]	3211	1			T75	8		T130	7		T765	6
values[45]	3281	1			T75	11		T130	12		T765	6
values[46]	3135	1			T75	7		T130	8		T765	6
values[47]	3104	1			T75	8		T130	6		T765	6
values[48]	3001	1			T75	17		T130	4		T765	6
values[49]	2966	1			T75	8		T130	6		T765	6
values[50]	2942	1			T75	9		T130	7		T765	6
values[51]	2817	1			T75	9		T130	4		T765	6
values[52]	2760	1			T75	4		T130	5		T765	6
values[53]	2613	1			T75	1		T130	6		T765	6
values[54]	2550	1			T75	1		T130	8		T765	6
values[55]	2469	1			T75	3		T130	10		T765	6
values[56]	2533	1			T75	1		T130	11		T765	6
values[57]	2353	1			T75	2		T130	6		T765	6
values[58]	2313	1			T75	1		T130	8		T765	6
values[59]	2334	1			T75	1		T130	5		T765	6
values[60]	2403	1			T75	1		T130	10		T765	6
values[61]	2562	1			T75	2		T130	11		T765	6
values[62]	3628	1			T75	1		T130	15		T765	6
values[63]	10010	1			T75	6		T130	38		T765	6
values[64]	233240	1			T75	118		T130	179		T765	1171

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4962448	1			T75	25961		T76	120		T77	124
values[2]	841737	1			T75	4234		T76	24		T77	42
values[3]	82019	1			T75	97		T76	2		T77	2
values[4]	13639	1			T75	8		T81	1		T313	1
values[5]	4898	1			T75	1		T130	7		T439	1
values[6]	2829	1			T75	4		T130	10		T765	3
values[7]	2005	1			T75	2		T130	16		T765	2
values[8]	1765	1			T75	1		T130	25		T765	2
values[9]	1620	1			T75	1		T130	23		T542	4
values[10]	1560	1			T75	1		T130	10		T542	4
values[11]	1459	1			T75	4		T130	4		T542	4
values[12]	1411	1			T75	2		T130	3		T542	4
values[13]	1263	1			T75	1		T130	14		T542	4
values[14]	1177	1			T75	2		T130	21		T542	4
values[15]	1106	1			T75	1		T130	12		T542	4
values[16]	1047	1			T75	1		T130	9		T542	4
values[17]	964	1			T75	4		T130	6		T542	4
values[18]	895	1			T75	1		T130	12		T542	4
values[19]	849	1			T75	4		T130	8		T542	4
values[20]	839	1			T75	2		T130	9		T542	4
values[21]	836	1			T75	2		T130	4		T542	4
values[22]	751	1			T75	1		T130	14		T542	4
values[23]	782	1			T75	1		T130	10		T542	4
values[24]	748	1			T75	1		T130	9		T542	4
values[25]	699	1			T75	1		T130	11		T542	4
values[26]	723	1			T75	1		T130	14		T542	4
values[27]	664	1			T75	3		T130	5		T542	4
values[28]	595	1			T75	2		T130	5		T542	4
values[29]	596	1			T75	1		T130	7		T542	4
values[30]	603	1			T75	2		T130	11		T542	4
values[31]	603	1			T75	2		T130	22		T542	4
values[32]	563	1			T75	4		T130	13		T542	4
values[33]	584	1			T75	5		T130	9		T542	4
values[34]	534	1			T75	3		T130	15		T542	4
values[35]	531	1			T75	2		T130	11		T542	4
values[36]	522	1			T75	1		T130	9		T542	4
values[37]	478	1			T75	1		T130	2		T542	4
values[38]	489	1			T75	1		T542	4		T845	1
values[39]	448	1			T75	1		T542	4		T845	1
values[40]	487	1			T75	4		T542	4		T845	1
values[41]	474	1			T75	1		T542	4		T845	1
values[42]	501	1			T75	3		T542	4		T845	1
values[43]	471	1			T75	5		T542	4		T845	1
values[44]	485	1			T75	4		T542	4		T845	1
values[45]	425	1			T75	1		T542	4		T845	1
values[46]	435	1			T75	2		T542	4		T845	1
values[47]	417	1			T75	1		T542	4		T845	1
values[48]	403	1			T75	1		T542	4		T845	1
values[49]	378	1			T75	1		T542	4		T845	1
values[50]	401	1			T75	1		T542	4		T845	1
values[51]	398	1			T75	2		T542	4		T845	1
values[52]	401	1			T75	2		T542	4		T845	1
values[53]	437	1			T75	1		T542	4		T845	1
values[54]	418	1			T75	1		T542	4		T845	1
values[55]	391	1			T75	2		T542	4		T845	1
values[56]	380	1			T75	1		T542	4		T845	1
values[57]	402	1			T75	1		T542	5		T845	1
values[58]	398	1			T75	2		T542	4		T845	1
values[59]	403	1			T75	2		T542	4		T845	1
values[60]	387	1			T75	4		T542	4		T845	1
values[61]	434	1			T75	3		T542	4		T845	1
values[62]	661	1			T75	1		T542	4		T845	1
values[63]	2379	1			T75	4		T542	4		T845	1
values[64]	28880	1			T75	101		T542	844		T845	180

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	564375	1			T75	3347		T76	1		T77	1
values[2]	2875183	1			T75	19764		T76	15		T77	106
values[3]	1188647	1			T75	4207		T76	42		T77	57
values[4]	137488	1			T75	190		T76	4		T81	17
values[5]	70444	1			T75	91		T313	17		T130	491
values[6]	46471	1			T75	61		T313	12		T130	315
values[7]	34606	1			T75	57		T313	14		T130	239
values[8]	27775	1			T75	30		T313	11		T130	144
values[9]	23946	1			T75	44		T313	7		T130	89
values[10]	20658	1			T75	40		T313	4		T130	49
values[11]	19534	1			T75	48		T313	21		T130	41
values[12]	18428	1			T75	49		T313	13		T130	61
values[13]	17443	1			T75	40		T313	20		T130	44
values[14]	16448	1			T75	38		T313	28		T130	42
values[15]	15655	1			T75	36		T313	24		T130	22
values[16]	15019	1			T75	38		T313	9		T130	13
values[17]	14540	1			T75	59		T313	12		T130	12
values[18]	13842	1			T75	48		T313	13		T130	11
values[19]	13562	1			T75	39		T313	7		T130	12
values[20]	13428	1			T75	42		T313	21		T130	17
values[21]	13007	1			T75	26		T313	16		T130	17
values[22]	11998	1			T75	44		T313	15		T130	12
values[23]	11682	1			T75	48		T313	12		T130	25
values[24]	11706	1			T75	62		T313	12		T130	21
values[25]	11132	1			T75	29		T313	6		T130	15
values[26]	10380	1			T75	27		T313	19		T130	18
values[27]	9883	1			T75	45		T313	15		T130	16
values[28]	9149	1			T75	40		T313	10		T130	13
values[29]	8633	1			T75	34		T313	3		T130	15
values[30]	7903	1			T75	26		T313	9		T130	14
values[31]	7458	1			T75	40		T313	3		T130	11
values[32]	6948	1			T75	41		T313	1		T130	9
values[33]	6398	1			T75	23		T313	1		T130	8
values[34]	5878	1			T75	12		T313	1		T130	6
values[35]	5279	1			T75	3		T313	11		T130	12
values[36]	4984	1			T75	1		T313	8		T130	6
values[37]	4669	1			T75	3		T313	6		T130	13
values[38]	4270	1			T75	2		T313	5		T130	14
values[39]	4119	1			T75	1		T313	5		T130	8
values[40]	3947	1			T75	1		T313	3		T130	11
values[41]	3725	1			T75	1		T313	2		T130	4
values[42]	3684	1			T75	1		T130	5		T254	4
values[43]	3543	1			T75	1		T130	4		T254	10
values[44]	3501	1			T75	2		T130	4		T254	12
values[45]	3418	1			T75	2		T130	6		T254	4
values[46]	3426	1			T75	1		T130	5		T254	7
values[47]	3297	1			T75	2		T130	7		T254	1
values[48]	3306	1			T75	1		T130	9		T254	8
values[49]	3168	1			T75	4		T130	12		T254	1
values[50]	3054	1			T75	2		T130	17		T254	5
values[51]	3081	1			T75	3		T130	16		T254	2
values[52]	3051	1			T75	1		T130	6		T765	6
values[53]	2901	1			T75	7		T130	7		T765	6
values[54]	2826	1			T75	4		T130	6		T765	6
values[55]	2814	1			T75	1		T130	7		T765	6
values[56]	2759	1			T75	3		T130	16		T765	6
values[57]	2719	1			T75	2		T130	15		T765	6
values[58]	2660	1			T75	2		T130	8		T765	7
values[59]	2585	1			T75	3		T130	5		T765	6
values[60]	2577	1			T75	2		T130	4		T765	6
values[61]	2629	1			T75	1		T130	7		T765	6
values[62]	3443	1			T75	2		T130	19		T765	6
values[63]	8751	1			T75	2		T130	35		T765	7
values[64]	228364	1			T75	97		T130	62		T765	1273